source: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd@ 236

Last change on this file since 236 was 236, checked in by qweitzel, 11 years ago
second test for FTU added
File size: 4.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 01/07/2010
6-- Design Name:
7-- Module Name: FTU_test2_spi_interface - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library ftu_definitions;
25USE ftu_definitions.ftu_array_types.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY FTU_test2_spi_interface IS
33 PORT(
34 clk_50MHz : IN std_logic;
35 config_start : IN std_logic;
36 dac_array : IN dac_array_type;
37 config_ready : OUT std_logic;
38 config_started : OUT std_logic := '0';
39 dac_cs : OUT std_logic;
40 mosi : OUT std_logic := '0';
41 sclk : OUT std_logic;
42 miso : INOUT std_logic
43 );
44END FTU_test2_spi_interface;
45
46ARCHITECTURE struct OF FTU_test2_spi_interface IS
47
48 -- Internal signal declarations
49 SIGNAL dac_config_ready : std_logic;
50 SIGNAL dac_config_start : std_logic;
51 SIGNAL dac_id : std_logic_vector(2 DOWNTO 0);
52 SIGNAL data : std_logic_vector(15 DOWNTO 0);
53
54 -- Implicit buffer signal declarations
55 SIGNAL sclk_internal : std_logic;
56
57
58 -- Component Declarations
59 COMPONENT FTU_test2_spi_clock_generator
60 GENERIC (
61 CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz
62 );
63 PORT (
64 clk : IN std_logic;
65 sclk : OUT std_logic := '0'
66 );
67 END COMPONENT;
68
69 COMPONENT FTU_test2_spi_controller
70 PORT (
71 clk : IN std_logic;
72 dac_id : IN std_logic_vector (2 DOWNTO 0);
73 dac_start : IN std_logic;
74 dac_cs : OUT std_logic := '1';
75 dac_ready : OUT std_logic := '0';
76 mosi : OUT std_logic := '0';
77 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
78 miso : INOUT std_logic := 'Z'
79 );
80 END COMPONENT;
81
82 COMPONENT FTU_test2_spi_distributor
83 PORT (
84 clk : IN std_logic;
85 config_start : IN std_logic;
86 dac_array : IN dac_array_type;
87 dac_config_ready : IN std_logic;
88 config_ready : OUT std_logic := '0';
89 config_started : OUT std_logic := '0';
90 dac_config_start : OUT std_logic := '0';
91 dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0');
92 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z')
93 );
94 END COMPONENT;
95
96BEGIN
97
98 -- Instance port mappings.
99 Inst_FTU_test2_spi_clock_generator : FTU_test2_spi_clock_generator
100 GENERIC MAP (
101 CLK_DIVIDER => 25 --2 MHz @ 50 MHz
102 )
103 PORT MAP (
104 clk => clk_50MHz,
105 sclk => sclk_internal
106 );
107
108 Inst_FTU_test2_spi_controller : FTU_test2_spi_controller
109 PORT MAP (
110 clk => sclk_internal,
111 miso => miso,
112 mosi => mosi,
113 dac_id => dac_id,
114 data => data,
115 dac_cs => dac_cs,
116 dac_start => dac_config_start,
117 dac_ready => dac_config_ready
118 );
119
120 Inst_FTU_test2_spi_distributor : FTU_test2_spi_distributor
121 PORT MAP (
122 clk => sclk_internal,
123 config_start => config_start,
124 config_ready => config_ready,
125 config_started => config_started,
126 dac_array => dac_array,
127 dac_config_start => dac_config_start,
128 dac_config_ready => dac_config_ready,
129 dac_id => dac_id,
130 data => data
131 );
132
133 -- Implicit buffered output assignments
134 sclk <= sclk_internal;
135
136END struct;
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