source: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_tb.vhd@ 8723

Last change on this file since 8723 was 236, checked in by qweitzel, 15 years ago
second test for FTU added
File size: 6.2 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 02/07/2010
6-- Design Name:
7-- Module Name: FTU_test2_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for test2 entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_test2
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--
28-- based on testbench for FTU_test1
29--
30--------------------------------------------------------------------------------
31library IEEE;
32use IEEE.STD_LOGIC_1164.ALL;
33use IEEE.STD_LOGIC_UNSIGNED.ALL;
34use IEEE.NUMERIC_STD.ALL;
35
36entity FTU_test2_tb is
37end FTU_test2_tb;
38
39architecture behavior of FTU_test2_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTU_test2
44 port(
45 -- global control
46 ext_clk : IN STD_LOGIC; -- external clock from FTU board
47 --reset : in STD_LOGIC; -- reset
48 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
49 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address
50
51 -- rate counters LVDS inputs
52 -- use IBUFDS differential input buffer
53 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
54 patch_A_n : IN STD_LOGIC;
55 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
56 patch_B_n : IN STD_LOGIC;
57 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
58 patch_C_n : IN STD_LOGIC;
59 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
60 patch_D_n : IN STD_LOGIC;
61 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
62 trig_prim_n : IN STD_LOGIC;
63
64 -- DAC interface
65 -- miso : IN STD_LOGIC; -- master-in-slave-out
66 sck : OUT STD_LOGIC; -- serial clock to DAC
67 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
68 clr : OUT STD_LOGIC; -- clear signal to DAC
69 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
70
71 -- RS-485 interface to FTM
72 rx : IN STD_LOGIC; -- serial data from FTM
73 tx : OUT STD_LOGIC; -- serial data to FTM
74 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
75 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
76
77 -- analog buffer enable
78 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
79 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
80 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
81 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
82
83 -- testpoints
84 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
85 );
86 end component;
87
88 --Inputs
89 signal ext_clk : STD_LOGIC := '0';
90 --signal reset : STD_LOGIC := '0';
91 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
92 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
93 signal patch_A_p : STD_LOGIC := '0';
94 signal patch_A_n : STD_LOGIC := '0';
95 signal patch_B_p : STD_LOGIC := '0';
96 signal patch_B_n : STD_LOGIC := '0';
97 signal patch_C_p : STD_LOGIC := '0';
98 signal patch_C_n : STD_LOGIC := '0';
99 signal patch_D_p : STD_LOGIC := '0';
100 signal patch_D_n : STD_LOGIC := '0';
101 signal trig_prim_p : STD_LOGIC := '0';
102 signal trig_prim_n : STD_LOGIC := '0';
103 -- signal miso : STD_LOGIC := '0';
104 signal rx : STD_LOGIC := '0';
105
106 --Outputs
107 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
108 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
109 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
110 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
111 signal clr : STD_LOGIC;
112 signal cs_ld : STD_LOGIC;
113 signal sck : STD_LOGIC;
114 signal mosi : STD_LOGIC;
115 signal tx : STD_LOGIC;
116 signal rx_en : STD_LOGIC;
117 signal tx_en : STD_LOGIC;
118 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
119
120 -- Clock period definitions
121 constant ext_clk_period : TIME := 20 ns;
122
123begin
124
125 -- Instantiate the Unit Under Test (UUT)
126 uut: FTU_test2
127 port map(
128 ext_clk => ext_clk,
129 --reset => reset,
130 brd_add => brd_add,
131 brd_id => brd_id,
132 patch_A_p => patch_A_p,
133 patch_A_n => patch_A_n,
134 patch_B_p => patch_B_p,
135 patch_B_n => patch_B_n,
136 patch_C_p => patch_C_p,
137 patch_C_n => patch_C_n,
138 patch_D_p => patch_D_p,
139 patch_D_n => patch_D_n,
140 trig_prim_p => trig_prim_p,
141 trig_prim_n => trig_prim_n,
142 -- miso => miso,
143 rx => rx,
144 rx_en => rx_en,
145 enables_A => enables_A,
146 enables_B => enables_B,
147 enables_C => enables_C,
148 enables_D => enables_D,
149 clr => clr,
150 cs_ld => cs_ld,
151 sck => sck,
152 mosi => mosi,
153 tx => tx,
154 tx_en => tx_en,
155 TP_A => TP_A
156 );
157
158 -- Clock process definitions
159 ext_clk_proc: process
160 begin
161 ext_clk <= '0';
162 wait for ext_clk_period/2;
163 ext_clk <= '1';
164 wait for ext_clk_period/2;
165 end process ext_clk_proc;
166
167 -- Stimulus process
168 stim_proc: process
169 begin
170 -- hold reset state for 100ms.
171 wait for 100ms;
172
173 wait for ext_clk_period*10;
174
175 -- insert stimulus here
176
177 wait;
178 end process stim_proc;
179
180end;
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