source: FPGA/FTU/test_firmware/FTU_test3/FTU_test3_dcm.vhd @ 239

Last change on this file since 239 was 239, checked in by qweitzel, 10 years ago
FTU_test3 added to check only spi lines on PCB
File size: 2.8 KB
Line 
1--------------------------------------------------------------------------------
2-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3--------------------------------------------------------------------------------
4--   ____  ____
5--  /   /\/   /
6-- /___/  \  /    Vendor: Xilinx
7-- \   \   \/     Version : 11.1
8--  \   \         Application : xaw2vhdl
9--  /   /         Filename : FTU_test1_dcm.vhd
10-- /___/   /\     Timestamp : 05/04/2010 17:27:08
11-- \   \  /  \
12--  \___\/\___\
13--
14--Command: xaw2vhdl-st /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm.xaw /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm
15--Design Name: FTU_test1_dcm
16--Device: xc3s400an-4fgg400
17--
18-- Module FTU_test1_dcm
19-- Generated by Xilinx Architecture Wizard
20-- Written for synthesis tool: XST
21-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI
22-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns
23
24library ieee;
25use ieee.std_logic_1164.ALL;
26use ieee.numeric_std.ALL;
27library UNISIM;
28use UNISIM.Vcomponents.ALL;
29
30entity FTU_test3_dcm is
31   port ( CLKIN_IN        : in    std_logic; 
32          CLKFX_OUT       : out   std_logic; 
33          CLKIN_IBUFG_OUT : out   std_logic);
34end FTU_test3_dcm;
35
36architecture BEHAVIORAL of FTU_test3_dcm is
37   signal CLKFX_BUF       : std_logic;
38   signal CLKIN_IBUFG     : std_logic;
39   signal GND_BIT         : std_logic;
40begin
41   GND_BIT <= '0';
42   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
43   CLKFX_BUFG_INST : BUFG
44      port map (I=>CLKFX_BUF,
45                O=>CLKFX_OUT);
46   
47   CLKIN_IBUFG_INST : IBUFG
48      port map (I=>CLKIN_IN,
49                O=>CLKIN_IBUFG);
50   
51   DCM_SP_INST : DCM_SP
52   generic map( CLK_FEEDBACK => "NONE",
53            CLKDV_DIVIDE => 2.0,
54            CLKFX_DIVIDE => 20,
55            CLKFX_MULTIPLY => 2,
56            CLKIN_DIVIDE_BY_2 => FALSE,
57            CLKIN_PERIOD => 20.000,
58            CLKOUT_PHASE_SHIFT => "NONE",
59            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
60            DFS_FREQUENCY_MODE => "LOW",
61            DLL_FREQUENCY_MODE => "LOW",
62            DUTY_CYCLE_CORRECTION => TRUE,
63            FACTORY_JF => x"C080",
64            PHASE_SHIFT => 0,
65            STARTUP_WAIT => FALSE)
66      port map (CLKFB=>GND_BIT,
67                CLKIN=>CLKIN_IBUFG,
68                DSSEN=>GND_BIT,
69                PSCLK=>GND_BIT,
70                PSEN=>GND_BIT,
71                PSINCDEC=>GND_BIT,
72                RST=>GND_BIT,
73                CLKDV=>open,
74                CLKFX=>CLKFX_BUF,
75                CLKFX180=>open,
76                CLK0=>open,
77                CLK2X=>open,
78                CLK2X180=>open,
79                CLK90=>open,
80                CLK180=>open,
81                CLK270=>open,
82                LOCKED=>open,
83                PSDONE=>open,
84                STATUS=>open);
85   
86end BEHAVIORAL;
87
88
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