source: FPGA/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd@ 9621

Last change on this file since 9621 was 9621, checked in by weitzel, 14 years ago
FTU_test6 added (RS485 receiver)
File size: 6.4 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 07/30/2010
6-- Design Name:
7-- Module Name: FTU_test6_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for test6 entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_test6
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--
28-- based on testbench for FTU_test1
29--
30--------------------------------------------------------------------------------
31library IEEE;
32use IEEE.STD_LOGIC_1164.ALL;
33use IEEE.STD_LOGIC_UNSIGNED.ALL;
34use IEEE.NUMERIC_STD.ALL;
35
36entity FTU_test6_tb is
37end FTU_test6_tb;
38
39architecture behavior of FTU_test6_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTU_test6
44 port(
45 -- global control
46 ext_clk : IN STD_LOGIC; -- external clock from FTU board
47 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
48 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address
49
50 -- rate counters LVDS inputs
51 -- use IBUFDS differential input buffer
52 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
53 patch_A_n : IN STD_LOGIC;
54 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
55 patch_B_n : IN STD_LOGIC;
56 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
57 patch_C_n : IN STD_LOGIC;
58 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
59 patch_D_n : IN STD_LOGIC;
60 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
61 trig_prim_n : IN STD_LOGIC;
62
63 -- DAC interface
64 sck : OUT STD_LOGIC; -- serial clock to DAC
65 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
66 clr : OUT STD_LOGIC; -- clear signal to DAC
67 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
68
69 -- RS-485 interface to FTM
70 rx : IN STD_LOGIC; -- serial data from FTM
71 tx : OUT STD_LOGIC; -- serial data to FTM
72 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
73 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
74
75 -- analog buffer enable
76 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
78 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
79 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
80
81 -- testpoints
82 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
83 );
84 end component;
85
86 --Inputs
87 signal ext_clk : STD_LOGIC := '0';
88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
89 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
90 signal patch_A_p : STD_LOGIC := '0';
91 signal patch_A_n : STD_LOGIC := '0';
92 signal patch_B_p : STD_LOGIC := '0';
93 signal patch_B_n : STD_LOGIC := '0';
94 signal patch_C_p : STD_LOGIC := '0';
95 signal patch_C_n : STD_LOGIC := '0';
96 signal patch_D_p : STD_LOGIC := '0';
97 signal patch_D_n : STD_LOGIC := '0';
98 signal trig_prim_p : STD_LOGIC := '0';
99 signal trig_prim_n : STD_LOGIC := '0';
100 signal rx : STD_LOGIC := '0';
101
102 --Outputs
103 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
104 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
105 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
106 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
107 signal clr : STD_LOGIC;
108 signal cs_ld : STD_LOGIC;
109 signal sck : STD_LOGIC;
110 signal mosi : STD_LOGIC;
111 signal tx : STD_LOGIC;
112 signal rx_en : STD_LOGIC;
113 signal tx_en : STD_LOGIC;
114 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
115
116 -- Clock period definitions
117 constant ext_clk_period : TIME := 20 ns;
118
119begin
120
121 -- Instantiate the Unit Under Test (UUT)
122 uut: FTU_test6
123 port map(
124 ext_clk => ext_clk,
125 brd_add => brd_add,
126 brd_id => brd_id,
127 patch_A_p => patch_A_p,
128 patch_A_n => patch_A_n,
129 patch_B_p => patch_B_p,
130 patch_B_n => patch_B_n,
131 patch_C_p => patch_C_p,
132 patch_C_n => patch_C_n,
133 patch_D_p => patch_D_p,
134 patch_D_n => patch_D_n,
135 trig_prim_p => trig_prim_p,
136 trig_prim_n => trig_prim_n,
137 rx => rx,
138 rx_en => rx_en,
139 enables_A => enables_A,
140 enables_B => enables_B,
141 enables_C => enables_C,
142 enables_D => enables_D,
143 clr => clr,
144 cs_ld => cs_ld,
145 sck => sck,
146 mosi => mosi,
147 tx => tx,
148 tx_en => tx_en,
149 TP_A => TP_A
150 );
151
152 -- Clock process definitions
153 ext_clk_proc: process
154 begin
155 ext_clk <= '0';
156 wait for ext_clk_period/2;
157 ext_clk <= '1';
158 wait for ext_clk_period/2;
159 end process ext_clk_proc;
160
161 -- Stimulus process
162 stim_proc: process
163 begin
164 -- hold reset state for 100ms.
165 --wait for 100ms;
166
167 wait for ext_clk_period*10;
168
169 rx <= '1'; --start bit
170 wait for ext_clk_period*5;
171 rx <= '1';
172 wait for ext_clk_period*5;
173 rx <= '0';
174 wait for ext_clk_period*5;
175 rx <= '0';
176 wait for ext_clk_period*5;
177 rx <= '0';
178 wait for ext_clk_period*5;
179 rx <= '1';
180 wait for ext_clk_period*5;
181 rx <= '1';
182 wait for ext_clk_period*5;
183 rx <= '0';
184 wait for ext_clk_period*5;
185 rx <= '0';
186 wait for ext_clk_period*5;
187 rx <= '0'; --parity bit
188 wait for ext_clk_period*5;
189 rx <= '1'; --stop bit
190
191 wait;
192 end process stim_proc;
193
194end;
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