source: drsdaq/VME/struck/sis1100/V2.02/dev/pci/f1_map.h@ 23

Last change on this file since 23 was 22, checked in by ogrimm, 16 years ago
First commit of drsdaq program
File size: 3.1 KB
Line 
1/* $ZEL: f1_map.h,v 1.2 2004/05/27 23:10:14 wuestner Exp $ */
2
3/*
4 * Copyright (c) 2004
5 * Peter Wuestner. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _straw_map_h_
30#define _straw_map_h_
31
32struct straw_cm_regs {
33 u_int32_t ident;
34 u_int32_t sr; /* Status Register */
35#define SR_EVENT 0x0010L
36#define SR_DATA_AVAIL 0x0020L
37#define SR_ATTENT 0x0040L
38
39 u_int32_t cr; /* Control Register, 4 bit */
40/* noch unbenutzt */
41
42 u_int32_t res1;
43 u_int32_t jtag_csr; /* JTAG control/status */
44 u_int32_t jtag_data; /* JTAG data */
45};
46
47struct straw_reg {
48 u_int32_t ident;
49 u_int32_t sc;
50 u_int32_t optical_cr;
51 u_int32_t dsp_sc;
52 u_int32_t dummy;
53};
54
55/* bits in in_out */
56#define straw_io_flat_out1 (1<<0)
57#define straw_io_flat_out2 (1<<1)
58#define straw_io_flat_out3 (1<<2)
59#define straw_io_flat_out4 (1<<3)
60#define straw_io_lemo_out1 (1<<4)
61#define straw_io_lemo_out2 (1<<5)
62#define straw_io_lemo_out3 (1<<6)
63/* clear is (io_*_out?)<<16 */
64#define straw_io_flat_in1 (1<<16)
65#define straw_io_flat_in2 (1<<17)
66#define straw_io_flat_in3 (1<<18)
67#define straw_io_flat_in4 (1<<19)
68#define straw_io_lemo_in1 (1<<20)
69#define straw_io_lemo_in2 (1<<21)
70#define straw_io_lemo_in3 (1<<22)
71
72/* bits in dsp_sc */
73#define straw_dsp_run (1<<8)
74#define straw_dsp_boot_eprom (1<<9)
75#define straw_dsp_boot_ctrl (1<<11)
76
77#define straw_dsp_available (1<<24)
78#define straw_dsp_flag0 (1<<28)
79#define straw_dsp_flag1 (1<<29)
80#define straw_dsp_flag2 (1<<30)
81#define straw_dsp_flag3 (1<<31)
82
83/* error codes */
84#define straw_sis3100_re_berr 0x211 /* Bus Error */
85#define straw_sis3100_re_retr 0x212 /* Retry */
86#define straw_sis3100_re_atimeout 0x214 /* Arbitration timeout */
87
88#endif
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