| 1 | /* $ZEL: sis1100_map.h,v 1.4 2004/05/27 23:10:25 wuestner Exp $ */
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| 2 |
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| 3 | /*
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| 4 | * Copyright (c) 2001-2004
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| 5 | * Peter Wuestner. All rights reserved.
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| 6 | *
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| 7 | * Redistribution and use in source and binary forms, with or without
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| 8 | * modification, are permitted provided that the following conditions
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| 9 | * are met:
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| 10 | * 1. Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions, and the following disclaimer.
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| 12 | * 2. Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | *
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| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
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| 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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| 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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| 26 | * SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #ifndef _sis1100_map_h_
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| 30 | #define _sis1100_map_h_
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| 31 |
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| 32 | struct sis1100_reg {
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| 33 | u_int32_t ident;
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| 34 | u_int32_t sr;
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| 35 | u_int32_t cr;
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| 36 | u_int32_t semaphore;
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| 37 | u_int32_t doorbell;
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| 38 | u_int32_t res0[3];
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| 39 | u_int32_t mailbox[8];
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| 40 | u_int32_t res1[16];
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| 41 | u_int32_t t_hdr;
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| 42 | u_int32_t t_am;
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| 43 | u_int32_t t_adl;
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| 44 | u_int32_t t_adh;
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| 45 | u_int32_t t_dal;
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| 46 | u_int32_t t_dah;
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| 47 | u_int32_t res2;
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| 48 | u_int32_t tc_hdr;
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| 49 | u_int32_t tc_dal;
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| 50 | u_int32_t tc_dah;
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| 51 | u_int32_t p_balance;
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| 52 | u_int32_t prot_error;
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| 53 | u_int32_t d0_bc;
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| 54 | u_int32_t d0_bc_buf;
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| 55 | u_int32_t d0_bc_blen;
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| 56 | u_int32_t d_hdr;
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| 57 | u_int32_t d_am;
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| 58 | u_int32_t d_adl;
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| 59 | u_int32_t d_adh;
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| 60 | u_int32_t d_bc;
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| 61 | u_int32_t res4[2];
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| 62 | u_int32_t rd_pipe_buf;
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| 63 | u_int32_t rd_pipe_blen;
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| 64 | u_int32_t res5[2];
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| 65 | u_int32_t tp_special;
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| 66 | u_int32_t tp_data;
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| 67 | u_int32_t opt_csr;
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| 68 | union jtag_csr {
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| 69 | u_int32_t jtag_csrl;
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| 70 | u_int8_t jtag_csrb[4];
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| 71 | } jtag_csr;
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| 72 | u_int32_t jtag_data;
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| 73 | u_int32_t res6[1];
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| 74 | u_int32_t mailext[192];
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| 75 |
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| 76 | struct {
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| 77 | u_int32_t hdr;
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| 78 | u_int32_t am;
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| 79 | u_int32_t adl;
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| 80 | u_int32_t adh;
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| 81 | } sp1_descr[64];
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| 82 | };
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| 83 |
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| 84 | /* irq bits in sr and cr */
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| 85 | #define irq_synch_chg (1<< 4)
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| 86 | #define irq_inh_chg (1<< 5)
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| 87 | #define irq_sema_chg (1<< 6)
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| 88 | #define irq_rec_violation (1<< 7)
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| 89 | #define irq_reset_req (1<< 8)
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| 90 | #define irq_dma_eot (1<< 9)
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| 91 | #define irq_mbx0 (1<<10)
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| 92 | /*#define irq_s_xoff (1<<11)*/
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| 93 | #define irq_lemo_in_0_chg (1<<12)
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| 94 | #define irq_lemo_in_1_chg (1<<13)
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| 95 | #define irq_lemo_in_chg (irq_lemo_in_0_chg|irq_lemo_in_1_chg)
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| 96 | #define irq_prot_end (1<<14)
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| 97 | #define irq_prot_l_err (1<<15)
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| 98 |
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| 99 | #define sis1100_all_irq 0xfff0
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| 100 |
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| 101 | /* bits in sr (without irqs) */
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| 102 | #define sr_rx_synch (1<<0)
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| 103 | #define sr_tx_synch (1<<1)
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| 104 | #define sr_synch (sr_rx_synch|sr_tx_synch)
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| 105 | #define sr_inhibit (1<<2)
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| 106 | #define sr_configured (1<<3)
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| 107 | #define sr_dma0_blocked (1<<16)
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| 108 | #define sr_no_pread_buf (1<<17)
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| 109 | #define sr_prot_err (1<<18)
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| 110 | #define sr_bus_tout (1<<19)
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| 111 | #define sr_tp_special (1<<20)
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| 112 | #define sr_tp_data (1<<21)
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| 113 | #define sr_abort_dma (1<<31)
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| 114 |
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| 115 | /* bits in cr (without irqs) */
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| 116 | #define cr_reset (1<<0)
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| 117 | #define cr_transparent (1<<1)
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| 118 | #define cr_ready (1<<2)
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| 119 | #define cr_bigendian (1<<3)
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| 120 | #define cr_rem_reset (1<<16)
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| 121 |
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| 122 | /* bits in opt_csr (without "internals") */
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| 123 | #define opt_lemo_out_0 (1<<4)
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| 124 | #define opt_lemo_out_1 (1<<5)
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| 125 | #define opt_led_0 (1<<6)
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| 126 | #define opt_led_1 (1<<7)
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| 127 | #define opt_lemo_in_0 (1<<8)
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| 128 | #define opt_lemo_in_1 (1<<9)
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| 129 |
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| 130 | /* error codes */
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| 131 | #define sis1100_e_dlock 0x005
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| 132 | #define sis1100_le_synch 0x101
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| 133 | #define sis1100_le_nrdy 0x102
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| 134 | #define sis1100_le_xoff 0x103
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| 135 | #define sis1100_le_resource 0x104
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| 136 | #define sis1100_le_dlock 0x105
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| 137 | #define sis1100_le_to 0x107
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| 138 | #define sis1100_re_nrdy 0x202
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| 139 | #define sis1100_re_prot 0x206
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| 140 | #define sis1100_re_to 0x207
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| 141 | #define sis1100_re_berr 0x208
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| 142 | #define sis1100_re_ferr 0x209
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| 143 |
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| 144 | #endif
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