1 | /* $ZEL: sis1100_map.h,v 1.4 2004/05/27 23:10:25 wuestner Exp $ */
|
---|
2 |
|
---|
3 | /*
|
---|
4 | * Copyright (c) 2001-2004
|
---|
5 | * Peter Wuestner. All rights reserved.
|
---|
6 | *
|
---|
7 | * Redistribution and use in source and binary forms, with or without
|
---|
8 | * modification, are permitted provided that the following conditions
|
---|
9 | * are met:
|
---|
10 | * 1. Redistributions of source code must retain the above copyright
|
---|
11 | * notice, this list of conditions, and the following disclaimer.
|
---|
12 | * 2. Redistributions in binary form must reproduce the above copyright
|
---|
13 | * notice, this list of conditions and the following disclaimer in the
|
---|
14 | * documentation and/or other materials provided with the distribution.
|
---|
15 | *
|
---|
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
|
---|
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
---|
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
---|
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
---|
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
---|
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
---|
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
---|
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
---|
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
---|
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
---|
26 | * SUCH DAMAGE.
|
---|
27 | */
|
---|
28 |
|
---|
29 | #ifndef _sis1100_map_h_
|
---|
30 | #define _sis1100_map_h_
|
---|
31 |
|
---|
32 | struct sis1100_reg {
|
---|
33 | u_int32_t ident;
|
---|
34 | u_int32_t sr;
|
---|
35 | u_int32_t cr;
|
---|
36 | u_int32_t semaphore;
|
---|
37 | u_int32_t doorbell;
|
---|
38 | u_int32_t res0[3];
|
---|
39 | u_int32_t mailbox[8];
|
---|
40 | u_int32_t res1[16];
|
---|
41 | u_int32_t t_hdr;
|
---|
42 | u_int32_t t_am;
|
---|
43 | u_int32_t t_adl;
|
---|
44 | u_int32_t t_adh;
|
---|
45 | u_int32_t t_dal;
|
---|
46 | u_int32_t t_dah;
|
---|
47 | u_int32_t res2;
|
---|
48 | u_int32_t tc_hdr;
|
---|
49 | u_int32_t tc_dal;
|
---|
50 | u_int32_t tc_dah;
|
---|
51 | u_int32_t p_balance;
|
---|
52 | u_int32_t prot_error;
|
---|
53 | u_int32_t d0_bc;
|
---|
54 | u_int32_t d0_bc_buf;
|
---|
55 | u_int32_t d0_bc_blen;
|
---|
56 | u_int32_t d_hdr;
|
---|
57 | u_int32_t d_am;
|
---|
58 | u_int32_t d_adl;
|
---|
59 | u_int32_t d_adh;
|
---|
60 | u_int32_t d_bc;
|
---|
61 | u_int32_t res4[2];
|
---|
62 | u_int32_t rd_pipe_buf;
|
---|
63 | u_int32_t rd_pipe_blen;
|
---|
64 | u_int32_t res5[2];
|
---|
65 | u_int32_t tp_special;
|
---|
66 | u_int32_t tp_data;
|
---|
67 | u_int32_t opt_csr;
|
---|
68 | union jtag_csr {
|
---|
69 | u_int32_t jtag_csrl;
|
---|
70 | u_int8_t jtag_csrb[4];
|
---|
71 | } jtag_csr;
|
---|
72 | u_int32_t jtag_data;
|
---|
73 | u_int32_t res6[1];
|
---|
74 | u_int32_t mailext[192];
|
---|
75 |
|
---|
76 | struct {
|
---|
77 | u_int32_t hdr;
|
---|
78 | u_int32_t am;
|
---|
79 | u_int32_t adl;
|
---|
80 | u_int32_t adh;
|
---|
81 | } sp1_descr[64];
|
---|
82 | };
|
---|
83 |
|
---|
84 | /* irq bits in sr and cr */
|
---|
85 | #define irq_synch_chg (1<< 4)
|
---|
86 | #define irq_inh_chg (1<< 5)
|
---|
87 | #define irq_sema_chg (1<< 6)
|
---|
88 | #define irq_rec_violation (1<< 7)
|
---|
89 | #define irq_reset_req (1<< 8)
|
---|
90 | #define irq_dma_eot (1<< 9)
|
---|
91 | #define irq_mbx0 (1<<10)
|
---|
92 | /*#define irq_s_xoff (1<<11)*/
|
---|
93 | #define irq_lemo_in_0_chg (1<<12)
|
---|
94 | #define irq_lemo_in_1_chg (1<<13)
|
---|
95 | #define irq_lemo_in_chg (irq_lemo_in_0_chg|irq_lemo_in_1_chg)
|
---|
96 | #define irq_prot_end (1<<14)
|
---|
97 | #define irq_prot_l_err (1<<15)
|
---|
98 |
|
---|
99 | #define sis1100_all_irq 0xfff0
|
---|
100 |
|
---|
101 | /* bits in sr (without irqs) */
|
---|
102 | #define sr_rx_synch (1<<0)
|
---|
103 | #define sr_tx_synch (1<<1)
|
---|
104 | #define sr_synch (sr_rx_synch|sr_tx_synch)
|
---|
105 | #define sr_inhibit (1<<2)
|
---|
106 | #define sr_configured (1<<3)
|
---|
107 | #define sr_dma0_blocked (1<<16)
|
---|
108 | #define sr_no_pread_buf (1<<17)
|
---|
109 | #define sr_prot_err (1<<18)
|
---|
110 | #define sr_bus_tout (1<<19)
|
---|
111 | #define sr_tp_special (1<<20)
|
---|
112 | #define sr_tp_data (1<<21)
|
---|
113 | #define sr_abort_dma (1<<31)
|
---|
114 |
|
---|
115 | /* bits in cr (without irqs) */
|
---|
116 | #define cr_reset (1<<0)
|
---|
117 | #define cr_transparent (1<<1)
|
---|
118 | #define cr_ready (1<<2)
|
---|
119 | #define cr_bigendian (1<<3)
|
---|
120 | #define cr_rem_reset (1<<16)
|
---|
121 |
|
---|
122 | /* bits in opt_csr (without "internals") */
|
---|
123 | #define opt_lemo_out_0 (1<<4)
|
---|
124 | #define opt_lemo_out_1 (1<<5)
|
---|
125 | #define opt_led_0 (1<<6)
|
---|
126 | #define opt_led_1 (1<<7)
|
---|
127 | #define opt_lemo_in_0 (1<<8)
|
---|
128 | #define opt_lemo_in_1 (1<<9)
|
---|
129 |
|
---|
130 | /* error codes */
|
---|
131 | #define sis1100_e_dlock 0x005
|
---|
132 | #define sis1100_le_synch 0x101
|
---|
133 | #define sis1100_le_nrdy 0x102
|
---|
134 | #define sis1100_le_xoff 0x103
|
---|
135 | #define sis1100_le_resource 0x104
|
---|
136 | #define sis1100_le_dlock 0x105
|
---|
137 | #define sis1100_le_to 0x107
|
---|
138 | #define sis1100_re_nrdy 0x202
|
---|
139 | #define sis1100_re_prot 0x206
|
---|
140 | #define sis1100_re_to 0x207
|
---|
141 | #define sis1100_re_berr 0x208
|
---|
142 | #define sis1100_re_ferr 0x209
|
---|
143 |
|
---|
144 | #endif
|
---|