source: fact/drsdaq/DRS/DRS.h

Last change on this file was 176, checked in by ogrimm, 15 years ago
Migrated to DRS4. DRS class does not run with DRS2 FPGA firmware anymore.
File size: 34.0 KB
Line 
1/********************************************************************
2 DRS.h, S.Ritt, M. Schneebeli - PSI
3
4 $Id: DRS.h 14428 2009-10-19 12:59:46Z ritt $
5
6********************************************************************/
7#ifndef DRS_H
8#define DRS_H
9#include <stdio.h>
10#include <string.h>
11
12#ifdef HAVE_LIBUSB
13# ifndef HAVE_USB
14# define HAVE_USB
15# endif
16#endif
17
18#ifdef HAVE_USB
19# include <musbstd.h>
20#endif // HAVE_USB
21
22#ifdef HAVE_VME
23# include <mvmestd.h>
24#endif // HAVE_VME
25
26// Concurrent Technologies VME single board computer
27#ifdef CT_VME
28 #include "rcc_error/rcc_error.h" // Error reporting
29 #include "vme_rcc/vme_rcc.h" // VME access
30 #include "cmem_rcc/cmem_rcc.h" // Allocation of contiguous memory
31#endif
32
33/* disable "deprecated" warning */
34#ifdef _MSC_VER
35#pragma warning(disable: 4996)
36#endif
37
38#ifndef NULL
39#define NULL 0
40#endif
41
42/* transport mode */
43#define TR_VME 1
44#define TR_USB 2
45#define TR_USB2 3
46
47/* address types */
48#ifndef T_CTRL
49#define T_CTRL 1
50#define T_STATUS 2
51#define T_RAM 3
52#define T_FIFO 4
53#endif
54
55/*---- Register addresses ------------------------------------------*/
56
57#define REG_CTRL 0x00000 /* 32 bit control reg */
58#define REG_DAC_OFS 0x00004
59#define REG_DAC0 0x00004
60#define REG_DAC1 0x00006
61#define REG_DAC2 0x00008
62#define REG_DAC3 0x0000A
63#define REG_DAC4 0x0000C
64#define REG_DAC5 0x0000E
65#define REG_DAC6 0x00010
66#define REG_DAC7 0x00012
67#define REG_CHANNEL_CONFIG 0x00014 // low byte
68#define REG_CONFIG 0x00014 // high byte
69#define REG_CHANNEL_MODE 0x00016
70#define REG_ADCCLK_PHASE 0x00016
71#define REG_FREQ_SET_HI 0x00018 // DRS2
72#define REG_FREQ_SET_LO 0x0001A // DRS2
73#define REG_TRG_DELAY 0x00018 // DRS4
74#define REG_FREQ_SET 0x0001A // DRS4
75#define REG_TRIG_DELAY 0x0001C
76#define REG_LMK_MSB 0x0001C // DRS4 Mezz
77#define REG_CALIB_TIMING 0x0001E // DRS2
78#define REG_EEPROM_PAGE_EVAL 0x0001E // DRS4 Eval
79#define REG_EEPROM_PAGE_MEZZ 0x0001A // DRS4 Mezz
80#define REG_LMK_LSB 0x0001E // DRS4 Mezz
81#define REG_WARMUP 0x00020 // DRS4 Mezz
82#define REG_COOLDOWN 0x00022 // DRS4 Mezz
83
84#define REG_MAGIC 0x00000
85#define REG_BOARD_TYPE 0x00002
86#define REG_STATUS 0x00004
87#define REG_RDAC_OFS 0x0000E
88#define REG_RDAC0 0x00008
89#define REG_STOP_CELL0 0x00008
90#define REG_RDAC1 0x0000A
91#define REG_STOP_CELL1 0x0000A
92#define REG_RDAC2 0x0000C
93#define REG_STOP_CELL2 0x0000C
94#define REG_RDAC3 0x0000E
95#define REG_STOP_CELL3 0x0000E
96#define REG_RDAC4 0x00000
97#define REG_RDAC5 0x00002
98#define REG_RDAC6 0x00014
99#define REG_RDAC7 0x00016
100#define REG_EVENTS_IN_FIFO 0x00018
101#define REG_EVENT_COUNT 0x0001A
102#define REG_FREQ1 0x0001C
103#define REG_FREQ2 0x0001E
104#define REG_TEMPERATURE 0x00020
105#define REG_TRIGGER_BUS 0x00022
106#define REG_SERIAL_BOARD 0x00024
107#define REG_VERSION_FW 0x00026
108
109/*---- Control register bit definitions ----------------------------*/
110
111#define BIT_START_TRIG (1<<0) // write a "1" to start domino wave
112#define BIT_REINIT_TRIG (1<<1) // write a "1" to stop & reset DRS
113#define BIT_SOFT_TRIG (1<<2) // write a "1" to stop and read data to RAM
114#define BIT_EEPROM_WRITE_TRIG (1<<3) // write a "1" to write into serial EEPROM
115#define BIT_EEPROM_READ_TRIG (1<<4) // write a "1" to read from serial EEPROM
116#define BIT_AUTOSTART (1<<16)
117#define BIT_DMODE (1<<17) // (*DRS2*) 0: single shot, 1: circular
118#define BIT_LED (1<<18) // 1=on, 0=blink during readout
119#define BIT_TCAL_EN (1<<19) // switch on (1) / off (0) for 33 MHz calib signal
120#define BIT_TCAL_SOURCE (1<<20)
121#define BIT_REFCLK_SOURCE (1<<20)
122#define BIT_FREQ_AUTO_ADJ (1<<21) // DRS2/3
123#define BIT_TRANSP_MODE (1<<21) // DRS4
124#define BIT_ENABLE_TRIGGER1 (1<<22) // External LEMO/FP/TRBUS trigger
125#define BIT_LONG_START_PULSE (1<<23) // (*DRS2*) 0:short start pulse (>0.8GHz), 1:long start pulse (<0.8GHz)
126#define BIT_READOUT_MODE (1<<23) // (*DRS3*,*DRS4*) 0:start from first bin, 1:start from domino stop
127#define BIT_DELAYED_START (1<<24) // DRS2: start domino wave 400ns after soft trigger, used for waveform
128 // generator startup
129#define BIT_NEG_TRIGGER (1<<24) // DRS4: use high-to-low trigger if set
130#define BIT_ACAL_EN (1<<25) // connect DRS to inputs (0) or to DAC6 (1)
131#define BIT_TRIGGER_DELAYED (1<<26) // select delayed trigger from trigger bus
132#define BIT_ADCCLK_INVERT (1<<26) // invert ADC clock
133#define BIT_DACTIVE (1<<27) // keep domino wave running during readout
134#define BIT_STANDBY_MODE (1<<28) // put chip in standby mode
135#define BIT_TR_SOURCE1 (1<<29) // trigger source selection bits
136#define BIT_TR_SOURCE2 (1<<30) // trigger source selection bits
137#define BIT_ENABLE_TRIGGER2 (1<<31) // analog threshold (internal) trigger
138
139/* DRS4 configuration register bit definitions */
140#define BIT_CONFIG_DMODE (1<<8) // 0: single shot, 1: circular
141#define BIT_CONFIG_PLLEN (1<<9) // write a "1" to enable the internal PLL
142#define BIT_CONFIG_WSRLOOP (1<<10) // write a "1" to connect WSROUT to WSRIN internally
143
144/*---- Status register bit definitions -----------------------------*/
145
146#define BIT_RUNNING (1<<0) // one if domino wave running or readout in progress
147#define BIT_NEW_FREQ1 (1<<1) // one if new frequency measurement available
148#define BIT_NEW_FREQ2 (1<<2)
149#define BIT_PLL_LOCKED0 (1<<1) // 1 if PLL has locked (DRS4 evaluation board only)
150#define BIT_PLL_LOCKED1 (1<<2) // 1 if PLL DRS4 B has locked (DRS4 mezzanine board only)
151#define BIT_PLL_LOCKED2 (1<<3) // 1 if PLL DRS4 C has locked (DRS4 mezzanine board only)
152#define BIT_PLL_LOCKED3 (1<<4) // 1 if PLL DRS4 D has locked (DRS4 mezzanine board only)
153#define BIT_SERIAL_BUSY (1<<5) // 1 if EEPROM operation in progress
154#define BIT_LMK_LOCKED (1<<6) // 1 if PLL of LMK chip has locked (DRS4 mezzanine board only)
155
156enum DRSBoardConstants {
157 kNumberOfChannelsMax = 10,
158 kNumberOfCalibChannelsV3 = 10,
159 kNumberOfCalibChannelsV4 = 8,
160 kNumberOfBins = 1024,
161 kNumberOfChipsMax = 4,
162 kFrequencyCacheSize = 10,
163 kBSplineOrder = 4,
164 kPreCaliculatedBSplines = 1000,
165 kPreCaliculatedBSplineGroups = 5,
166 kNumberOfADCBins = 4096,
167 kBSplineXMinOffset = 20,
168 kMaxNumberOfClockCycles = 100,
169};
170
171enum DRSErrorCodes {
172 kSuccess = 0,
173 kInvalidTriggerSignal = -1,
174 kWrongChannelOrChip = -2,
175 kInvalidTransport = -3,
176 kZeroSuppression = -4,
177 kWaveNotAvailable = -5
178};
179
180/*---- callback class ----*/
181
182class DRSCallback
183{
184public:
185 virtual void Progress(int value) = 0;
186 virtual ~DRSCallback() {};
187};
188
189/*------------------------*/
190
191class DRSBoard;
192
193class ResponseCalibration {
194protected:
195
196 class CalibrationData {
197 public:
198 class CalibrationDataChannel {
199 public:
200 unsigned char fLimitGroup[kNumberOfBins]; //!
201 float fMin[kNumberOfBins]; //!
202 float fRange[kNumberOfBins]; //!
203 short fOffset[kNumberOfBins]; //!
204 short fGain[kNumberOfBins]; //!
205 unsigned short fOffsetADC[kNumberOfBins]; //!
206 short *fData[kNumberOfBins]; //!
207 unsigned char *fLookUp[kNumberOfBins]; //!
208 unsigned short fLookUpOffset[kNumberOfBins]; //!
209 unsigned char fNumberOfLookUpPoints[kNumberOfBins]; //!
210 float *fTempData; //!
211
212 private:
213 CalibrationDataChannel(const CalibrationDataChannel &c); // not implemented
214 CalibrationDataChannel &operator=(const CalibrationDataChannel &rhs); // not implemented
215
216 public:
217 CalibrationDataChannel(int numberOfGridPoints)
218 :fTempData(new float[numberOfGridPoints]) {
219 int i;
220 for (i = 0; i < kNumberOfBins; i++) {
221 fData[i] = new short[numberOfGridPoints];
222 }
223 memset(fLimitGroup, 0, sizeof(fLimitGroup));
224 memset(fMin, 0, sizeof(fMin));
225 memset(fRange, 0, sizeof(fRange));
226 memset(fOffset, 0, sizeof(fOffset));
227 memset(fGain, 0, sizeof(fGain));
228 memset(fOffsetADC, 0, sizeof(fOffsetADC));
229 memset(fLookUp, 0, sizeof(fLookUp));
230 memset(fLookUpOffset, 0, sizeof(fLookUpOffset));
231 memset(fNumberOfLookUpPoints, 0, sizeof(fNumberOfLookUpPoints));
232 }
233 ~CalibrationDataChannel() {
234 int i;
235 delete fTempData;
236 for (i = 0; i < kNumberOfBins; i++) {
237 delete fData[i];
238 delete fLookUp[i];
239 }
240 }
241 };
242
243 bool fRead; //!
244 CalibrationDataChannel *fChannel[10]; //!
245 unsigned char fNumberOfGridPoints; //!
246 int fHasOffsetCalibration; //!
247 float fStartTemperature; //!
248 float fEndTemperature; //!
249 int *fBSplineOffsetLookUp[kNumberOfADCBins]; //!
250 float **fBSplineLookUp[kNumberOfADCBins]; //!
251 float fMin; //!
252 float fMax; //!
253 unsigned char fNumberOfLimitGroups; //!
254 static float fIntRevers[2 * kBSplineOrder - 2];
255
256 private:
257 CalibrationData(const CalibrationData &c); // not implemented
258 CalibrationData &operator=(const CalibrationData &rhs); // not implemented
259
260 public:
261 CalibrationData(int numberOfGridPoints);
262 ~CalibrationData();
263 static int CalculateBSpline(int nGrid, float value, float *bsplines);
264 void PreCalculateBSpline();
265 void DeletePreCalculatedBSpline();
266 };
267
268 // General Fields
269 DRSBoard *fBoard;
270
271 double fPrecision;
272
273 // Fields for creating the Calibration
274 bool fInitialized;
275 bool fRecorded;
276 bool fFitted;
277 bool fOffset;
278 bool fCalibrationValid[2];
279
280 int fNumberOfPointsLowVolt;
281 int fNumberOfPoints;
282 int fNumberOfMode2Bins;
283 int fNumberOfSamples;
284 int fNumberOfGridPoints;
285 int fNumberOfXConstPoints;
286 int fNumberOfXConstGridPoints;
287 double fTriggerFrequency;
288 int fShowStatistics;
289 FILE *fCalibFile;
290
291 int fCurrentLowVoltPoint;
292 int fCurrentPoint;
293 int fCurrentSample;
294 int fCurrentFitChannel;
295 int fCurrentFitBin;
296
297 float *fResponseX[10][kNumberOfBins];
298 float *fResponseY;
299 unsigned short **fWaveFormMode3[10];
300 unsigned short **fWaveFormMode2[10];
301 short **fWaveFormOffset[10];
302 unsigned short **fWaveFormOffsetADC[10];
303 unsigned short *fSamples;
304 int *fSampleUsed;
305
306 float *fPntX[2];
307 float *fPntY[2];
308 float *fUValues[2];
309 float *fRes[kNumberOfBins];
310 float *fResX[kNumberOfBins];
311
312 double *fXXFit;
313 double *fYYFit;
314 double *fWWFit;
315 double *fYYFitRes;
316 double *fYYSave;
317 double *fXXSave;
318 double fGainMin;
319 double fGainMax;
320
321 float **fStatisticsApprox;
322 float **fStatisticsApproxExt;
323
324 // Fields for applying the Calibration
325 CalibrationData *fCalibrationData[kNumberOfChipsMax];
326
327private:
328 ResponseCalibration(const ResponseCalibration &c); // not implemented
329 ResponseCalibration &operator=(const ResponseCalibration &rhs); // not implemented
330
331public:
332 ResponseCalibration(DRSBoard* board);
333 ~ResponseCalibration();
334
335 void SetCalibrationParameters(int numberOfPointsLowVolt, int numberOfPoints, int numberOfMode2Bins,
336 int numberOfSamples, int numberOfGridPoints, int numberOfXConstPoints,
337 int numberOfXConstGridPoints, double triggerFrequency, int showStatistics = 0);
338 void ResetCalibration();
339 bool RecordCalibrationPoints(int chipNumber);
340 bool RecordCalibrationPointsV3(int chipNumber);
341 bool RecordCalibrationPointsV4(int chipNumber);
342 bool FitCalibrationPoints(int chipNumber);
343 bool FitCalibrationPointsV3(int chipNumber);
344 bool FitCalibrationPointsV4(int chipNumber);
345 bool OffsetCalibration(int chipNumber);
346 bool OffsetCalibrationV3(int chipNumber);
347 bool OffsetCalibrationV4(int chipNumber);
348 double GetTemperature(unsigned int chipIndex);
349
350 bool WriteCalibration(unsigned int chipIndex);
351 bool WriteCalibrationV3(unsigned int chipIndex);
352 bool WriteCalibrationV4(unsigned int chipIndex);
353 bool ReadCalibration(unsigned int chipIndex);
354 bool ReadCalibrationV3(unsigned int chipIndex);
355 bool ReadCalibrationV4(unsigned int chipIndex);
356 bool Calibrate(unsigned int chipIndex, unsigned int channel, float *adcWaveform,
357 float *uWaveform, float threshold, bool offsetCalib);
358 bool Calibrate(unsigned int chipIndex, unsigned int channel, unsigned short *adcWaveform, short *uWaveform,
359 int triggerCell, float threshold, bool offsetCalib);
360 bool SubtractADCOffset(unsigned int chipIndex, unsigned int channel, unsigned short *adcWaveform,
361 unsigned short *adcCalibratedWaveform, unsigned short newBaseLevel);
362 bool IsRead(int chipIndex) const { return fCalibrationValid[chipIndex]; }
363 double GetPrecision() const { return fPrecision; };
364
365 double GetOffsetAt(int chip,int chn,int bin) const { return fCalibrationData[chip]->fChannel[chn]->fOffset[bin]; };
366 double GetGainAt(int chip,int chn,int bin) const { return fCalibrationData[chip]->fChannel[chn]->fGain[bin]; };
367 double GetMeasPointXAt(int ip) const { return fXXSave[ip]; };
368 double GetMeasPointYAt(int ip) const { return fYYSave[ip]; };
369
370protected:
371 void InitFields(int numberOfPointsLowVolt, int numberOfPoints, int numberOfMode2Bins, int numberOfSamples,
372 int numberOfGridPoints, int numberOfXConstPoints, int numberOfXConstGridPoints,
373 double triggerFrequency, int showStatistics);
374 void DeleteFields();
375 void CalibrationTrigger(int mode, double voltage);
376 void CalibrationStart(double voltage);
377
378 static float GetValue(float *coefficients, float u, int n);
379 static int Approx(float *p, float *uu, int np, int nu, float *coef);
380 static void LeastSquaresAccumulation(float **matrix, int nb, int *ip, int *ir, int mt, int jt);
381 static int LeastSquaresSolving(float **matrix, int nb, int ip, int ir, float *x, int n);
382 static void Housholder(int lpivot, int l1, int m, float **u, int iU1, int iU2, float *up, float **c, int iC1,
383 int iC2, int ice, int ncv);
384
385 static int MakeDir(const char *path);
386 static void Average(int method,float *samples,int numberOfSamples,float &mean,float &error,float sigmaBoundary);
387};
388
389
390class DRSBoard {
391protected:
392 class TimeData {
393 public:
394 class FrequencyData {
395 public:
396 int fFrequency;
397 double fBin[kNumberOfBins];
398 };
399
400 enum {
401 kMaxNumberOfFrequencies = 4000
402 };
403 int fChip;
404 int fNumberOfFrequencies;
405 FrequencyData *fFrequency[kMaxNumberOfFrequencies];
406
407 private:
408 TimeData(const TimeData &c); // not implemented
409 TimeData &operator=(const TimeData &rhs); // not implemented
410
411 public:
412 TimeData()
413 :fChip(0)
414 ,fNumberOfFrequencies(0) {
415 }
416 ~TimeData() {
417 int i;
418 for (i = 0; i < fNumberOfFrequencies; i++) {
419 delete fFrequency[i];
420 }
421 }
422 };
423
424public:
425 // DAC channels (CMC Version 1 : DAC_COFSA,DAC_COFSB,DAC_DRA,DAC_DSA,DAC_TLEVEL,DAC_ACALIB,DAC_DSB,DAC_DRB)
426 unsigned int fDAC_COFSA;
427 unsigned int fDAC_COFSB;
428 unsigned int fDAC_DRA;
429 unsigned int fDAC_DSA;
430 unsigned int fDAC_TLEVEL;
431 unsigned int fDAC_ACALIB;
432 unsigned int fDAC_DSB;
433 unsigned int fDAC_DRB;
434 // DAC channels (CMC Version 2+3 : DAC_COFS,DAC_DSA,DAC_DSB,DAC_TLEVEL,DAC_ADCOFS,DAC_CLKOFS,DAC_ACALIB)
435 unsigned int fDAC_COFS;
436 unsigned int fDAC_ADCOFS;
437 unsigned int fDAC_CLKOFS;
438 // DAC channels (CMC Version 4 : DAC_ROFS_1,DAC_DSA,DAC_DSB,DAC_ROFS_2,DAC_ADCOFS,DAC_ACALIB,DAC_INOFS,DAC_BIAS)
439 unsigned int fDAC_ROFS_1;
440 unsigned int fDAC_ROFS_2;
441 unsigned int fDAC_INOFS;
442 unsigned int fDAC_BIAS;
443 // DAC channels (USB EVAL1 (Version 5) : DAC_ROFS_1,DAC_CMOFS,DAC_CALN,DAC_CALP,DAC_BIAS,DAC_TLEVEL,DAC_ONOFS)
444 unsigned int fDAC_CMOFS;
445 unsigned int fDAC_CALN;
446 unsigned int fDAC_CALP;
447 unsigned int fDAC_ONOFS;
448 // DAC channels (DRS4 MEZZ1 (Version 6) : DAC_ONOFS,DAC_CMOFSP,DAC_CALN,DAC_CALP,DAC_BIAS,DAC_CMOFSN,DAC_ROFS_1)
449 unsigned int fDAC_CMOFSP;
450 unsigned int fDAC_CMOFSN;
451
452protected:
453 // Fields for DRS
454 int fDRSType;
455 int fBoardType;
456 int fNumberOfChips;
457 int fNumberOfChannels;
458 int fRequiredFirmwareVersion;
459 int fFirmwareVersion;
460 int fBoardSerialNumber;
461 unsigned int fTransport;
462 unsigned int fCtrlBits;
463 int fNumberOfReadoutChannels;
464 int fReadoutChannelConfig;
465 int fADCClkPhase;
466 bool fADCClkInvert;
467 double fExternalClockFrequency;
468#ifdef HAVE_USB
469 MUSB_INTERFACE *fUsbInterface;
470#endif
471#ifdef HAVE_VME
472 MVME_INTERFACE *fVmeInterface;
473 mvme_addr_t fBaseAddress;
474#endif
475#ifdef CT_VME
476 VME_ErrorCode_t ErrorCode;
477 VME_BlockTransferList_t BLT_List;
478 char ErrorString[VME_MAXSTRING];
479 int CMEM_SegIdentifier;
480 unsigned long PCIAddress; // Physical address of contiguous buffer
481 unsigned long VirtualAddress; // Virtual address of contiguous buffer
482 unsigned int fBaseAddress;
483 unsigned int fBoardAddress;
484 int fMasterMapping;
485
486 unsigned int GetBaseAddress() const {return fBaseAddress; }
487 unsigned int GetBoardAddress() const {return fBoardAddress; }
488
489 int AllocateSegmentCMEM(unsigned int SegSize, int *CMEM_SegIdentifier);
490 int AssignPhysicalSegAddressCMEM(int CMEM_SegIdentifier, unsigned long* PCIAddress);
491 int AssignVirtualSegAddressCMEM(int CMEM_SegIdentifier, unsigned long* VirtualAddress);
492 int FreeSegmentCMEM(int CMEM_SegIdentifier);
493#endif
494
495 int fSlotNumber;
496 double fFrequency;
497 double fTCALFrequency;
498 double fRefClock;
499 int fDominoMode;
500 int fDominoActive;
501 int fChannelConfig;
502 int fWSRLoop;
503 int fReadoutMode;
504 int fTriggerEnable1;
505 int fTriggerEnable2;
506 int fTriggerSource;
507 int fTriggerDelay;
508 int fDelayedStart;
509 int fTranspMode;
510 unsigned short fStopCell[4];
511 double fROFS;
512 double fRange;
513 double fCommonMode;
514 int fAcalMode;
515 int fbkAcalMode;
516 double fAcalVolt;
517 double fbkAcalVolt;
518 int fTcalFreq;
519 int fbkTcalFreq;
520 int fTcalLevel;
521 int fbkTcalLevel;
522 int fTcalPhase;
523 int fTcalSource;
524
525 unsigned char fWaveforms[kNumberOfChipsMax * kNumberOfChannelsMax * 2 * kNumberOfBins];
526
527 // Fields for Calibration
528 int fMaxChips;
529 char fCalibDirectory[1000];
530
531 // Fields for Response Calibration old method
532 ResponseCalibration *fResponseCalibration;
533
534 // Fields for Calibration new method
535 bool fCellCalibrationValid;
536 double fCellCalibratedRange;
537 unsigned short fCellOffset[kNumberOfChipsMax * kNumberOfChannelsMax][kNumberOfBins];
538 unsigned short fCellOffset2[kNumberOfChipsMax * kNumberOfChannelsMax][kNumberOfBins];
539 double fCellGain[kNumberOfChipsMax * kNumberOfChannelsMax][kNumberOfBins];
540
541 bool fTimingCalibrationValid;
542 double fTimingCalibratedFrequency;
543 double fCellT[kNumberOfChipsMax][kNumberOfBins];
544 signed short fCellDT[kNumberOfChipsMax * kNumberOfChannelsMax][kNumberOfBins];
545
546 // Fields for Time Calibration
547 TimeData **fTimeData;
548 int fNumberOfTimeData;
549
550 // General debugging flag
551 int fDebug;
552
553 // Fields for wave transfer
554 bool fWaveTransferred[kNumberOfChipsMax * kNumberOfChannelsMax];
555
556 // Waveform Rotation
557 int fTriggerStartBin; // Start Bin of the trigger
558
559private:
560 DRSBoard(const DRSBoard &c); // not implemented
561 DRSBoard &operator=(const DRSBoard &rhs); // not implemented
562
563public:
564 // Public Methods
565#ifdef HAVE_USB
566 DRSBoard(MUSB_INTERFACE * musb_interface, int usb_slot);
567#endif
568#ifdef HAVE_VME
569 DRSBoard(MVME_INTERFACE * mvme_interface, mvme_addr_t base_address, int slot_number);
570
571 MVME_INTERFACE *GetVMEInterface() const { return fVmeInterface; };
572#endif
573#ifdef CT_VME
574 DRSBoard(int MasterMapping, unsigned int BaseAddress, unsigned int BoardAddress, int SlotNumber);
575#endif
576
577 ~DRSBoard();
578
579 int SetBoardSerialNumber(unsigned short serialNumber);
580 int GetBoardSerialNumber() const { return fBoardSerialNumber; }
581 int GetFirmwareVersion() const { return fFirmwareVersion; }
582 int GetRequiredFirmwareVersion() const { return fRequiredFirmwareVersion; }
583 int GetDRSType() const { return fDRSType; }
584 int GetBoardType() const { return fBoardType; }
585 int GetNumberOfChips() const { return fNumberOfChips; }
586 int GetNumberOfChannels() const { return fNumberOfChannels; }
587 int GetSlotNumber() const { return fSlotNumber; }
588 int InitFPGA(void);
589 int Write(int type, unsigned int addr, void *data, int size);
590 int Read(int type, void *data, unsigned int addr, int size);
591 int GetTransport() const { return fTransport; }
592 void RegisterTest(void);
593 int RAMTest(int flag);
594 int ChipTest();
595 unsigned int GetCtrlReg(void);
596 unsigned short GetConfigReg(void);
597 unsigned int GetStatusReg(void);
598 void SetLED(int state);
599 void SetChannelConfig(int firstChannel, int lastChannel, int nConfigChannels);
600 void SetADCClkPhase(int phase, bool invert);
601 void SetWarmup(unsigned int ticks);
602 void SetCooldown(unsigned int ticks);
603 int GetReadoutChannelConfig() { return fReadoutChannelConfig; }
604 void SetNumberOfChannels(int nChannels);
605 int EnableTrigger(int flag1, int flag2);
606 int GetTriggerEnable(int i) { return i?fTriggerEnable2:fTriggerEnable1; }
607 int SetDelayedTrigger(int flag);
608 int SetTriggerDelay(int delay);
609 int GetTriggerDelay() { return fTriggerDelay; }
610 int SetTriggerLevel(double value, bool negative);
611 int SetTriggerSource(int source);
612 int GetTriggerSource() { return fTriggerSource; }
613 int SetDelayedStart(int flag);
614 int SetTranspMode(int flag);
615 int SetStandbyMode(int flag);
616 int IsBusy(void);
617 int IsPLLLocked(void);
618 int IsLMKLocked(void);
619 int IsNewFreq(unsigned char chipIndex);
620 int SetDAC(unsigned char channel, double value);
621 int ReadDAC(unsigned char channel, double *value);
622 int GetRegulationDAC(double *value);
623 int StartDomino();
624 int StartClearCycle();
625 int FinishClearCycle();
626 int Reinit();
627 int Init();
628 void SetDebug(int debug) { fDebug = debug; }
629 int Debug() { return fDebug; }
630 int SetDominoMode(unsigned char mode);
631 int SetDominoActive(unsigned char mode);
632 int SetReadoutMode(unsigned char mode);
633 int SoftTrigger(void);
634 int ReadFrequency(unsigned char chipIndex, double *f);
635 int SetFrequency(double freq, bool wait);
636 double VoltToFreq(double volt);
637 double FreqToVolt(double freq);
638 double GetFrequency() const { return fFrequency; }
639 int RegulateFrequency(double freq);
640 int SetExternalClockFrequency(double frequencyMHz);
641 double GetExternalClockFrequency();
642 void SetVoltageOffset(double offset1, double offset2);
643 int SetInputRange(double center);
644 double GetInputRange(void) { return fRange; }
645 double GetCalibratedInputRange(void) { return fCellCalibratedRange; }
646 double GetCalibratedFrequency(void) { return fTimingCalibratedFrequency; }
647 int TransferWaves(int numberOfChannels = kNumberOfChipsMax * kNumberOfChannelsMax);
648 int TransferWaves(unsigned char *p, int numberOfChannels = kNumberOfChipsMax * kNumberOfChannelsMax);
649 int TransferWaves(int firstChannel, int lastChannel);
650 int TransferWaves(unsigned char *p, int firstChannel, int lastChannel);
651 int DecodeWave(unsigned char *waveforms, unsigned int chipIndex, unsigned char channel,
652 unsigned short *waveform);
653 int DecodeWave(unsigned int chipIndex, unsigned char channel, unsigned short *waveform);
654 int GetWave(unsigned char *waveforms, unsigned int chipIndex, unsigned char channel, short *waveform,
655 bool responseCalib = false, int triggerCell = -1, bool adjustToClock = false,
656 float threshold = 0, bool offsetCalib = true);
657 int GetWave(unsigned char *waveforms, unsigned int chipIndex, unsigned char channel, float *waveform,
658 bool responseCalib = false, int triggerCell = -1, bool adjustToClock = false,
659 float threshold = 0, bool offsetCalib = true);
660 int GetWave(unsigned int chipIndex, unsigned char channel, short *waveform, bool responseCalib = false,
661 int triggerCell = -1, bool adjustToClock = false, float threshold = 0, bool offsetCalib = true);
662 int GetWave(unsigned int chipIndex, unsigned char channel, float *waveform, bool responseCalib,
663 int triggerCell = -1, bool adjustToClock = false, float threshold = 0, bool offsetCalib = true);
664 int GetWave(unsigned int chipIndex, unsigned char channel, float *waveform);
665 int GetRawWave(unsigned int chipIndex, unsigned char channel, unsigned short *waveform, bool adjustToClock = false);
666 int GetRawWave(unsigned char *waveforms,unsigned int chipIndex, unsigned char channel,
667 unsigned short *waveform, bool adjustToClock = false);
668 int GetTime(unsigned int chipIndex, double freq, float *time, bool tcalibrated=true, bool rotated=true);
669 int GetTime(unsigned int chipIndex, float *time, bool tcalibrated=true, bool rotated=true);
670 int GetTriggerCell(unsigned int chipIndex);
671 int GetStopCell(unsigned int chipIndex);
672 int GetTriggerCell(unsigned char *waveforms,unsigned int chipIndex);
673 void TestDAC(int channel);
674 void MeasureSpeed();
675 void InteractSpeed();
676 void MonitorFrequency();
677 int TestShift(int n);
678 int EnableAcal(int mode, double voltage);
679 int GetAcalMode() { return fAcalMode; }
680 double GetAcalVolt() { return fAcalVolt; }
681 int EnableTcal(int freq, int level=0, int phase=0);
682 int SelectClockSource(int source);
683 int SetRefclk(int source);
684 int GetTcalFreq() { return fTcalFreq; }
685 int GetTcalLevel() { return fTcalLevel; }
686 int GetTcalPhase() { return fTcalPhase; }
687 int GetTcalSource() { return fTcalSource; }
688 int SetCalibVoltage(double value);
689 int SetCalibTiming(int t1, int t2);
690 double GetTemperature();
691 int GetTriggerBus();
692 int ReadEEPROM(unsigned short page, void *buffer, int size);
693 int WriteEEPROM(unsigned short page, void *buffer, int size);
694 bool HasCorrectFirmware();
695 int ConfigureLMK(double sampFreq, bool freqChange, int calFreq, int calPhase);
696
697 bool InitTimeCalibration(unsigned int chipIndex);
698 void SetCalibrationDirectory(const char *calibrationDirectoryPath);
699 void GetCalibrationDirectory(char *calibrationDirectoryPath);
700
701 ResponseCalibration *GetResponseCalibration() const { return fResponseCalibration; }
702
703 double GetPrecision() const { return fResponseCalibration ? fResponseCalibration->GetPrecision() : 0.1; }
704 int CalibrateWaveform(unsigned int chipIndex, unsigned char channel, unsigned short *adcWaveform,
705 short *waveform, bool responseCalib, int triggerCell, bool adjustToClock,
706 float threshold, bool offsetCalib);
707
708 static void LinearRegression(double *x, double *y, int n, double *a, double *b);
709
710 void ReadSingleWaveform(int nChips, int nChan,
711 unsigned short wfu[kNumberOfChipsMax][kNumberOfChannelsMax][kNumberOfBins], bool rotated);
712 int AverageWaveforms(DRSCallback *pcb, int chipIndex, int nChan, int prog1, int prog2, unsigned short *awf, int n, bool rotated);
713 int RobustAverageWaveforms(DRSCallback *pcb, int chipIndex, int nChan, int prog1, int prog2, unsigned short *awf, int n, bool rotated);
714 int CalibrateVolt(DRSCallback *pcb);
715 int AnalyzeWF(int nIter, float wf[kNumberOfBins], int tCell, double cellT[kNumberOfBins]);
716 int CalibrateTiming(DRSCallback *pcb);
717 bool IsCalibrationValid() { return fCellCalibrationValid; }
718 bool IsTimingCalibrationValid() { return fTimingCalibrationValid; }
719 static void RemoveSymmetricSpikes(short **wf, int nwf,
720 short diffThreshold, int spikeWidth,
721 short maxPeakToPeak, short spikeVoltage,
722 int nTimeRegionThreshold);
723protected:
724 // Protected Methods
725 void ConstructBoard();
726 void ReadSerialNumber();
727 void ReadCalibration(void);
728
729 TimeData *GetTimeCalibration(unsigned int chipIndex, bool reinit = false);
730
731 int GetStretchedTime(float *time, float *measurement, int numberOfMeasurements, float period);
732};
733
734class DRS {
735protected:
736 // constants
737 enum {
738 kMaxNumberOfBoards = 40
739 };
740
741protected:
742 DRSBoard *fBoard[kMaxNumberOfBoards];
743 int fNumberOfBoards;
744 char fError[256];
745#ifdef HAVE_VME
746 MVME_INTERFACE *fVmeInterface;
747#endif
748
749private:
750 DRS(const DRS &c); // not implemented
751 DRS &operator=(const DRS &rhs); // not implemented
752
753#ifdef CT_VME
754 VME_MasterMap_t MasterMap;
755 VME_ErrorCode_t ErrorCode;
756 char ErrorString[VME_MAXSTRING];
757 int MasterMapping[kMaxNumberOfBoards];
758
759 int OpenVME();
760 int MasterMapVME(int* MMap);
761 int MasterUnMapVME(int MMap);
762 int CloseVME();
763 int OpenCMEM();
764 int CloseCMEM();
765#endif
766
767public:
768 // Public Methods
769 DRS();
770 ~DRS();
771
772 DRSBoard *GetBoard(int i) { return fBoard[i]; }
773 DRSBoard **GetBoards() { return fBoard; }
774 int GetNumberOfBoards() const { return fNumberOfBoards; }
775 bool GetError(char *str, int size);
776#ifdef HAVE_VME
777 MVME_INTERFACE *GetVMEInterface() const { return fVmeInterface; };
778#endif
779};
780
781#endif // DRS_H
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