1 | [DesignChecker]
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2 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/designcheck
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3 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck
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4 | [ModelSim]
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5 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
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6 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
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7 | hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/work
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8 | secureip = D:\unisim/secureip
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9 | simprim = D:\unisim/simprim
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10 | unimacro = D:\unisim/unimacro
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11 | unisim = D:\unisim/unisim
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12 | XilinxCoreLib = D:\unisim/xilinxcorelib
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13 | [QuestaSim]
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14 | secureip = D:\unisim/secureip
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15 | simprim = D:\unisim/simprim
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16 | unimacro = D:\unisim/unimacro
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17 | unisim = D:\unisim/unisim
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18 | XilinxCoreLib = D:\unisim/xilinxcorelib
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19 | [XilinxISE]
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20 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
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21 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise
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22 | [hdl]
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23 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
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24 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl
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25 | unisim = $HDS_PROJECT_DIR/unisim/hdl
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26 | [hdl_vm]
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27 | FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm
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28 | [hds]
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29 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
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30 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds
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31 | unisim = $HDS_PROJECT_DIR/unisim/hds
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32 | [hds_settings]
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33 | default_library = FACT_FAD_lib
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34 | design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
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35 | project_description = FPGA design for data acquisition from FACT
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36 | version = 1
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37 | [hds_vm]
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38 | FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm
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39 | [library_files_inclusion]
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40 | FACT_FAD_lib = specify
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41 | FACT_FAD_TB_lib = all
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42 | [library_type]
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43 | FACT_FAD_lib = regular
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44 | FACT_FAD_TB_lib = regular
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45 | secureip = downstream_only
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46 | simprim = downstream_only
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47 | unimacro = downstream_only
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48 | unisim = standard
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49 | XilinxCoreLib = downstream_only
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50 | [protected_library_traversal]
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51 | unisim = no
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52 | [shared]
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53 | others = $HDS_TEAM_HOME/shared.hdp
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