| 1 | [DesignChecker]
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| 2 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/designcheck
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| 3 | [ModelSim]
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| 4 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
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| 5 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
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| 6 | secureip = D:/unisim/secureip
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| 7 | simprim = D:/unisim/simprim
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| 8 | unimacro = D:/unisim/unimacro
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| 9 | unisim = D:/unisim/unisim
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| 10 | XilinxCoreLib = D:/unisim/xilinxcorelib
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| 11 | [QuestaSim]
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| 12 | secureip = D:/unisim/secureip
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| 13 | simprim = D:/unisim/simprim
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| 14 | unimacro = D:/unisim/unimacro
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| 15 | unisim = D:/unisim/unisim
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| 16 | XilinxCoreLib = D:/unisim/xilinxcorelib
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| 17 | [XilinxISE]
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| 18 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
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| 19 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\ise
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| 20 | [hdl]
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| 21 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
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| 22 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl
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| 23 | unisim = $HDS_PROJECT_DIR/unisim/hdl
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| 24 | [hdl_vm]
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| 25 | FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm
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| 26 | [hds]
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| 27 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
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| 28 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds
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| 29 | unisim = $HDS_PROJECT_DIR/unisim/hds
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| 30 | [hds_settings]
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| 31 | default_library = FACT_FAD_lib
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| 32 | design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
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| 33 | project_description = FPGA design for data acquisition from FACT
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| 34 | version = 1
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| 35 | [hds_vm]
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| 36 | FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm
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| 37 | [library_files_inclusion]
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| 38 | FACT_FAD_lib = specify
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| 39 | FACT_FAD_TB_lib = all
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| 40 | [library_type]
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| 41 | FACT_FAD_lib = regular
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| 42 | FACT_FAD_TB_lib = regular
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| 43 | secureip = downstream_only
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| 44 | simprim = downstream_only
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| 45 | unimacro = downstream_only
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| 46 | unisim = standard
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| 47 | XilinxCoreLib = downstream_only
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| 48 | [protected_library_traversal]
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| 49 | unisim = no
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| 50 | [shared]
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| 51 | others = $HDS_TEAM_HOME/shared.hdp
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