[DesignChecker]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/designcheck
FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck
[ModelSim]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
hds_package_library = $HDS_HOME\hdl_libs\hds_package_library\work
secureip = D:\unisim/secureip
simprim = D:\unisim/simprim
unimacro = D:\unisim/unimacro
unisim = D:\unisim/unisim
XilinxCoreLib = D:\unisim/xilinxcorelib
[QuestaSim]
secureip = D:\unisim/secureip
simprim = D:\unisim/simprim
unimacro = D:\unisim/unimacro
unisim = D:\unisim/unisim
XilinxCoreLib = D:\unisim/xilinxcorelib
[XilinxISE]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise
[hdl]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl
unisim = $HDS_PROJECT_DIR/unisim/hdl
[hdl_vm]
FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm
[hds]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds
unisim = $HDS_PROJECT_DIR/unisim/hds
[hds_settings]
default_library = FACT_FAD_lib
design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
project_description = FPGA design for data acquisition from FACT
version = 1
[hds_vm]
FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm
[library_files_inclusion]
FACT_FAD_lib = specify
FACT_FAD_TB_lib = all
[library_type]
FACT_FAD_lib = regular
FACT_FAD_TB_lib = regular
secureip = downstream_only
simprim = downstream_only
unimacro = downstream_only
unisim = standard
XilinxCoreLib = downstream_only
[protected_library_traversal]
unisim = no
[shared]
others = $HDS_TEAM_HOME/shared.hdp