source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/dna_gen_tb_struct.vhd@ 10240

Last change on this file since 10240 was 10240, checked in by neise, 10 years ago
File size: 2.3 KB
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1-- VHDL Entity FACT_FAD_TB_lib.dna_gen_tb.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 09:58:10 03.03.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9
10
11ENTITY dna_gen_tb IS
12-- Declarations
13
14END dna_gen_tb ;
15
16--
17-- VHDL Architecture FACT_FAD_TB_lib.dna_gen_tb.struct
18--
19-- Created:
20-- by - daqct3.UNKNOWN (IHP110)
21-- at - 09:58:10 03.03.2011
22--
23-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
24--
25LIBRARY IEEE;
26USE IEEE.STD_LOGIC_1164.ALL;
27USE IEEE.STD_LOGIC_ARITH.ALL;
28USE IEEE.STD_LOGIC_UNSIGNED.ALL;
29LIBRARY UNISIM;
30USE UNISIM.VComponents.ALL;
31
32LIBRARY FACT_FAD_lib;
33LIBRARY FACT_FAD_TB_lib;
34
35ARCHITECTURE struct OF dna_gen_tb IS
36
37 -- Architecture declarations
38
39 -- Internal signal declarations
40 SIGNAL clk : STD_LOGIC;
41 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0);
42 SIGNAL ready : STD_LOGIC;
43
44
45 -- Component Declarations
46 COMPONENT dna_gen
47 PORT (
48 clk : IN STD_LOGIC;
49 dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0');
50 ready : OUT STD_LOGIC := '0'
51 );
52 END COMPONENT;
53 COMPONENT clock_generator
54 GENERIC (
55 clock_period : time := 20 ns;
56 reset_time : time := 50 ns
57 );
58 PORT (
59 clk : OUT std_logic := '0';
60 rst : OUT std_logic := '0'
61 );
62 END COMPONENT;
63 COMPONENT dna_gen_tester
64 PORT (
65 dna : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
66 ready : IN STD_LOGIC
67 );
68 END COMPONENT;
69
70 -- Optional embedded configurations
71 -- pragma synthesis_off
72 FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
73 FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen;
74 FOR ALL : dna_gen_tester USE ENTITY FACT_FAD_TB_lib.dna_gen_tester;
75 -- pragma synthesis_on
76
77
78BEGIN
79
80 -- Instance port mappings.
81 U_0 : dna_gen
82 PORT MAP (
83 clk => clk,
84 dna => dna,
85 ready => ready
86 );
87 U_2 : clock_generator
88 GENERIC MAP (
89 clock_period => 20 ns,
90 reset_time => 50 ns
91 )
92 PORT MAP (
93 clk => clk,
94 rst => OPEN
95 );
96 U_1 : dna_gen_tester
97 PORT MAP (
98 dna => dna,
99 ready => ready
100 );
101
102END struct;
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