source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/dna_gen_tester_beha.vhd@ 10240

Last change on this file since 10240 was 10240, checked in by neise, 10 years ago
File size: 607 bytes
Line 
1--
2-- VHDL Architecture FACT_FAD_TB_lib.dna_gen_tester.beha
3--
4-- Created:
5-- by - daqct3.UNKNOWN (IHP110)
6-- at - 09:57:18 03.03.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10LIBRARY IEEE;
11USE IEEE.STD_LOGIC_1164.ALL;
12USE IEEE.STD_LOGIC_ARITH.ALL;
13USE IEEE.STD_LOGIC_UNSIGNED.ALL;
14LIBRARY UNISIM;
15USE UNISIM.VComponents.ALL;
16
17ENTITY dna_gen_tester IS
18 PORT(
19 dna : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
20 ready : IN STD_LOGIC
21 );
22
23-- Declarations
24
25END dna_gen_tester ;
26
27--
28ARCHITECTURE beha OF dna_gen_tester IS
29BEGIN
30END ARCHITECTURE beha;
31
Note: See TracBrowser for help on using the repository browser.