source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/led_controller_tb_struct.vhd@ 10240

Last change on this file since 10240 was 10240, checked in by neise, 10 years ago
File size: 4.6 KB
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1-- VHDL Entity FACT_FAD_TB_lib.led_controller_tb.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 10:21:57 02.03.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9
10
11ENTITY led_controller_tb IS
12 GENERIC(
13 HEARTBEAT_PWM_DIVIDER : integer := 500;
14 WAITING_DIVIDER : integer := 500000000
15 );
16-- Declarations
17
18END led_controller_tb ;
19
20--
21-- VHDL Architecture FACT_FAD_TB_lib.led_controller_tb.struct
22--
23-- Created:
24-- by - daqct3.UNKNOWN (IHP110)
25-- at - 10:21:58 02.03.2011
26--
27-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
28--
29LIBRARY ieee;
30USE ieee.std_logic_1164.ALL;
31USE ieee.std_logic_arith.ALL;
32USE ieee.STD_LOGIC_UNSIGNED.ALL;
33LIBRARY FACT_FAD_lib;
34USE FACT_FAD_lib.fad_definitions.ALL;
35
36LIBRARY FACT_FAD_lib;
37LIBRARY FACT_FAD_TB_lib;
38
39ARCHITECTURE struct OF led_controller_tb IS
40
41 -- Architecture declarations
42
43 -- Internal signal declarations
44 SIGNAL CLK : std_logic;
45 SIGNAL additional_flasher_out : std_logic;
46 SIGNAL amber : std_logic;
47 SIGNAL green : std_logic;
48 SIGNAL red : std_logic;
49 SIGNAL refclk_too_high : std_logic;
50 SIGNAL refclk_too_low : std_logic;
51 SIGNAL socks_connected : std_logic;
52 SIGNAL socks_waiting : std_logic;
53 SIGNAL trigger : std_logic;
54
55
56 -- Component Declarations
57 COMPONENT led_controller
58 GENERIC (
59 HEARTBEAT_PWM_DIVIDER : integer := 500;
60 WAITING_DIVIDER : integer := 500000000
61 );
62 PORT (
63 CLK : IN std_logic;
64 refclk_too_high : IN std_logic;
65 refclk_too_low : IN std_logic;
66 socks_connected : IN std_logic;
67 socks_waiting : IN std_logic;
68 trigger : IN std_logic;
69 additional_flasher_out : OUT std_logic;
70 amber : OUT std_logic;
71 green : OUT std_logic;
72 red : OUT std_logic
73 );
74 END COMPONENT;
75 COMPONENT clock_generator
76 GENERIC (
77 clock_period : time := 20 ns;
78 reset_time : time := 50 ns
79 );
80 PORT (
81 clk : OUT std_logic := '0';
82 rst : OUT std_logic := '0'
83 );
84 END COMPONENT;
85 COMPONENT led_controller_tester
86 PORT (
87 additional_flasher_out : IN std_logic ;
88 amber : IN std_logic ;
89 green : IN std_logic ;
90 red : IN std_logic ;
91 refclk_too_high : OUT std_logic ;
92 refclk_too_low : OUT std_logic ;
93 socks_connected : OUT std_logic ;
94 socks_waiting : OUT std_logic ;
95 trigger : OUT std_logic
96 );
97 END COMPONENT;
98
99 -- Optional embedded configurations
100 -- pragma synthesis_off
101 FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
102 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
103 FOR ALL : led_controller_tester USE ENTITY FACT_FAD_TB_lib.led_controller_tester;
104 -- pragma synthesis_on
105
106
107BEGIN
108
109 -- Instance port mappings.
110 led_controller_instance : led_controller
111 GENERIC MAP (
112 HEARTBEAT_PWM_DIVIDER => 500,
113 WAITING_DIVIDER => 500000000
114 )
115 PORT MAP (
116 CLK => CLK,
117 green => green,
118 amber => amber,
119 red => red,
120 additional_flasher_out => additional_flasher_out,
121 trigger => trigger,
122 refclk_too_high => refclk_too_high,
123 refclk_too_low => refclk_too_low,
124 socks_waiting => socks_waiting,
125 socks_connected => socks_connected
126 );
127 U_2 : clock_generator
128 GENERIC MAP (
129 clock_period => 20 ns,
130 reset_time => 50 ns
131 )
132 PORT MAP (
133 clk => CLK,
134 rst => OPEN
135 );
136 U_1 : led_controller_tester
137 PORT MAP (
138 additional_flasher_out => additional_flasher_out,
139 amber => amber,
140 green => green,
141 red => red,
142 refclk_too_high => refclk_too_high,
143 refclk_too_low => refclk_too_low,
144 socks_connected => socks_connected,
145 socks_waiting => socks_waiting,
146 trigger => trigger
147 );
148
149END struct;
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