source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/trigger_manager_tb_struct.vhd@ 10240

Last change on this file since 10240 was 10240, checked in by neise, 10 years ago
File size: 3.1 KB
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1-- VHDL Entity FACT_FAD_TB_lib.trigger_manager_tb.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 14:19:05 14.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9
10
11ENTITY trigger_manager_tb IS
12-- Declarations
13
14END trigger_manager_tb ;
15
16--
17-- VHDL Architecture FACT_FAD_TB_lib.trigger_manager_tb.struct
18--
19-- Created:
20-- by - daqct3.UNKNOWN (IHP110)
21-- at - 14:19:06 14.01.2011
22--
23-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
24--
25LIBRARY ieee;
26USE ieee.std_logic_1164.ALL;
27USE ieee.std_logic_arith.ALL;
28USE ieee.std_logic_unsigned.all;
29
30LIBRARY FACT_FAD_lib;
31LIBRARY FACT_FAD_TB_lib;
32
33ARCHITECTURE struct OF trigger_manager_tb IS
34
35 -- Architecture declarations
36
37 -- Internal signal declarations
38 SIGNAL clk : std_logic;
39 SIGNAL drs_readout_ready : std_logic := '0';
40 SIGNAL drs_readout_ready_ack : std_logic;
41 SIGNAL drs_write : std_logic := '1';
42 SIGNAL trigger_in : std_logic := '0';
43 SIGNAL trigger_out : std_logic := '0';
44
45
46 -- Component Declarations
47 COMPONENT trigger_manager
48 PORT (
49 clk : IN std_logic;
50 drs_readout_ready : IN std_logic;
51 trigger_in : IN std_logic;
52 drs_readout_ready_ack : OUT std_logic := '0';
53 drs_write : OUT std_logic := '1';
54 trigger_out : OUT std_logic := '0'
55 );
56 END COMPONENT;
57 COMPONENT clock_generator
58 GENERIC (
59 clock_period : time := 20 ns;
60 reset_time : time := 50 ns
61 );
62 PORT (
63 clk : OUT std_logic := '0';
64 rst : OUT std_logic := '0'
65 );
66 END COMPONENT;
67 COMPONENT trigger_manager_tester
68 PORT (
69 drs_readout_ready_ack : IN std_logic ;
70 drs_readout_ready : OUT std_logic ;
71 trigger_in : OUT std_logic
72 );
73 END COMPONENT;
74
75 -- Optional embedded configurations
76 -- pragma synthesis_off
77 FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
78 FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager;
79 FOR ALL : trigger_manager_tester USE ENTITY FACT_FAD_TB_lib.trigger_manager_tester;
80 -- pragma synthesis_on
81
82
83BEGIN
84
85 -- Instance port mappings.
86 U_0 : trigger_manager
87 PORT MAP (
88 clk => clk,
89 trigger_in => trigger_in,
90 trigger_out => trigger_out,
91 drs_write => drs_write,
92 drs_readout_ready => drs_readout_ready,
93 drs_readout_ready_ack => drs_readout_ready_ack
94 );
95 -- synthesis translate_off
96 U_2 : clock_generator
97 GENERIC MAP (
98 clock_period => 20 ns,
99 reset_time => 50 ns
100 )
101 PORT MAP (
102 clk => clk,
103 rst => OPEN
104 );
105 U_1 : trigger_manager_tester
106 PORT MAP (
107 drs_readout_ready_ack => drs_readout_ready_ack,
108 drs_readout_ready => drs_readout_ready,
109 trigger_in => trigger_in
110 );
111
112END struct;
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