source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/trigger_manager_tester_beha.vhd@ 10240

Last change on this file since 10240 was 10240, checked in by neise, 10 years ago
File size: 1.1 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_TB_lib.trigger_manager_tester.beha
3--
4-- Created:
5-- by - daqct3.UNKNOWN (IHP110)
6-- at - 13:39:39 14.01.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.ALL;
12USE ieee.std_logic_arith.ALL;
13USE ieee.std_logic_unsigned.all;
14
15ENTITY trigger_manager_tester IS
16 PORT(
17 drs_readout_ready_ack : IN std_logic;
18-- drs_write : IN std_logic;
19-- trigger_out : IN std_logic;
20-- clk : OUT std_logic;
21 drs_readout_ready : OUT std_logic := '0';
22 trigger_in : OUT std_logic := '0'
23 );
24
25-- Declarations
26
27END trigger_manager_tester ;
28
29--
30ARCHITECTURE beha OF trigger_manager_tester IS
31BEGIN
32
33 main_proc : process
34 begin
35 wait for 500 ns;
36 wait for 5 ns;
37 trigger_in <= '1';
38 wait for 15 ns;
39 wait for 100 ns;
40 trigger_in <= '0';
41 wait for 110 ns;
42 drs_readout_ready <= '1';
43 wait until (drs_readout_ready_ack = '1');
44 wait for 20 ns;
45 drs_readout_ready <= '0';
46 wait for 100 ns;
47 end process main_proc;
48
49
50END ARCHITECTURE beha;
51
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