source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd@ 10225

Last change on this file since 10225 was 10225, checked in by neise, 10 years ago
new data format implemented. setting of DAC during run is possible.
File size: 2.7 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha
3--
4-- Created:
5-- by - FPGA_Developer.UNKNOWN (EEPC8)
6-- at - 07:51:36 04.02.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12USE ieee.std_logic_arith.all;
13USE ieee.std_logic_unsigned.all;
14LIBRARY FACT_FAD_lib;
15USE FACT_FAD_lib.fad_definitions.all;
16
17ENTITY w5300_emulator IS
18 PORT(
19 int : out std_logic := '1';
20 addr : in std_logic_vector (9 DOWNTO 0);
21 data : inout std_logic_vector (15 DOWNTO 0);
22 rd : in std_logic;
23 wr : in std_logic
24 );
25
26-- Declarations
27
28END w5300_emulator ;
29
30architecture beha of w5300_emulator is
31
32 signal open_done : std_logic_vector(7 downto 0) := (others => '0');
33 signal data_temp : std_logic_vector(15 downto 0);
34
35 signal RSR_0, RSR_1 : std_logic_vector (15 downto 0);
36 signal FIFOR_CNT : integer := 0;
37
38begin
39
40 data <= data_temp when (rd = '0') else (others => 'Z');
41 data_temp <= data when (wr = '0') else (others => 'Z');
42
43 set_proc : process
44 begin
45 FIFOR_CNT <= 0;
46 RSR_0 <= X"0000";
47 RSR_1 <= X"0000";
48 wait for 150 us;
49 RSR_1 <= X"0001";
50 wait for 100 us;
51 RSR_1 <= X"0002";
52 wait for 500 us;
53 FIFOR_CNT <= 1;
54 wait for 100 us;
55 FIFOR_CNT <= 2;
56 wait for 200 us;
57 FIFOR_CNT <= 3;
58 wait for 200 ns;
59 RSR_1 <= X"0000";
60 wait for 2 ms;
61 RSR_1 <= X"0002";
62 FIFOR_CNT <= 2;
63
64 wait for 6 ms;
65 int <= '0';
66
67-- wait for 1 ms;
68-- RSR_1 <= X"0000";
69-- FIFOR_CNT <= 3;
70 wait;
71 end process set_proc;
72
73 w5300_proc : process (addr)
74 begin
75 for i in 0 to 7 loop
76 if (addr = conv_integer(W5300_S0_SSR) + i * 64) then
77 if (open_done(i) = '0') then
78 data_temp <= X"0013";
79 open_done(i) <= '1';
80 else
81 data_temp <= X"0017";
82 end if;
83 elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then
84 data_temp <= X"0000";
85 elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then
86 data_temp <= X"3C00";
87 elsif (addr = conv_integer(W5300_S0_RX_RSR)) then
88 data_temp <= RSR_0;
89 elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then
90 data_temp <= RSR_1;
91 elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then
92 if (FIFOR_CNT = 0) then
93 data_temp <= X"1800";
94
95 elsif (FIFOR_CNT = 1) then
96 data_temp <= X"2200";
97
98 elsif (FIFOR_CNT = 2) then
99 data_temp <= X"A000";
100
101
102 elsif (FIFOR_CNT = 3) then
103 data_temp <= X"A000";
104 end if;
105 else
106 null;
107 end if;
108 end loop;
109 end process w5300_proc;
110
111
112end architecture beha;
113
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