source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak@ 10225

Last change on this file since 10225 was 10225, checked in by neise, 10 years ago
new data format implemented. setting of DAC during run is possible.
File size: 110.3 KB
Line 
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990)
991xt "101700,21500,108000,22500"
992st "wiz_data : (15:0)"
993ju 2
994blo "108000,22300"
995)
996)
997thePort (LogicalPort
998m 2
999decl (Decl
1000n "wiz_data"
1001t "std_logic_vector"
1002b "(15 DOWNTO 0)"
1003o 42
1004suid 27,0
1005)
1006)
1007)
1008*21 (CptPort
1009uid 141,0
1010ps "OnEdgeStrategy"
1011shape (Triangle
1012uid 142,0
1013ro 90
1014va (VaSet
1015vasetType 1
1016fg "0,65535,0"
1017)
1018xt "109000,27625,109750,28375"
1019)
1020tg (CPTG
1021uid 143,0
1022ps "CptPortTextPlaceStrategy"
1023stg "RightVerticalLayoutStrategy"
1024f (Text
1025uid 144,0
1026va (VaSet
1027)
1028xt "105300,27500,108000,28500"
1029st "wiz_cs"
1030ju 2
1031blo "108000,28300"
1032)
1033)
1034thePort (LogicalPort
1035m 1
1036decl (Decl
1037n "wiz_cs"
1038t "std_logic"
1039o 37
1040suid 28,0
1041i "'1'"
1042)
1043)
1044)
1045*22 (CptPort
1046uid 145,0
1047ps "OnEdgeStrategy"
1048shape (Triangle
1049uid 146,0
1050ro 90
1051va (VaSet
1052vasetType 1
1053fg "0,65535,0"
1054)
1055xt "109000,25625,109750,26375"
1056)
1057tg (CPTG
1058uid 147,0
1059ps "CptPortTextPlaceStrategy"
1060stg "RightVerticalLayoutStrategy"
1061f (Text
1062uid 148,0
1063va (VaSet
1064)
1065xt "105300,25500,108000,26500"
1066st "wiz_wr"
1067ju 2
1068blo "108000,26300"
1069)
1070)
1071thePort (LogicalPort
1072m 1
1073decl (Decl
1074n "wiz_wr"
1075t "std_logic"
1076o 40
1077suid 29,0
1078i "'1'"
1079)
1080)
1081)
1082*23 (CptPort
1083uid 149,0
1084ps "OnEdgeStrategy"
1085shape (Triangle
1086uid 150,0
1087ro 90
1088va (VaSet
1089vasetType 1
1090fg "0,65535,0"
1091)
1092xt "109000,24625,109750,25375"
1093)
1094tg (CPTG
1095uid 151,0
1096ps "CptPortTextPlaceStrategy"
1097stg "RightVerticalLayoutStrategy"
1098f (Text
1099uid 152,0
1100va (VaSet
1101)
1102xt "105400,24500,108000,25500"
1103st "wiz_rd"
1104ju 2
1105blo "108000,25300"
1106)
1107)
1108thePort (LogicalPort
1109m 1
1110decl (Decl
1111n "wiz_rd"
1112t "std_logic"
1113o 38
1114suid 30,0
1115i "'1'"
1116)
1117)
1118)
1119*24 (CptPort
1120uid 153,0
1121ps "OnEdgeStrategy"
1122shape (Triangle
1123uid 154,0
1124ro 270
1125va (VaSet
1126vasetType 1
1127fg "0,65535,0"
1128)
1129xt "109000,26625,109750,27375"
1130)
1131tg (CPTG
1132uid 155,0
1133ps "CptPortTextPlaceStrategy"
1134stg "RightVerticalLayoutStrategy"
1135f (Text
1136uid 156,0
1137va (VaSet
1138)
1139xt "105300,26500,108000,27500"
1140st "wiz_int"
1141ju 2
1142blo "108000,27300"
1143)
1144)
1145thePort (LogicalPort
1146decl (Decl
1147n "wiz_int"
1148t "std_logic"
1149o 14
1150suid 31,0
1151)
1152)
1153)
1154*25 (CptPort
1155uid 157,0
1156ps "OnEdgeStrategy"
1157shape (Triangle
1158uid 158,0
1159ro 270
1160va (VaSet
1161vasetType 1
1162fg "0,65535,0"
1163)
1164xt "80250,22625,81000,23375"
1165)
1166tg (CPTG
1167uid 159,0
1168ps "CptPortTextPlaceStrategy"
1169stg "VerticalLayoutStrategy"
1170f (Text
1171uid 160,0
1172va (VaSet
1173)
1174xt "82000,22500,86500,23500"
1175st "CLK_25_PS"
1176blo "82000,23300"
1177)
1178)
1179thePort (LogicalPort
1180m 1
1181decl (Decl
1182n "CLK_25_PS"
1183t "std_logic"
1184o 16
1185suid 35,0
1186)
1187)
1188)
1189*26 (CptPort
1190uid 161,0
1191ps "OnEdgeStrategy"
1192shape (Triangle
1193uid 162,0
1194ro 270
1195va (VaSet
1196vasetType 1
1197fg "0,65535,0"
1198)
1199xt "80250,21625,81000,22375"
1200)
1201tg (CPTG
1202uid 163,0
1203ps "CptPortTextPlaceStrategy"
1204stg "VerticalLayoutStrategy"
1205f (Text
1206uid 164,0
1207va (VaSet
1208)
1209xt "82000,21500,85100,22500"
1210st "CLK_50"
1211blo "82000,22300"
1212)
1213)
1214thePort (LogicalPort
1215m 1
1216decl (Decl
1217n "CLK_50"
1218t "std_logic"
1219preAdd 0
1220posAdd 0
1221o 17
1222suid 37,0
1223)
1224)
1225)
1226*27 (CptPort
1227uid 165,0
1228ps "OnEdgeStrategy"
1229shape (Triangle
1230uid 166,0
1231ro 90
1232va (VaSet
1233vasetType 1
1234fg "0,65535,0"
1235)
1236xt "80250,20625,81000,21375"
1237)
1238tg (CPTG
1239uid 167,0
1240ps "CptPortTextPlaceStrategy"
1241stg "VerticalLayoutStrategy"
1242f (Text
1243uid 168,0
1244va (VaSet
1245)
1246xt "82000,20500,83900,21500"
1247st "CLK"
1248blo "82000,21300"
1249)
1250)
1251thePort (LogicalPort
1252decl (Decl
1253n "CLK"
1254t "std_logic"
1255o 1
1256suid 38,0
1257)
1258)
1259)
1260*28 (CptPort
1261uid 169,0
1262ps "OnEdgeStrategy"
1263shape (Triangle
1264uid 170,0
1265ro 90
1266va (VaSet
1267vasetType 1
1268fg "0,65535,0"
1269)
1270xt "80250,41625,81000,42375"
1271)
1272tg (CPTG
1273uid 171,0
1274ps "CptPortTextPlaceStrategy"
1275stg "VerticalLayoutStrategy"
1276f (Text
1277uid 172,0
1278va (VaSet
1279)
1280xt "82000,41500,90000,42500"
1281st "adc_otr_array : (3:0)"
1282blo "82000,42300"
1283)
1284)
1285thePort (LogicalPort
1286decl (Decl
1287n "adc_otr_array"
1288t "std_logic_vector"
1289b "(3 DOWNTO 0)"
1290o 8
1291suid 40,0
1292)
1293)
1294)
1295*29 (CptPort
1296uid 173,0
1297ps "OnEdgeStrategy"
1298shape (Triangle
1299uid 174,0
1300ro 90
1301va (VaSet
1302vasetType 1
1303fg "0,65535,0"
1304)
1305xt "80250,47625,81000,48375"
1306)
1307tg (CPTG
1308uid 175,0
1309ps "CptPortTextPlaceStrategy"
1310stg "VerticalLayoutStrategy"
1311f (Text
1312uid 176,0
1313va (VaSet
1314)
1315xt "82000,47500,87900,48500"
1316st "adc_data_array"
1317blo "82000,48300"
1318)
1319)
1320thePort (LogicalPort
1321decl (Decl
1322n "adc_data_array"
1323t "adc_data_array_type"
1324o 7
1325suid 41,0
1326)
1327)
1328)
1329*30 (CptPort
1330uid 177,0
1331ps "OnEdgeStrategy"
1332shape (Triangle
1333uid 178,0
1334ro 270
1335va (VaSet
1336vasetType 1
1337fg "0,65535,0"
1338)
1339xt "80250,61625,81000,62375"
1340)
1341tg (CPTG
1342uid 179,0
1343ps "CptPortTextPlaceStrategy"
1344stg "VerticalLayoutStrategy"
1345f (Text
1346uid 180,0
1347va (VaSet
1348)
1349xt "82000,61500,90500,62500"
1350st "drs_channel_id : (3:0)"
1351blo "82000,62300"
1352)
1353)
1354thePort (LogicalPort
1355m 1
1356decl (Decl
1357n "drs_channel_id"
1358t "std_logic_vector"
1359b "(3 downto 0)"
1360o 28
1361suid 48,0
1362i "(others => '0')"
1363)
1364)
1365)
1366*31 (CptPort
1367uid 181,0
1368ps "OnEdgeStrategy"
1369shape (Triangle
1370uid 182,0
1371ro 270
1372va (VaSet
1373vasetType 1
1374fg "0,65535,0"
1375)
1376xt "80250,66625,81000,67375"
1377)
1378tg (CPTG
1379uid 183,0
1380ps "CptPortTextPlaceStrategy"
1381stg "VerticalLayoutStrategy"
1382f (Text
1383uid 184,0
1384va (VaSet
1385)
1386xt "82000,66500,86300,67500"
1387st "drs_dwrite"
1388blo "82000,67300"
1389)
1390)
1391thePort (LogicalPort
1392m 1
1393decl (Decl
1394n "drs_dwrite"
1395t "std_logic"
1396o 29
1397suid 49,0
1398i "'1'"
1399)
1400)
1401)
1402*32 (CptPort
1403uid 185,0
1404ps "OnEdgeStrategy"
1405shape (Triangle
1406uid 186,0
1407ro 90
1408va (VaSet
1409vasetType 1
1410fg "0,65535,0"
1411)
1412xt "80250,57625,81000,58375"
1413)
1414tg (CPTG
1415uid 187,0
1416ps "CptPortTextPlaceStrategy"
1417stg "VerticalLayoutStrategy"
1418f (Text
1419uid 188,0
1420va (VaSet
1421)
1422xt "82000,57500,87400,58500"
1423st "SROUT_in_0"
1424blo "82000,58300"
1425)
1426)
1427thePort (LogicalPort
1428decl (Decl
1429n "SROUT_in_0"
1430t "std_logic"
1431o 3
1432suid 52,0
1433)
1434)
1435)
1436*33 (CptPort
1437uid 189,0
1438ps "OnEdgeStrategy"
1439shape (Triangle
1440uid 190,0
1441ro 90
1442va (VaSet
1443vasetType 1
1444fg "0,65535,0"
1445)
1446xt "80250,58625,81000,59375"
1447)
1448tg (CPTG
1449uid 191,0
1450ps "CptPortTextPlaceStrategy"
1451stg "VerticalLayoutStrategy"
1452f (Text
1453uid 192,0
1454va (VaSet
1455)
1456xt "82000,58500,87400,59500"
1457st "SROUT_in_1"
1458blo "82000,59300"
1459)
1460)
1461thePort (LogicalPort
1462decl (Decl
1463n "SROUT_in_1"
1464t "std_logic"
1465o 4
1466suid 53,0
1467)
1468)
1469)
1470*34 (CptPort
1471uid 193,0
1472ps "OnEdgeStrategy"
1473shape (Triangle
1474uid 194,0
1475ro 90
1476va (VaSet
1477vasetType 1
1478fg "0,65535,0"
1479)
1480xt "80250,59625,81000,60375"
1481)
1482tg (CPTG
1483uid 195,0
1484ps "CptPortTextPlaceStrategy"
1485stg "VerticalLayoutStrategy"
1486f (Text
1487uid 196,0
1488va (VaSet
1489)
1490xt "82000,59500,87400,60500"
1491st "SROUT_in_2"
1492blo "82000,60300"
1493)
1494)
1495thePort (LogicalPort
1496decl (Decl
1497n "SROUT_in_2"
1498t "std_logic"
1499o 5
1500suid 54,0
1501)
1502)
1503)
1504*35 (CptPort
1505uid 197,0
1506ps "OnEdgeStrategy"
1507shape (Triangle
1508uid 198,0
1509ro 90
1510va (VaSet
1511vasetType 1
1512fg "0,65535,0"
1513)
1514xt "80250,60625,81000,61375"
1515)
1516tg (CPTG
1517uid 199,0
1518ps "CptPortTextPlaceStrategy"
1519stg "VerticalLayoutStrategy"
1520f (Text
1521uid 200,0
1522va (VaSet
1523)
1524xt "82000,60500,87400,61500"
1525st "SROUT_in_3"
1526blo "82000,61300"
1527)
1528)
1529thePort (LogicalPort
1530decl (Decl
1531n "SROUT_in_3"
1532t "std_logic"
1533o 6
1534suid 55,0
1535)
1536)
1537)
1538*36 (CptPort
1539uid 201,0
1540ps "OnEdgeStrategy"
1541shape (Triangle
1542uid 202,0
1543ro 270
1544va (VaSet
1545vasetType 1
1546fg "0,65535,0"
1547)
1548xt "80250,63625,81000,64375"
1549)
1550tg (CPTG
1551uid 203,0
1552ps "CptPortTextPlaceStrategy"
1553stg "VerticalLayoutStrategy"
1554f (Text
1555uid 204,0
1556va (VaSet
1557)
1558xt "82000,63500,86200,64500"
1559st "RSRLOAD"
1560blo "82000,64300"
1561)
1562)
1563thePort (LogicalPort
1564m 1
1565decl (Decl
1566n "RSRLOAD"
1567t "std_logic"
1568o 18
1569suid 56,0
1570i "'0'"
1571)
1572)
1573)
1574*37 (CptPort
1575uid 205,0
1576ps "OnEdgeStrategy"
1577shape (Triangle
1578uid 206,0
1579ro 270
1580va (VaSet
1581vasetType 1
1582fg "0,65535,0"
1583)
1584xt "80250,64625,81000,65375"
1585)
1586tg (CPTG
1587uid 207,0
1588ps "CptPortTextPlaceStrategy"
1589stg "VerticalLayoutStrategy"
1590f (Text
1591uid 208,0
1592va (VaSet
1593)
1594xt "82000,64500,85000,65500"
1595st "SRCLK"
1596blo "82000,65300"
1597)
1598)
1599thePort (LogicalPort
1600m 1
1601decl (Decl
1602n "SRCLK"
1603t "std_logic"
1604o 19
1605suid 57,0
1606i "'0'"
1607)
1608)
1609)
1610*38 (CptPort
1611uid 209,0
1612ps "OnEdgeStrategy"
1613shape (Triangle
1614uid 210,0
1615ro 90
1616va (VaSet
1617vasetType 1
1618fg "0,65535,0"
1619)
1620xt "109000,50625,109750,51375"
1621)
1622tg (CPTG
1623uid 211,0
1624ps "CptPortTextPlaceStrategy"
1625stg "RightVerticalLayoutStrategy"
1626f (Text
1627uid 212,0
1628va (VaSet
1629)
1630xt "106300,50500,108000,51500"
1631st "sclk"
1632ju 2
1633blo "108000,51300"
1634)
1635)
1636thePort (LogicalPort
1637m 1
1638decl (Decl
1639n "sclk"
1640t "std_logic"
1641o 34
1642suid 62,0
1643)
1644)
1645)
1646*39 (CptPort
1647uid 213,0
1648ps "OnEdgeStrategy"
1649shape (Diamond
1650uid 214,0
1651ro 90
1652va (VaSet
1653vasetType 1
1654fg "0,65535,0"
1655)
1656xt "109000,51625,109750,52375"
1657)
1658tg (CPTG
1659uid 215,0
1660ps "CptPortTextPlaceStrategy"
1661stg "RightVerticalLayoutStrategy"
1662f (Text
1663uid 216,0
1664va (VaSet
1665)
1666xt "106600,51500,108000,52500"
1667st "sio"
1668ju 2
1669blo "108000,52300"
1670)
1671)
1672thePort (LogicalPort
1673m 2
1674decl (Decl
1675n "sio"
1676t "std_logic"
1677preAdd 0
1678posAdd 0
1679o 41
1680suid 63,0
1681)
1682)
1683)
1684*40 (CptPort
1685uid 217,0
1686ps "OnEdgeStrategy"
1687shape (Triangle
1688uid 218,0
1689ro 90
1690va (VaSet
1691vasetType 1
1692fg "0,65535,0"
1693)
1694xt "109000,39625,109750,40375"
1695)
1696tg (CPTG
1697uid 219,0
1698ps "CptPortTextPlaceStrategy"
1699stg "RightVerticalLayoutStrategy"
1700f (Text
1701uid 220,0
1702va (VaSet
1703)
1704xt "105200,39500,108000,40500"
1705st "dac_cs"
1706ju 2
1707blo "108000,40300"
1708)
1709)
1710thePort (LogicalPort
1711m 1
1712decl (Decl
1713n "dac_cs"
1714t "std_logic"
1715o 26
1716suid 64,0
1717)
1718)
1719)
1720*41 (CptPort
1721uid 221,0
1722ps "OnEdgeStrategy"
1723shape (Triangle
1724uid 222,0
1725ro 90
1726va (VaSet
1727vasetType 1
1728fg "0,65535,0"
1729)
1730xt "109000,41625,109750,42375"
1731)
1732tg (CPTG
1733uid 223,0
1734ps "CptPortTextPlaceStrategy"
1735stg "RightVerticalLayoutStrategy"
1736f (Text
1737uid 224,0
1738va (VaSet
1739)
1740xt "101500,41500,108000,42500"
1741st "sensor_cs : (3:0)"
1742ju 2
1743blo "108000,42300"
1744)
1745)
1746thePort (LogicalPort
1747m 1
1748decl (Decl
1749n "sensor_cs"
1750t "std_logic_vector"
1751b "(3 DOWNTO 0)"
1752o 35
1753suid 65,0
1754)
1755)
1756)
1757*42 (CptPort
1758uid 225,0
1759ps "OnEdgeStrategy"
1760shape (Triangle
1761uid 226,0
1762ro 90
1763va (VaSet
1764vasetType 1
1765fg "0,65535,0"
1766)
1767xt "109000,52625,109750,53375"
1768)
1769tg (CPTG
1770uid 227,0
1771ps "CptPortTextPlaceStrategy"
1772stg "RightVerticalLayoutStrategy"
1773f (Text
1774uid 228,0
1775va (VaSet
1776)
1777xt "106000,52500,108000,53500"
1778st "mosi"
1779ju 2
1780blo "108000,53300"
1781)
1782)
1783thePort (LogicalPort
1784m 1
1785decl (Decl
1786n "mosi"
1787t "std_logic"
1788o 32
1789suid 66,0
1790i "'0'"
1791)
1792)
1793)
1794*43 (CptPort
1795uid 229,0
1796ps "OnEdgeStrategy"
1797shape (Triangle
1798uid 230,0
1799ro 270
1800va (VaSet
1801vasetType 1
1802fg "0,65535,0"
1803)
1804xt "80250,65625,81000,66375"
1805)
1806tg (CPTG
1807uid 231,0
1808ps "CptPortTextPlaceStrategy"
1809stg "VerticalLayoutStrategy"
1810f (Text
1811uid 232,0
1812va (VaSet
1813)
1814xt "82000,65500,85000,66500"
1815st "denable"
1816blo "82000,66300"
1817)
1818)
1819thePort (LogicalPort
1820m 1
1821decl (Decl
1822n "denable"
1823t "std_logic"
1824eolc "-- default domino wave off"
1825posAdd 0
1826o 27
1827suid 67,0
1828i "'0'"
1829)
1830)
1831)
1832*44 (CptPort
1833uid 1395,0
1834ps "OnEdgeStrategy"
1835shape (Triangle
1836uid 1396,0
1837ro 90
1838va (VaSet
1839vasetType 1
1840fg "0,65535,0"
1841)
1842xt "109000,73625,109750,74375"
1843)
1844tg (CPTG
1845uid 1397,0
1846ps "CptPortTextPlaceStrategy"
1847stg "RightVerticalLayoutStrategy"
1848f (Text
1849uid 1398,0
1850va (VaSet
1851)
1852xt "99400,73500,108000,74500"
1853st "alarm_refclk_too_high"
1854ju 2
1855blo "108000,74300"
1856)
1857)
1858thePort (LogicalPort
1859m 1
1860decl (Decl
1861n "alarm_refclk_too_high"
1862t "std_logic"
1863o 22
1864suid 95,0
1865)
1866)
1867)
1868*45 (CptPort
1869uid 1399,0
1870ps "OnEdgeStrategy"
1871shape (Triangle
1872uid 1400,0
1873ro 90
1874va (VaSet
1875vasetType 1
1876fg "0,65535,0"
1877)
1878xt "109000,74625,109750,75375"
1879)
1880tg (CPTG
1881uid 1401,0
1882ps "CptPortTextPlaceStrategy"
1883stg "RightVerticalLayoutStrategy"
1884f (Text
1885uid 1402,0
1886va (VaSet
1887)
1888xt "99800,74500,108000,75500"
1889st "alarm_refclk_too_low"
1890ju 2
1891blo "108000,75300"
1892)
1893)
1894thePort (LogicalPort
1895m 1
1896decl (Decl
1897n "alarm_refclk_too_low"
1898t "std_logic"
1899posAdd 0
1900o 23
1901suid 96,0
1902)
1903)
1904)
1905*46 (CptPort
1906uid 1403,0
1907ps "OnEdgeStrategy"
1908shape (Triangle
1909uid 1404,0
1910ro 90
1911va (VaSet
1912vasetType 1
1913fg "0,65535,0"
1914)
1915xt "109000,79625,109750,80375"
1916)
1917tg (CPTG
1918uid 1405,0
1919ps "CptPortTextPlaceStrategy"
1920stg "RightVerticalLayoutStrategy"
1921f (Text
1922uid 1406,0
1923va (VaSet
1924)
1925xt "105500,79500,108000,80500"
1926st "amber"
1927ju 2
1928blo "108000,80300"
1929)
1930)
1931thePort (LogicalPort
1932m 1
1933decl (Decl
1934n "amber"
1935t "std_logic"
1936o 24
1937suid 87,0
1938)
1939)
1940)
1941*47 (CptPort
1942uid 1407,0
1943ps "OnEdgeStrategy"
1944shape (Triangle
1945uid 1408,0
1946ro 90
1947va (VaSet
1948vasetType 1
1949fg "0,65535,0"
1950)
1951xt "109000,76625,109750,77375"
1952)
1953tg (CPTG
1954uid 1409,0
1955ps "CptPortTextPlaceStrategy"
1956stg "RightVerticalLayoutStrategy"
1957f (Text
1958uid 1410,0
1959va (VaSet
1960)
1961xt "99400,76500,108000,77500"
1962st "counter_result : (11:0)"
1963ju 2
1964blo "108000,77300"
1965)
1966)
1967thePort (LogicalPort
1968m 1
1969decl (Decl
1970n "counter_result"
1971t "std_logic_vector"
1972b "(11 DOWNTO 0)"
1973o 25
1974suid 94,0
1975)
1976)
1977)
1978*48 (CptPort
1979uid 1411,0
1980ps "OnEdgeStrategy"
1981shape (Triangle
1982uid 1412,0
1983ro 90
1984va (VaSet
1985vasetType 1
1986fg "0,65535,0"
1987)
1988xt "80250,74625,81000,75375"
1989)
1990tg (CPTG
1991uid 1413,0
1992ps "CptPortTextPlaceStrategy"
1993stg "VerticalLayoutStrategy"
1994f (Text
1995uid 1414,0
1996va (VaSet
1997)
1998xt "82000,74500,87500,75500"
1999st "D_T_in : (1:0)"
2000blo "82000,75300"
2001)
2002)
2003thePort (LogicalPort
2004decl (Decl
2005n "D_T_in"
2006t "std_logic_vector"
2007b "(1 DOWNTO 0)"
2008o 2
2009suid 91,0
2010)
2011)
2012)
2013*49 (CptPort
2014uid 1415,0
2015ps "OnEdgeStrategy"
2016shape (Triangle
2017uid 1416,0
2018ro 90
2019va (VaSet
2020vasetType 1
2021fg "0,65535,0"
2022)
2023xt "80250,75625,81000,76375"
2024)
2025tg (CPTG
2026uid 1417,0
2027ps "CptPortTextPlaceStrategy"
2028stg "VerticalLayoutStrategy"
2029f (Text
2030uid 1418,0
2031va (VaSet
2032)
2033xt "82000,75500,87100,76500"
2034st "drs_refclk_in"
2035blo "82000,76300"
2036)
2037)
2038thePort (LogicalPort
2039decl (Decl
2040n "drs_refclk_in"
2041t "std_logic"
2042eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
2043o 11
2044suid 92,0
2045)
2046)
2047)
2048*50 (CptPort
2049uid 1419,0
2050ps "OnEdgeStrategy"
2051shape (Triangle
2052uid 1420,0
2053ro 90
2054va (VaSet
2055vasetType 1
2056fg "0,65535,0"
2057)
2058xt "109000,77625,109750,78375"
2059)
2060tg (CPTG
2061uid 1421,0
2062ps "CptPortTextPlaceStrategy"
2063stg "RightVerticalLayoutStrategy"
2064f (Text
2065uid 1422,0
2066va (VaSet
2067)
2068xt "105600,77500,108000,78500"
2069st "green"
2070ju 2
2071blo "108000,78300"
2072)
2073)
2074thePort (LogicalPort
2075m 1
2076decl (Decl
2077n "green"
2078t "std_logic"
2079o 30
2080suid 86,0
2081)
2082)
2083)
2084*51 (CptPort
2085uid 1423,0
2086ps "OnEdgeStrategy"
2087shape (Triangle
2088uid 1424,0
2089ro 90
2090va (VaSet
2091vasetType 1
2092fg "0,65535,0"
2093)
2094xt "80250,76625,81000,77375"
2095)
2096tg (CPTG
2097uid 1425,0
2098ps "CptPortTextPlaceStrategy"
2099stg "VerticalLayoutStrategy"
2100f (Text
2101uid 1426,0
2102va (VaSet
2103)
2104xt "82000,76500,88100,77500"
2105st "plllock_in : (3:0)"
2106blo "82000,77300"
2107)
2108)
2109thePort (LogicalPort
2110decl (Decl
2111n "plllock_in"
2112t "std_logic_vector"
2113b "(3 DOWNTO 0)"
2114eolc "-- high level, if dominowave is running and DRS PLL locked"
2115o 12
2116suid 93,0
2117)
2118)
2119)
2120*52 (CptPort
2121uid 1427,0
2122ps "OnEdgeStrategy"
2123shape (Triangle
2124uid 1428,0
2125ro 90
2126va (VaSet
2127vasetType 1
2128fg "0,65535,0"
2129)
2130xt "109000,78625,109750,79375"
2131)
2132tg (CPTG
2133uid 1429,0
2134ps "CptPortTextPlaceStrategy"
2135stg "RightVerticalLayoutStrategy"
2136f (Text
2137uid 1430,0
2138va (VaSet
2139)
2140xt "106500,78500,108000,79500"
2141st "red"
2142ju 2
2143blo "108000,79300"
2144)
2145)
2146thePort (LogicalPort
2147m 1
2148decl (Decl
2149n "red"
2150t "std_logic"
2151o 33
2152suid 88,0
2153)
2154)
2155)
2156*53 (CptPort
2157uid 1431,0
2158ps "OnEdgeStrategy"
2159shape (Triangle
2160uid 1432,0
2161ro 270
2162va (VaSet
2163vasetType 1
2164fg "0,65535,0"
2165)
2166xt "80250,71625,81000,72375"
2167)
2168tg (CPTG
2169uid 1433,0
2170ps "CptPortTextPlaceStrategy"
2171stg "VerticalLayoutStrategy"
2172f (Text
2173uid 1434,0
2174va (VaSet
2175)
2176xt "82000,71500,85700,72500"
2177st "SRIN_out"
2178blo "82000,72300"
2179)
2180)
2181thePort (LogicalPort
2182m 1
2183decl (Decl
2184n "SRIN_out"
2185t "std_logic"
2186o 20
2187suid 85,0
2188i "'0'"
2189)
2190)
2191)
2192*54 (CptPort
2193uid 1678,0
2194ps "OnEdgeStrategy"
2195shape (Triangle
2196uid 1679,0
2197ro 270
2198va (VaSet
2199vasetType 1
2200fg "0,65535,0"
2201)
2202xt "80250,23625,81000,24375"
2203)
2204tg (CPTG
2205uid 1680,0
2206ps "CptPortTextPlaceStrategy"
2207stg "VerticalLayoutStrategy"
2208f (Text
2209uid 1681,0
2210va (VaSet
2211)
2212xt "82000,23500,86000,24500"
2213st "ADC_CLK"
2214blo "82000,24300"
2215)
2216)
2217thePort (LogicalPort
2218lang 2
2219m 1
2220decl (Decl
2221n "ADC_CLK"
2222t "std_logic"
2223o 15
2224suid 97,0
2225)
2226)
2227)
2228]
2229shape (Rectangle
2230uid 234,0
2231va (VaSet
2232vasetType 1
2233fg "0,65535,0"
2234lineColor "0,32896,0"
2235lineWidth 2
2236)
2237xt "81000,19000,109000,81000"
2238)
2239oxt "15000,-8000,43000,46000"
2240ttg (MlTextGroup
2241uid 235,0
2242ps "CenterOffsetStrategy"
2243stg "VerticalLayoutStrategy"
2244textVec [
2245*55 (Text
2246uid 236,0
2247va (VaSet
2248font "Arial,8,1"
2249)
2250xt "83200,81000,89400,82000"
2251st "FACT_FAD_lib"
2252blo "83200,81800"
2253tm "BdLibraryNameMgr"
2254)
2255*56 (Text
2256uid 237,0
2257va (VaSet
2258font "Arial,8,1"
2259)
2260xt "83200,82000,87400,83000"
2261st "FAD_main"
2262blo "83200,82800"
2263tm "CptNameMgr"
2264)
2265*57 (Text
2266uid 238,0
2267va (VaSet
2268font "Arial,8,1"
2269)
2270xt "83200,83000,90000,84000"
2271st "I_mainTB_FPGA"
2272blo "83200,83800"
2273tm "InstanceNameMgr"
2274)
2275]
2276)
2277ga (GenericAssociation
2278uid 239,0
2279ps "EdgeToEdgeStrategy"
2280matrix (Matrix
2281uid 240,0
2282text (MLText
2283uid 241,0
2284va (VaSet
2285font "Courier New,8,0"
2286)
2287xt "81000,18200,101000,19000"
2288st "RAMADDRWIDTH64b = 15 ( integer ) "
2289)
2290header ""
2291)
2292elements [
2293(GiElement
2294name "RAMADDRWIDTH64b"
2295type "integer"
2296value "15"
2297)
2298]
2299)
2300viewicon (ZoomableIcon
2301uid 242,0
2302sl 0
2303va (VaSet
2304vasetType 1
2305fg "49152,49152,49152"
2306)
2307xt "81250,79250,82750,80750"
2308iconName "BlockDiagram.png"
2309iconMaskName "BlockDiagram.msk"
2310ftype 1
2311)
2312viewiconposition 0
2313portVis (PortSigDisplay
2314)
2315archFileType "UNKNOWN"
2316)
2317*58 (SaComponent
2318uid 274,0
2319optionalChildren [
2320*59 (CptPort
2321uid 266,0
2322ps "OnEdgeStrategy"
2323shape (Triangle
2324uid 267,0
2325ro 90
2326va (VaSet
2327vasetType 1
2328fg "0,65535,0"
2329)
2330xt "58000,20625,58750,21375"
2331)
2332tg (CPTG
2333uid 268,0
2334ps "CptPortTextPlaceStrategy"
2335stg "RightVerticalLayoutStrategy"
2336f (Text
2337uid 269,0
2338va (VaSet
2339)
2340xt "55700,20500,57000,21500"
2341st "clk"
2342ju 2
2343blo "57000,21300"
2344)
2345)
2346thePort (LogicalPort
2347m 1
2348decl (Decl
2349n "clk"
2350t "STD_LOGIC"
2351o 1
2352i "'0'"
2353)
2354)
2355)
2356*60 (CptPort
2357uid 270,0
2358ps "OnEdgeStrategy"
2359shape (Triangle
2360uid 271,0
2361ro 90
2362va (VaSet
2363vasetType 1
2364fg "0,65535,0"
2365)
2366xt "58000,21625,58750,22375"
2367)
2368tg (CPTG
2369uid 272,0
2370ps "CptPortTextPlaceStrategy"
2371stg "RightVerticalLayoutStrategy"
2372f (Text
2373uid 273,0
2374va (VaSet
2375)
2376xt "55700,21500,57000,22500"
2377st "rst"
2378ju 2
2379blo "57000,22300"
2380)
2381)
2382thePort (LogicalPort
2383m 1
2384decl (Decl
2385n "rst"
2386t "STD_LOGIC"
2387o 2
2388i "'0'"
2389)
2390)
2391)
2392]
2393shape (Rectangle
2394uid 275,0
2395va (VaSet
2396vasetType 1
2397fg "0,49152,49152"
2398lineColor "0,0,50000"
2399lineWidth 2
2400)
2401xt "50000,19000,58000,24000"
2402)
2403oxt "0,0,8000,10000"
2404ttg (MlTextGroup
2405uid 276,0
2406ps "CenterOffsetStrategy"
2407stg "VerticalLayoutStrategy"
2408textVec [
2409*61 (Text
2410uid 277,0
2411va (VaSet
2412font "Arial,8,1"
2413)
2414xt "50150,24000,57850,25000"
2415st "FACT_FAD_TB_lib"
2416blo "50150,24800"
2417tm "BdLibraryNameMgr"
2418)
2419*62 (Text
2420uid 278,0
2421va (VaSet
2422font "Arial,8,1"
2423)
2424xt "50150,25000,56850,26000"
2425st "clock_generator"
2426blo "50150,25800"
2427tm "CptNameMgr"
2428)
2429*63 (Text
2430uid 279,0
2431va (VaSet
2432font "Arial,8,1"
2433)
2434xt "50150,26000,56750,27000"
2435st "I_mainTB_clock"
2436blo "50150,26800"
2437tm "InstanceNameMgr"
2438)
2439]
2440)
2441ga (GenericAssociation
2442uid 280,0
2443ps "EdgeToEdgeStrategy"
2444matrix (Matrix
2445uid 281,0
2446text (MLText
2447uid 282,0
2448va (VaSet
2449font "Courier New,8,0"
2450)
2451xt "50000,17400,68500,19000"
2452st "clock_period = 20 ns ( time )
2453reset_time = 50 ns ( time ) "
2454)
2455header ""
2456)
2457elements [
2458(GiElement
2459name "clock_period"
2460type "time"
2461value "20 ns"
2462)
2463(GiElement
2464name "reset_time"
2465type "time"
2466value "50 ns"
2467)
2468]
2469)
2470viewicon (ZoomableIcon
2471uid 283,0
2472sl 0
2473va (VaSet
2474vasetType 1
2475fg "49152,49152,49152"
2476)
2477xt "50250,22250,51750,23750"
2478iconName "VhdlFileViewIcon.png"
2479iconMaskName "VhdlFileViewIcon.msk"
2480ftype 10
2481)
2482ordering 1
2483viewiconposition 0
2484portVis (PortSigDisplay
2485)
2486archFileType "UNKNOWN"
2487)
2488*64 (Net
2489uid 284,0
2490decl (Decl
2491n "clk"
2492t "STD_LOGIC"
2493preAdd 0
2494posAdd 0
2495o 1
2496suid 1,0
2497)
2498declText (MLText
2499uid 285,0
2500va (VaSet
2501font "Courier New,8,0"
2502)
2503xt "-90000,41400,-68000,42200"
2504st "SIGNAL clk : STD_LOGIC"
2505)
2506)
2507*65 (Net
2508uid 316,0
2509decl (Decl
2510n "wiz_addr"
2511t "std_logic_vector"
2512b "(9 DOWNTO 0)"
2513o 2
2514suid 2,0
2515)
2516declText (MLText
2517uid 317,0
2518va (VaSet
2519font "Courier New,8,0"
2520)
2521xt "-90000,54200,-58500,55000"
2522st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0)"
2523)
2524)
2525*66 (Net
2526uid 322,0
2527decl (Decl
2528n "wiz_data"
2529t "std_logic_vector"
2530b "(15 DOWNTO 0)"
2531o 3
2532suid 3,0
2533)
2534declText (MLText
2535uid 323,0
2536va (VaSet
2537font "Courier New,8,0"
2538)
2539xt "-90000,55800,-58000,56600"
2540st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0)"
2541)
2542)
2543*67 (Net
2544uid 328,0
2545decl (Decl
2546n "wiz_rd"
2547t "std_logic"
2548o 4
2549suid 4,0
2550i "'1'"
2551)
2552declText (MLText
2553uid 329,0
2554va (VaSet
2555font "Courier New,8,0"
2556)
2557xt "-90000,57400,-55000,58200"
2558st "SIGNAL wiz_rd : std_logic := '1'"
2559)
2560)
2561*68 (Net
2562uid 334,0
2563decl (Decl
2564n "wiz_wr"
2565t "std_logic"
2566o 5
2567suid 5,0
2568i "'1'"
2569)
2570declText (MLText
2571uid 335,0
2572va (VaSet
2573font "Courier New,8,0"
2574)
2575xt "-90000,59000,-55000,59800"
2576st "SIGNAL wiz_wr : std_logic := '1'"
2577)
2578)
2579*69 (SaComponent
2580uid 362,0
2581optionalChildren [
2582*70 (CptPort
2583uid 350,0
2584ps "OnEdgeStrategy"
2585shape (Triangle
2586uid 351,0
2587ro 90
2588va (VaSet
2589vasetType 1
2590fg "0,65535,0"
2591)
2592xt "122250,50625,123000,51375"
2593)
2594tg (CPTG
2595uid 352,0
2596ps "CptPortTextPlaceStrategy"
2597stg "VerticalLayoutStrategy"
2598f (Text
2599uid 353,0
2600va (VaSet
2601)
2602xt "124000,50500,125700,51500"
2603st "sclk"
2604blo "124000,51300"
2605)
2606)
2607thePort (LogicalPort
2608decl (Decl
2609n "sclk"
2610t "std_logic"
2611preAdd 0
2612posAdd 0
2613o 1
2614suid 1,0
2615)
2616)
2617)
2618*71 (CptPort
2619uid 354,0
2620ps "OnEdgeStrategy"
2621shape (Diamond
2622uid 355,0
2623ro 270
2624va (VaSet
2625vasetType 1
2626fg "0,65535,0"
2627)
2628xt "122250,51625,123000,52375"
2629)
2630tg (CPTG
2631uid 356,0
2632ps "CptPortTextPlaceStrategy"
2633stg "VerticalLayoutStrategy"
2634f (Text
2635uid 357,0
2636va (VaSet
2637)
2638xt "124000,51500,125400,52500"
2639st "sio"
2640blo "124000,52300"
2641)
2642)
2643thePort (LogicalPort
2644m 2
2645decl (Decl
2646n "sio"
2647t "std_logic"
2648preAdd 0
2649posAdd 0
2650o 2
2651suid 2,0
2652)
2653)
2654)
2655*72 (CptPort
2656uid 358,0
2657ps "OnEdgeStrategy"
2658shape (Triangle
2659uid 359,0
2660ro 90
2661va (VaSet
2662vasetType 1
2663fg "0,65535,0"
2664)
2665xt "122250,47625,123000,48375"
2666)
2667tg (CPTG
2668uid 360,0
2669ps "CptPortTextPlaceStrategy"
2670stg "VerticalLayoutStrategy"
2671f (Text
2672uid 361,0
2673va (VaSet
2674)
2675xt "124000,47500,130500,48500"
2676st "sensor_cs : (3:0)"
2677blo "124000,48300"
2678)
2679)
2680thePort (LogicalPort
2681decl (Decl
2682n "sensor_cs"
2683t "std_logic_vector"
2684b "(3 downto 0)"
2685preAdd 0
2686posAdd 0
2687o 3
2688suid 3,0
2689)
2690)
2691)
2692]
2693shape (Rectangle
2694uid 363,0
2695va (VaSet
2696vasetType 1
2697fg "0,49152,49152"
2698lineColor "0,0,50000"
2699lineWidth 2
2700)
2701xt "123000,46000,133000,56000"
2702)
2703oxt "30000,3000,40000,13000"
2704ttg (MlTextGroup
2705uid 364,0
2706ps "CenterOffsetStrategy"
2707stg "VerticalLayoutStrategy"
2708textVec [
2709*73 (Text
2710uid 365,0
2711va (VaSet
2712font "Arial,8,1"
2713)
2714xt "123200,56000,130900,57000"
2715st "FACT_FAD_TB_lib"
2716blo "123200,56800"
2717tm "BdLibraryNameMgr"
2718)
2719*74 (Text
2720uid 366,0
2721va (VaSet
2722font "Arial,8,1"
2723)
2724xt "123200,57000,130800,58000"
2725st "max6662_emulator"
2726blo "123200,57800"
2727tm "CptNameMgr"
2728)
2729*75 (Text
2730uid 367,0
2731va (VaSet
2732font "Arial,8,1"
2733)
2734xt "123200,58000,131000,59000"
2735st "I_mainTB_max6662"
2736blo "123200,58800"
2737tm "InstanceNameMgr"
2738)
2739]
2740)
2741ga (GenericAssociation
2742uid 368,0
2743ps "EdgeToEdgeStrategy"
2744matrix (Matrix
2745uid 369,0
2746text (MLText
2747uid 370,0
2748va (VaSet
2749font "Courier New,8,0"
2750)
2751xt "123000,45200,143000,46000"
2752st "DRS_TEMPERATURE = 51 ( integer ) "
2753)
2754header ""
2755)
2756elements [
2757(GiElement
2758name "DRS_TEMPERATURE"
2759type "integer"
2760value "51"
2761)
2762]
2763)
2764viewicon (ZoomableIcon
2765uid 371,0
2766sl 0
2767va (VaSet
2768vasetType 1
2769fg "49152,49152,49152"
2770)
2771xt "123250,54250,124750,55750"
2772iconName "VhdlFileViewIcon.png"
2773iconMaskName "VhdlFileViewIcon.msk"
2774ftype 10
2775)
2776ordering 1
2777viewiconposition 0
2778portVis (PortSigDisplay
2779sIVOD 1
2780)
2781archFileType "UNKNOWN"
2782)
2783*76 (Net
2784uid 372,0
2785decl (Decl
2786n "sensor_cs"
2787t "std_logic_vector"
2788b "(3 DOWNTO 0)"
2789o 6
2790suid 6,0
2791)
2792declText (MLText
2793uid 373,0
2794va (VaSet
2795font "Courier New,8,0"
2796)
2797xt "-90000,51800,-58500,52600"
2798st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)"
2799)
2800)
2801*77 (Net
2802uid 378,0
2803decl (Decl
2804n "sclk"
2805t "std_logic"
2806o 7
2807suid 7,0
2808)
2809declText (MLText
2810uid 379,0
2811va (VaSet
2812font "Courier New,8,0"
2813)
2814xt "-90000,51000,-68000,51800"
2815st "SIGNAL sclk : std_logic"
2816)
2817)
2818*78 (Net
2819uid 384,0
2820decl (Decl
2821n "sio"
2822t "std_logic"
2823preAdd 0
2824posAdd 0
2825o 8
2826suid 8,0
2827)
2828declText (MLText
2829uid 385,0
2830va (VaSet
2831font "Courier New,8,0"
2832)
2833xt "-90000,52600,-68000,53400"
2834st "SIGNAL sio : std_logic"
2835)
2836)
2837*79 (SaComponent
2838uid 414,0
2839optionalChildren [
2840*80 (CptPort
2841uid 410,0
2842ps "OnEdgeStrategy"
2843shape (Triangle
2844uid 411,0
2845ro 90
2846va (VaSet
2847vasetType 1
2848fg "0,65535,0"
2849)
2850xt "58000,31625,58750,32375"
2851)
2852tg (CPTG
2853uid 412,0
2854ps "CptPortTextPlaceStrategy"
2855stg "RightVerticalLayoutStrategy"
2856f (Text
2857uid 413,0
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2865)
2866thePort (LogicalPort
2867m 1
2868decl (Decl
2869n "trigger"
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2872posAdd 0
2873o 1
2874suid 1,0
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2877)
2878]
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2900xt "50200,36000,57900,37000"
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2902blo "50200,36800"
2903tm "BdLibraryNameMgr"
2904)
2905*82 (Text
2906uid 418,0
2907va (VaSet
2908font "Arial,8,1"
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2911st "trigger_generator"
2912blo "50200,37800"
2913tm "CptNameMgr"
2914)
2915*83 (Text
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2917va (VaSet
2918font "Arial,8,1"
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2922blo "50200,38800"
2923tm "InstanceNameMgr"
2924)
2925]
2926)
2927ga (GenericAssociation
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2929ps "EdgeToEdgeStrategy"
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2939PULSE_WIDTH = 20 ns ( time ) "
2940)
2941header ""
2942)
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2946type "time"
2947value "1 ms"
2948)
2949(GiElement
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2953)
2954]
2955)
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2965iconMaskName "VhdlFileViewIcon.msk"
2966ftype 10
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2968ordering 1
2969viewiconposition 0
2970portVis (PortSigDisplay
2971sIVOD 1
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2973archFileType "UNKNOWN"
2974)
2975*84 (Net
2976uid 424,0
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2981posAdd 0
2982o 9
2983suid 9,0
2984)
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2986uid 425,0
2987va (VaSet
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2993)
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3008lineWidth 2
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3013text (MLText
3014uid 439,0
3015va (VaSet
3016)
3017xt "50200,45200,60200,48200"
3018st "
3019-- eb_ID 1: hard-wired IDs
3020board_id <= \"0101\";
3021crate_id <= \"01\";
3022
3023"
3024tm "HdlTextMgr"
3025wrapOption 3
3026visibleHeight 4000
3027visibleWidth 10000
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3029)
3030)
3031]
3032shape (Rectangle
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3036fg "65535,65535,37120"
3037lineColor "0,0,32768"
3038lineWidth 2
3039)
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3042oxt "0,0,8000,10000"
3043ttg (MlTextGroup
3044uid 432,0
3045ps "CenterOffsetStrategy"
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3047textVec [
3048*87 (Text
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3050va (VaSet
3051font "Arial,8,1"
3052)
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3054st "eb_mainTB_ID"
3055blo "51150,41800"
3056tm "HdlTextNameMgr"
3057)
3058*88 (Text
3059uid 434,0
3060va (VaSet
3061font "Arial,8,1"
3062)
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3064st "1"
3065blo "51150,42800"
3066tm "HdlTextNumberMgr"
3067)
3068]
3069)
3070viewicon (ZoomableIcon
3071uid 435,0
3072sl 0
3073va (VaSet
3074vasetType 1
3075fg "49152,49152,49152"
3076)
3077xt "50250,43250,51750,44750"
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3082viewiconposition 0
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3089b "(3 downto 0)"
3090preAdd 0
3091posAdd 0
3092o 10
3093suid 10,0
3094)
3095declText (MLText
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3104*90 (Net
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3110o 11
3111suid 11,0
3112)
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3122*91 (SaComponent
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3124optionalChildren [
3125*92 (CptPort
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3130ro 90
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3135xt "29250,52625,30000,53375"
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3137tg (CPTG
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3139ps "CptPortTextPlaceStrategy"
3140stg "VerticalLayoutStrategy"
3141f (Text
3142uid 492,0
3143va (VaSet
3144)
3145xt "31000,52500,32300,53500"
3146st "clk"
3147blo "31000,53300"
3148)
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3150thePort (LogicalPort
3151decl (Decl
3152n "clk"
3153t "STD_LOGIC"
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3155posAdd 0
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3159)
3160)
3161*93 (CptPort
3162uid 493,0
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3166ro 90
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3168vasetType 1
3169fg "0,65535,0"
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3171xt "40000,54625,40750,55375"
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3173tg (CPTG
3174uid 495,0
3175ps "CptPortTextPlaceStrategy"
3176stg "RightVerticalLayoutStrategy"
3177f (Text
3178uid 496,0
3179va (VaSet
3180)
3181xt "34200,54500,39000,55500"
3182st "data : (11:0)"
3183ju 2
3184blo "39000,55300"
3185)
3186)
3187thePort (LogicalPort
3188m 1
3189decl (Decl
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3191t "STD_LOGIC_VECTOR"
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3194posAdd 0
3195o 2
3196suid 2,0
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3200*94 (CptPort
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3210xt "40000,52625,40750,53375"
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3212tg (CPTG
3213uid 499,0
3214ps "CptPortTextPlaceStrategy"
3215stg "RightVerticalLayoutStrategy"
3216f (Text
3217uid 500,0
3218va (VaSet
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3220xt "37700,52500,39000,53500"
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3222ju 2
3223blo "39000,53300"
3224)
3225)
3226thePort (LogicalPort
3227m 1
3228decl (Decl
3229n "otr"
3230t "STD_LOGIC"
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3232posAdd 0
3233o 3
3234suid 3,0
3235)
3236)
3237)
3238*95 (CptPort
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3243ro 270
3244va (VaSet
3245vasetType 1
3246fg "0,65535,0"
3247)
3248xt "40000,53625,40750,54375"
3249)
3250tg (CPTG
3251uid 503,0
3252ps "CptPortTextPlaceStrategy"
3253stg "RightVerticalLayoutStrategy"
3254f (Text
3255uid 504,0
3256va (VaSet
3257)
3258xt "37400,53500,39000,54500"
3259st "oeb"
3260ju 2
3261blo "39000,54300"
3262)
3263)
3264thePort (LogicalPort
3265decl (Decl
3266n "oeb"
3267t "STD_LOGIC"
3268preAdd 0
3269posAdd 0
3270o 4
3271suid 4,0
3272)
3273)
3274)
3275]
3276shape (Rectangle
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3281lineColor "0,0,50000"
3282lineWidth 2
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3284xt "30000,51000,40000,58000"
3285)
3286oxt "29000,7000,39000,17000"
3287ttg (MlTextGroup
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3290stg "VerticalLayoutStrategy"
3291textVec [
3292*96 (Text
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3294va (VaSet
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3296)
3297xt "30200,58000,37900,59000"
3298st "FACT_FAD_TB_lib"
3299blo "30200,58800"
3300tm "BdLibraryNameMgr"
3301)
3302*97 (Text
3303uid 512,0
3304va (VaSet
3305font "Arial,8,1"
3306)
3307xt "30200,59000,36000,60000"
3308st "adc_emulator"
3309blo "30200,59800"
3310tm "CptNameMgr"
3311)
3312*98 (Text
3313uid 513,0
3314va (VaSet
3315font "Arial,8,1"
3316)
3317xt "30200,60000,36200,61000"
3318st "I_mainTB_adc"
3319blo "30200,60800"
3320tm "InstanceNameMgr"
3321)
3322]
3323)
3324ga (GenericAssociation
3325uid 514,0
3326ps "EdgeToEdgeStrategy"
3327matrix (Matrix
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3329text (MLText
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3332font "Courier New,8,0"
3333)
3334xt "30000,50200,65500,51000"
3335st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\" ( string ) "
3336)
3337header ""
3338)
3339elements [
3340(GiElement
3341name "INPUT_FILE"
3342type "string"
3343value "\"../memory_files/analog_input_ch0.txt\""
3344)
3345]
3346)
3347viewicon (ZoomableIcon
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3352fg "49152,49152,49152"
3353)
3354xt "30250,56250,31750,57750"
3355iconName "VhdlFileViewIcon.png"
3356iconMaskName "VhdlFileViewIcon.msk"
3357ftype 10
3358)
3359ordering 1
3360viewiconposition 0
3361portVis (PortSigDisplay
3362sIVOD 1
3363)
3364archFileType "UNKNOWN"
3365)
3366*99 (HdlText
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3378fg "65535,65535,65535"
3379lineColor "0,0,32768"
3380lineWidth 2
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3382xt "50000,57000,62000,67000"
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3384oxt "0,0,18000,5000"
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3386uid 527,0
3387va (VaSet
3388)
3389xt "50200,57200,62100,66200"
3390st "
3391-- eb_adc 2: ADC routing
3392adc_data_array(0) <= adc_data;
3393adc_data_array(1) <= adc_data;
3394adc_data_array(2) <= adc_data;
3395adc_data_array(3) <= adc_data;
3396adc_otr_array(0) <= adc_otr;
3397adc_otr_array(1) <= adc_otr;
3398adc_otr_array(2) <= adc_otr;
3399adc_otr_array(3) <= adc_otr;
3400
3401"
3402tm "HdlTextMgr"
3403wrapOption 3
3404visibleHeight 10000
3405visibleWidth 12000
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3407)
3408)
3409]
3410shape (Rectangle
3411uid 519,0
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3415lineColor "0,0,32768"
3416lineWidth 2
3417)
3418xt "50000,51000,58000,57000"
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3420oxt "0,0,8000,10000"
3421ttg (MlTextGroup
3422uid 520,0
3423ps "CenterOffsetStrategy"
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3427uid 521,0
3428va (VaSet
3429font "Arial,8,1"
3430)
3431xt "51150,52000,57850,53000"
3432st "eb_mainTB_adc"
3433blo "51150,52800"
3434tm "HdlTextNameMgr"
3435)
3436*102 (Text
3437uid 522,0
3438va (VaSet
3439font "Arial,8,1"
3440)
3441xt "51150,53000,51950,54000"
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3443blo "51150,53800"
3444tm "HdlTextNumberMgr"
3445)
3446]
3447)
3448viewicon (ZoomableIcon
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3450sl 0
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3452vasetType 1
3453fg "49152,49152,49152"
3454)
3455xt "50250,55250,51750,56750"
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3460viewiconposition 0
3461)
3462*103 (Net
3463uid 528,0
3464decl (Decl
3465n "adc_otr_array"
3466t "std_logic_vector"
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3469suid 12,0
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3471declText (MLText
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3476xt "-90000,37400,-58500,38200"
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3479)
3480*104 (Net
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3486suid 13,0
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3495)
3496)
3497*105 (Net
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3500n "adc_oeb"
3501t "std_logic"
3502preAdd 0
3503posAdd 0
3504o 14
3505suid 14,0
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3507declText (MLText
3508uid 545,0
3509va (VaSet
3510font "Courier New,8,0"
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3512xt "-90000,35800,-68000,36600"
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3514)
3515)
3516*106 (Net
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3520t "STD_LOGIC"
3521preAdd 0
3522posAdd 0
3523o 16
3524suid 16,0
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3526declText (MLText
3527uid 561,0
3528va (VaSet
3529font "Courier New,8,0"
3530)
3531xt "-90000,36600,-68000,37400"
3532st "SIGNAL adc_otr : STD_LOGIC"
3533)
3534)
3535*107 (Net
3536uid 568,0
3537decl (Decl
3538n "adc_data"
3539t "std_logic_vector"
3540b "(11 DOWNTO 0)"
3541preAdd 0
3542posAdd 0
3543o 17
3544suid 17,0
3545)
3546declText (MLText
3547uid 569,0
3548va (VaSet
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3551xt "-90000,34200,-58000,35000"
3552st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)"
3553)
3554)
3555*108 (Net
3556uid 767,0
3557decl (Decl
3558n "wiz_reset"
3559t "std_logic"
3560o 21
3561suid 23,0
3562i "'1'"
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3564declText (MLText
3565uid 768,0
3566va (VaSet
3567font "Courier New,8,0"
3568)
3569xt "-90000,58200,-55000,59000"
3570st "SIGNAL wiz_reset : std_logic := '1'"
3571)
3572)
3573*109 (Net
3574uid 775,0
3575decl (Decl
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3577t "std_logic_vector"
3578b "(7 DOWNTO 0)"
3579posAdd 0
3580o 22
3581suid 24,0
3582i "(OTHERS => '0')"
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3584declText (MLText
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3586va (VaSet
3587font "Courier New,8,0"
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3590st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
3591)
3592)
3593*110 (Net
3594uid 783,0
3595decl (Decl
3596n "wiz_cs"
3597t "std_logic"
3598o 23
3599suid 25,0
3600i "'1'"
3601)
3602declText (MLText
3603uid 784,0
3604va (VaSet
3605font "Courier New,8,0"
3606)
3607xt "-90000,55000,-55000,55800"
3608st "SIGNAL wiz_cs : std_logic := '1'"
3609)
3610)
3611*111 (Net
3612uid 791,0
3613decl (Decl
3614n "wiz_int"
3615t "std_logic"
3616o 24
3617suid 26,0
3618)
3619declText (MLText
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3621va (VaSet
3622font "Courier New,8,0"
3623)
3624xt "-90000,56600,-68000,57400"
3625st "SIGNAL wiz_int : std_logic"
3626)
3627)
3628*112 (Net
3629uid 799,0
3630decl (Decl
3631n "dac_cs"
3632t "std_logic"
3633o 25
3634suid 27,0
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3636declText (MLText
3637uid 800,0
3638va (VaSet
3639font "Courier New,8,0"
3640)
3641xt "-90000,43800,-68000,44600"
3642st "SIGNAL dac_cs : std_logic"
3643)
3644)
3645*113 (Net
3646uid 807,0
3647decl (Decl
3648n "mosi"
3649t "std_logic"
3650o 26
3651suid 28,0
3652i "'0'"
3653)
3654declText (MLText
3655uid 808,0
3656va (VaSet
3657font "Courier New,8,0"
3658)
3659xt "-90000,48600,-55000,49400"
3660st "SIGNAL mosi : std_logic := '0'"
3661)
3662)
3663*114 (Net
3664uid 815,0
3665decl (Decl
3666n "denable"
3667t "std_logic"
3668eolc "-- default domino wave off"
3669posAdd 0
3670o 27
3671suid 29,0
3672i "'0'"
3673)
3674declText (MLText
3675uid 816,0
3676va (VaSet
3677font "Courier New,8,0"
3678)
3679xt "-90000,44600,-41500,45400"
3680st "SIGNAL denable : std_logic := '0' -- default domino wave off"
3681)
3682)
3683*115 (Net
3684uid 823,0
3685decl (Decl
3686n "CLK_25_PS"
3687t "std_logic"
3688o 28
3689suid 30,0
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3691declText (MLText
3692uid 824,0
3693va (VaSet
3694font "Courier New,8,0"
3695)
3696xt "-90000,25400,-68000,26200"
3697st "SIGNAL CLK_25_PS : std_logic"
3698)
3699)
3700*116 (Net
3701uid 831,0
3702decl (Decl
3703n "CLK_50"
3704t "std_logic"
3705o 29
3706suid 31,0
3707)
3708declText (MLText
3709uid 832,0
3710va (VaSet
3711font "Courier New,8,0"
3712)
3713xt "-90000,26200,-68000,27000"
3714st "SIGNAL CLK_50 : std_logic"
3715)
3716)
3717*117 (Net
3718uid 839,0
3719decl (Decl
3720n "drs_channel_id"
3721t "std_logic_vector"
3722b "(3 downto 0)"
3723o 30
3724suid 32,0
3725i "(others => '0')"
3726)
3727declText (MLText
3728uid 840,0
3729va (VaSet
3730font "Courier New,8,0"
3731)
3732xt "-90000,45400,-49000,46200"
3733st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')"
3734)
3735)
3736*118 (Net
3737uid 847,0
3738decl (Decl
3739n "drs_dwrite"
3740t "std_logic"
3741o 31
3742suid 33,0
3743i "'1'"
3744)
3745declText (MLText
3746uid 848,0
3747va (VaSet
3748font "Courier New,8,0"
3749)
3750xt "-90000,46200,-55000,47000"
3751st "SIGNAL drs_dwrite : std_logic := '1'"
3752)
3753)
3754*119 (Net
3755uid 855,0
3756decl (Decl
3757n "RSRLOAD"
3758t "std_logic"
3759o 32
3760suid 34,0
3761i "'0'"
3762)
3763declText (MLText
3764uid 856,0
3765va (VaSet
3766font "Courier New,8,0"
3767)
3768xt "-90000,28600,-55000,29400"
3769st "SIGNAL RSRLOAD : std_logic := '0'"
3770)
3771)
3772*120 (Net
3773uid 863,0
3774decl (Decl
3775n "SRCLK"
3776t "std_logic"
3777o 33
3778suid 35,0
3779i "'0'"
3780)
3781declText (MLText
3782uid 864,0
3783va (VaSet
3784font "Courier New,8,0"
3785)
3786xt "-90000,29400,-55000,30200"
3787st "SIGNAL SRCLK : std_logic := '0'"
3788)
3789)
3790*121 (Net
3791uid 871,0
3792decl (Decl
3793n "SROUT_in_0"
3794t "std_logic"
3795o 30
3796suid 36,0
3797)
3798declText (MLText
3799uid 872,0
3800va (VaSet
3801font "Courier New,8,0"
3802)
3803xt "-90000,31000,-68000,31800"
3804st "SIGNAL SROUT_in_0 : std_logic"
3805)
3806)
3807*122 (Net
3808uid 879,0
3809decl (Decl
3810n "SROUT_in_1"
3811t "std_logic"
3812o 31
3813suid 37,0
3814)
3815declText (MLText
3816uid 880,0
3817va (VaSet
3818font "Courier New,8,0"
3819)
3820xt "-90000,31800,-68000,32600"
3821st "SIGNAL SROUT_in_1 : std_logic"
3822)
3823)
3824*123 (Net
3825uid 887,0
3826decl (Decl
3827n "SROUT_in_2"
3828t "std_logic"
3829o 32
3830suid 38,0
3831)
3832declText (MLText
3833uid 888,0
3834va (VaSet
3835font "Courier New,8,0"
3836)
3837xt "-90000,32600,-68000,33400"
3838st "SIGNAL SROUT_in_2 : std_logic"
3839)
3840)
3841*124 (Net
3842uid 895,0
3843decl (Decl
3844n "SROUT_in_3"
3845t "std_logic"
3846o 33
3847suid 39,0
3848)
3849declText (MLText
3850uid 896,0
3851va (VaSet
3852font "Courier New,8,0"
3853)
3854xt "-90000,33400,-68000,34200"
3855st "SIGNAL SROUT_in_3 : std_logic"
3856)
3857)
3858*125 (Net
3859uid 1435,0
3860decl (Decl
3861n "SRIN_out"
3862t "std_logic"
3863o 34
3864suid 40,0
3865i "'0'"
3866)
3867declText (MLText
3868uid 1436,0
3869va (VaSet
3870font "Courier New,8,0"
3871)
3872xt "-90000,30200,-55000,31000"
3873st "SIGNAL SRIN_out : std_logic := '0'"
3874)
3875)
3876*126 (Net
3877uid 1443,0
3878decl (Decl
3879n "amber"
3880t "std_logic"
3881o 35
3882suid 41,0
3883)
3884declText (MLText
3885uid 1444,0
3886va (VaSet
3887font "Courier New,8,0"
3888)
3889xt "-90000,39800,-68000,40600"
3890st "SIGNAL amber : std_logic"
3891)
3892)
3893*127 (Net
3894uid 1451,0
3895decl (Decl
3896n "red"
3897t "std_logic"
3898o 36
3899suid 42,0
3900)
3901declText (MLText
3902uid 1452,0
3903va (VaSet
3904font "Courier New,8,0"
3905)
3906xt "-90000,50200,-68000,51000"
3907st "SIGNAL red : std_logic"
3908)
3909)
3910*128 (Net
3911uid 1459,0
3912decl (Decl
3913n "green"
3914t "std_logic"
3915o 37
3916suid 43,0
3917)
3918declText (MLText
3919uid 1460,0
3920va (VaSet
3921font "Courier New,8,0"
3922)
3923xt "-90000,47000,-68000,47800"
3924st "SIGNAL green : std_logic"
3925)
3926)
3927*129 (Net
3928uid 1467,0
3929decl (Decl
3930n "counter_result"
3931t "std_logic_vector"
3932b "(11 DOWNTO 0)"
3933o 38
3934suid 44,0
3935)
3936declText (MLText
3937uid 1468,0
3938va (VaSet
3939font "Courier New,8,0"
3940)
3941xt "-90000,42200,-58000,43000"
3942st "SIGNAL counter_result : std_logic_vector(11 DOWNTO 0)"
3943)
3944)
3945*130 (Net
3946uid 1475,0
3947decl (Decl
3948n "alarm_refclk_too_low"
3949t "std_logic"
3950posAdd 0
3951o 39
3952suid 45,0
3953)
3954declText (MLText
3955uid 1476,0
3956va (VaSet
3957font "Courier New,8,0"
3958)
3959xt "-90000,39000,-68000,39800"
3960st "SIGNAL alarm_refclk_too_low : std_logic"
3961)
3962)
3963*131 (Net
3964uid 1483,0
3965decl (Decl
3966n "alarm_refclk_too_high"
3967t "std_logic"
3968o 40
3969suid 46,0
3970)
3971declText (MLText
3972uid 1484,0
3973va (VaSet
3974font "Courier New,8,0"
3975)
3976xt "-90000,38200,-68000,39000"
3977st "SIGNAL alarm_refclk_too_high : std_logic"
3978)
3979)
3980*132 (HdlText
3981uid 1491,0
3982optionalChildren [
3983*133 (EmbeddedText
3984uid 1497,0
3985commentText (CommentText
3986uid 1498,0
3987ps "CenterOffsetStrategy"
3988shape (Rectangle
3989uid 1499,0
3990va (VaSet
3991vasetType 1
3992fg "65535,65535,65535"
3993lineColor "0,0,32768"
3994lineWidth 2
3995)
3996xt "27000,72000,41000,77000"
3997)
3998oxt "0,0,18000,5000"
3999text (MLText
4000uid 1500,0
4001va (VaSet
4002)
4003xt "27200,72200,39400,77200"
4004st "
4005
4006D_T_in(1 downto 0) <= \"00\";
4007plllock_in(3 downto 0) <= \"1111\";
4008SROUT_in_0 <= '1';
4009SROUT_in_1 <= '0';
4010SROUT_in_2 <= '1';
4011SROUT_in_3 <= '0';
4012
4013"
4014tm "HdlTextMgr"
4015wrapOption 3
4016visibleHeight 5000
4017visibleWidth 14000
4018)
4019)
4020)
4021]
4022shape (Rectangle
4023uid 1492,0
4024va (VaSet
4025vasetType 1
4026fg "65535,65535,37120"
4027lineColor "0,0,32768"
4028lineWidth 2
4029)
4030xt "27000,69000,35000,72000"
4031)
4032oxt "0,0,8000,10000"
4033ttg (MlTextGroup
4034uid 1493,0
4035ps "CenterOffsetStrategy"
4036stg "VerticalLayoutStrategy"
4037textVec [
4038*134 (Text
4039uid 1494,0
4040va (VaSet
4041font "Arial,8,1"
4042)
4043xt "28150,69000,35250,70000"
4044st "eb_mainTB_adc1"
4045blo "28150,69800"
4046tm "HdlTextNameMgr"
4047)
4048*135 (Text
4049uid 1495,0
4050va (VaSet
4051font "Arial,8,1"
4052)
4053xt "28150,70000,28950,71000"
4054st "3"
4055blo "28150,70800"
4056tm "HdlTextNumberMgr"
4057)
4058]
4059)
4060viewicon (ZoomableIcon
4061uid 1496,0
4062sl 0
4063va (VaSet
4064vasetType 1
4065fg "49152,49152,49152"
4066)
4067xt "27250,70250,28750,71750"
4068iconName "TextFile.png"
4069iconMaskName "TextFile.msk"
4070ftype 21
4071)
4072viewiconposition 0
4073)
4074*136 (Net
4075uid 1501,0
4076decl (Decl
4077n "D_T_in"
4078t "std_logic_vector"
4079b "(1 DOWNTO 0)"
4080o 41
4081suid 47,0
4082)
4083declText (MLText
4084uid 1502,0
4085va (VaSet
4086font "Courier New,8,0"
4087)
4088xt "-90000,27000,-58500,27800"
4089st "SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0)"
4090)
4091)
4092*137 (SaComponent
4093uid 1509,0
4094optionalChildren [
4095*138 (CptPort
4096uid 1519,0
4097ps "OnEdgeStrategy"
4098shape (Triangle
4099uid 1520,0
4100ro 90
4101va (VaSet
4102vasetType 1
4103fg "0,65535,0"
4104)
4105xt "66000,78625,66750,79375"
4106)
4107tg (CPTG
4108uid 1521,0
4109ps "CptPortTextPlaceStrategy"
4110stg "RightVerticalLayoutStrategy"
4111f (Text
4112uid 1522,0
4113va (VaSet
4114)
4115xt "63700,78500,65000,79500"
4116st "clk"
4117ju 2
4118blo "65000,79300"
4119)
4120)
4121thePort (LogicalPort
4122m 1
4123decl (Decl
4124n "clk"
4125t "STD_LOGIC"
4126o 1
4127i "'0'"
4128)
4129)
4130)
4131*139 (CptPort
4132uid 1523,0
4133ps "OnEdgeStrategy"
4134shape (Triangle
4135uid 1524,0
4136ro 90
4137va (VaSet
4138vasetType 1
4139fg "0,65535,0"
4140)
4141xt "66000,79625,66750,80375"
4142)
4143tg (CPTG
4144uid 1525,0
4145ps "CptPortTextPlaceStrategy"
4146stg "RightVerticalLayoutStrategy"
4147f (Text
4148uid 1526,0
4149va (VaSet
4150)
4151xt "63700,79500,65000,80500"
4152st "rst"
4153ju 2
4154blo "65000,80300"
4155)
4156)
4157thePort (LogicalPort
4158m 1
4159decl (Decl
4160n "rst"
4161t "STD_LOGIC"
4162o 2
4163i "'0'"
4164)
4165)
4166)
4167]
4168shape (Rectangle
4169uid 1510,0
4170va (VaSet
4171vasetType 1
4172fg "0,49152,49152"
4173lineColor "0,0,50000"
4174lineWidth 2
4175)
4176xt "55000,77000,66000,82000"
4177)
4178oxt "0,0,8000,10000"
4179ttg (MlTextGroup
4180uid 1511,0
4181ps "CenterOffsetStrategy"
4182stg "VerticalLayoutStrategy"
4183textVec [
4184*140 (Text
4185uid 1512,0
4186va (VaSet
4187font "Arial,8,1"
4188)
4189xt "56150,78000,63850,79000"
4190st "FACT_FAD_TB_lib"
4191blo "56150,78800"
4192tm "BdLibraryNameMgr"
4193)
4194*141 (Text
4195uid 1513,0
4196va (VaSet
4197font "Arial,8,1"
4198)
4199xt "56150,79000,62850,80000"
4200st "clock_generator"
4201blo "56150,79800"
4202tm "CptNameMgr"
4203)
4204*142 (Text
4205uid 1514,0
4206va (VaSet
4207font "Arial,8,1"
4208)
4209xt "56150,80000,63150,81000"
4210st "I_mainTB_clock1"
4211blo "56150,80800"
4212tm "InstanceNameMgr"
4213)
4214]
4215)
4216ga (GenericAssociation
4217uid 1515,0
4218ps "EdgeToEdgeStrategy"
4219matrix (Matrix
4220uid 1516,0
4221text (MLText
4222uid 1517,0
4223va (VaSet
4224font "Courier New,8,0"
4225)
4226xt "55000,82400,73000,84000"
4227st "clock_period = 1 us ( time )
4228reset_time = 1 us ( time ) "
4229)
4230header ""
4231)
4232elements [
4233(GiElement
4234name "clock_period"
4235type "time"
4236value "1 us"
4237)
4238(GiElement
4239name "reset_time"
4240type "time"
4241value "1 us"
4242)
4243]
4244)
4245viewicon (ZoomableIcon
4246uid 1518,0
4247sl 0
4248va (VaSet
4249vasetType 1
4250fg "49152,49152,49152"
4251)
4252xt "55250,80250,56750,81750"
4253iconName "VhdlFileViewIcon.png"
4254iconMaskName "VhdlFileViewIcon.msk"
4255ftype 10
4256)
4257ordering 1
4258viewiconposition 0
4259portVis (PortSigDisplay
4260)
4261archFileType "UNKNOWN"
4262)
4263*143 (Net
4264uid 1559,0
4265decl (Decl
4266n "plllock_in"
4267t "std_logic_vector"
4268b "(3 DOWNTO 0)"
4269eolc "-- high level, if dominowave is running and DRS PLL locked"
4270o 43
4271suid 49,0
4272)
4273declText (MLText
4274uid 1560,0
4275va (VaSet
4276font "Courier New,8,0"
4277)
4278xt "-90000,49400,-29000,50200"
4279st "SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
4280)
4281)
4282*144 (Net
4283uid 1682,0
4284lang 2
4285decl (Decl
4286n "ADC_CLK"
4287t "std_logic"
4288o 44
4289suid 50,0
4290)
4291declText (MLText
4292uid 1683,0
4293va (VaSet
4294font "Courier New,8,0"
4295)
4296xt "-90000,24600,-68000,25400"
4297st "SIGNAL ADC_CLK : std_logic"
4298)
4299)
4300*145 (Net
4301uid 2001,0
4302decl (Decl
4303n "REF_CLK"
4304t "STD_LOGIC"
4305o 42
4306suid 51,0
4307i "'0'"
4308)
4309declText (MLText
4310uid 2002,0
4311va (VaSet
4312font "Courier New,8,0"
4313)
4314xt "-90000,27800,-55000,28600"
4315st "SIGNAL REF_CLK : STD_LOGIC := '0'"
4316)
4317)
4318*146 (SaComponent
4319uid 2336,0
4320optionalChildren [
4321*147 (CptPort
4322uid 2315,0
4323ps "OnEdgeStrategy"
4324shape (Triangle
4325uid 2316,0
4326ro 90
4327va (VaSet
4328vasetType 1
4329fg "0,65535,0"
4330)
4331xt "122250,20625,123000,21375"
4332)
4333tg (CPTG
4334uid 2317,0
4335ps "CptPortTextPlaceStrategy"
4336stg "VerticalLayoutStrategy"
4337f (Text
4338uid 2318,0
4339va (VaSet
4340)
4341xt "124000,20500,128500,21500"
4342st "addr : (9:0)"
4343blo "124000,21300"
4344)
4345)
4346thePort (LogicalPort
4347decl (Decl
4348n "addr"
4349t "std_logic_vector"
4350b "(9 DOWNTO 0)"
4351preAdd 0
4352posAdd 0
4353o 2
4354suid 1,0
4355)
4356)
4357)
4358*148 (CptPort
4359uid 2319,0
4360ps "OnEdgeStrategy"
4361shape (Diamond
4362uid 2320,0
4363ro 270
4364va (VaSet
4365vasetType 1
4366fg "0,65535,0"
4367)
4368xt "122250,21625,123000,22375"
4369)
4370tg (CPTG
4371uid 2321,0
4372ps "CptPortTextPlaceStrategy"
4373stg "VerticalLayoutStrategy"
4374f (Text
4375uid 2322,0
4376va (VaSet
4377)
4378xt "124000,21500,128800,22500"
4379st "data : (15:0)"
4380blo "124000,22300"
4381)
4382)
4383thePort (LogicalPort
4384m 2
4385decl (Decl
4386n "data"
4387t "std_logic_vector"
4388b "(15 DOWNTO 0)"
4389preAdd 0
4390posAdd 0
4391o 3
4392suid 2,0
4393)
4394)
4395)
4396*149 (CptPort
4397uid 2323,0
4398ps "OnEdgeStrategy"
4399shape (Triangle
4400uid 2324,0
4401ro 90
4402va (VaSet
4403vasetType 1
4404fg "0,65535,0"
4405)
4406xt "122250,24625,123000,25375"
4407)
4408tg (CPTG
4409uid 2325,0
4410ps "CptPortTextPlaceStrategy"
4411stg "VerticalLayoutStrategy"
4412f (Text
4413uid 2326,0
4414va (VaSet
4415)
4416xt "124000,24500,125100,25500"
4417st "rd"
4418blo "124000,25300"
4419)
4420)
4421thePort (LogicalPort
4422decl (Decl
4423n "rd"
4424t "std_logic"
4425preAdd 0
4426posAdd 0
4427o 4
4428suid 3,0
4429)
4430)
4431)
4432*150 (CptPort
4433uid 2327,0
4434ps "OnEdgeStrategy"
4435shape (Triangle
4436uid 2328,0
4437ro 90
4438va (VaSet
4439vasetType 1
4440fg "0,65535,0"
4441)
4442xt "122250,25625,123000,26375"
4443)
4444tg (CPTG
4445uid 2329,0
4446ps "CptPortTextPlaceStrategy"
4447stg "VerticalLayoutStrategy"
4448f (Text
4449uid 2330,0
4450va (VaSet
4451)
4452xt "124000,25500,125200,26500"
4453st "wr"
4454blo "124000,26300"
4455)
4456)
4457thePort (LogicalPort
4458decl (Decl
4459n "wr"
4460t "std_logic"
4461prec "-- int : out std_logic := '1';"
4462preAdd 0
4463posAdd 0
4464o 5
4465suid 4,0
4466)
4467)
4468)
4469*151 (CptPort
4470uid 2331,0
4471ps "OnEdgeStrategy"
4472shape (Triangle
4473uid 2332,0
4474ro 270
4475va (VaSet
4476vasetType 1
4477fg "0,65535,0"
4478)
4479xt "122250,26625,123000,27375"
4480)
4481tg (CPTG
4482uid 2333,0
4483ps "CptPortTextPlaceStrategy"
4484stg "VerticalLayoutStrategy"
4485f (Text
4486uid 2334,0
4487va (VaSet
4488)
4489xt "124000,26500,125200,27500"
4490st "int"
4491blo "124000,27300"
4492)
4493t (Text
4494uid 2335,0
4495va (VaSet
4496)
4497xt "124000,27500,125200,28500"
4498st "'0'"
4499blo "124000,28300"
4500)
4501)
4502thePort (LogicalPort
4503m 1
4504decl (Decl
4505n "int"
4506t "std_logic"
4507o 1
4508suid 5,0
4509i "'0'"
4510)
4511)
4512)
4513]
4514shape (Rectangle
4515uid 2337,0
4516va (VaSet
4517vasetType 1
4518fg "0,49152,49152"
4519lineColor "0,0,50000"
4520lineWidth 2
4521)
4522xt "123000,19000,133000,31000"
4523)
4524oxt "29000,0,39000,12000"
4525ttg (MlTextGroup
4526uid 2338,0
4527ps "CenterOffsetStrategy"
4528stg "VerticalLayoutStrategy"
4529textVec [
4530*152 (Text
4531uid 2339,0
4532va (VaSet
4533font "Arial,8,1"
4534)
4535xt "123200,31000,130900,32000"
4536st "FACT_FAD_TB_lib"
4537blo "123200,31800"
4538tm "BdLibraryNameMgr"
4539)
4540*153 (Text
4541uid 2340,0
4542va (VaSet
4543font "Arial,8,1"
4544)
4545xt "123200,32000,129800,33000"
4546st "w5300_emulator"
4547blo "123200,32800"
4548tm "CptNameMgr"
4549)
4550*154 (Text
4551uid 2341,0
4552va (VaSet
4553font "Arial,8,1"
4554)
4555xt "123200,33000,130000,34000"
4556st "I_mainTB_w5300"
4557blo "123200,33800"
4558tm "InstanceNameMgr"
4559)
4560]
4561)
4562ga (GenericAssociation
4563uid 2342,0
4564ps "EdgeToEdgeStrategy"
4565matrix (Matrix
4566uid 2343,0
4567text (MLText
4568uid 2344,0
4569va (VaSet
4570font "Courier New,8,0"
4571)
4572xt "123000,18000,123000,18000"
4573)
4574header ""
4575)
4576elements [
4577]
4578)
4579viewicon (ZoomableIcon
4580uid 2345,0
4581sl 0
4582va (VaSet
4583vasetType 1
4584fg "49152,49152,49152"
4585)
4586xt "123250,29250,124750,30750"
4587iconName "VhdlFileViewIcon.png"
4588iconMaskName "VhdlFileViewIcon.msk"
4589ftype 10
4590)
4591ordering 1
4592viewiconposition 0
4593portVis (PortSigDisplay
4594sIVOD 1
4595)
4596archFileType "UNKNOWN"
4597)
4598*155 (Wire
4599uid 286,0
4600shape (OrthoPolyLine
4601uid 287,0
4602va (VaSet
4603vasetType 3
4604)
4605xt "58750,21000,80250,21000"
4606pts [
4607"58750,21000"
4608"80250,21000"
4609]
4610)
4611start &59
4612end &27
4613sat 32
4614eat 32
4615st 0
4616sf 1
4617si 0
4618tg (WTG
4619uid 288,0
4620ps "ConnStartEndStrategy"
4621stg "STSignalDisplayStrategy"
4622f (Text
4623uid 289,0
4624va (VaSet
4625)
4626xt "71000,20000,72300,21000"
4627st "clk"
4628blo "71000,20800"
4629tm "WireNameMgr"
4630)
4631)
4632on &64
4633)
4634*156 (Wire
4635uid 318,0
4636shape (OrthoPolyLine
4637uid 319,0
4638va (VaSet
4639vasetType 3
4640lineWidth 2
4641)
4642xt "109750,21000,122250,21000"
4643pts [
4644"109750,21000"
4645"122250,21000"
4646]
4647)
4648start &19
4649end &147
4650sat 32
4651eat 32
4652sty 1
4653st 0
4654sf 1
4655si 0
4656tg (WTG
4657uid 320,0
4658ps "ConnStartEndStrategy"
4659stg "STSignalDisplayStrategy"
4660f (Text
4661uid 321,0
4662va (VaSet
4663)
4664xt "111000,20000,117000,21000"
4665st "wiz_addr : (9:0)"
4666blo "111000,20800"
4667tm "WireNameMgr"
4668)
4669)
4670on &65
4671)
4672*157 (Wire
4673uid 324,0
4674shape (OrthoPolyLine
4675uid 325,0
4676va (VaSet
4677vasetType 3
4678lineWidth 2
4679)
4680xt "109750,22000,122250,22000"
4681pts [
4682"109750,22000"
4683"122250,22000"
4684]
4685)
4686start &20
4687end &148
4688sat 32
4689eat 32
4690sty 1
4691st 0
4692sf 1
4693si 0
4694tg (WTG
4695uid 326,0
4696ps "ConnStartEndStrategy"
4697stg "STSignalDisplayStrategy"
4698f (Text
4699uid 327,0
4700va (VaSet
4701)
4702xt "111000,21000,117300,22000"
4703st "wiz_data : (15:0)"
4704blo "111000,21800"
4705tm "WireNameMgr"
4706)
4707)
4708on &66
4709)
4710*158 (Wire
4711uid 330,0
4712shape (OrthoPolyLine
4713uid 331,0
4714va (VaSet
4715vasetType 3
4716)
4717xt "109750,25000,122250,25000"
4718pts [
4719"109750,25000"
4720"122250,25000"
4721]
4722)
4723start &23
4724end &149
4725sat 32
4726eat 32
4727st 0
4728sf 1
4729si 0
4730tg (WTG
4731uid 332,0
4732ps "ConnStartEndStrategy"
4733stg "STSignalDisplayStrategy"
4734f (Text
4735uid 333,0
4736va (VaSet
4737)
4738xt "111000,24000,113600,25000"
4739st "wiz_rd"
4740blo "111000,24800"
4741tm "WireNameMgr"
4742)
4743)
4744on &67
4745)
4746*159 (Wire
4747uid 336,0
4748shape (OrthoPolyLine
4749uid 337,0
4750va (VaSet
4751vasetType 3
4752)
4753xt "109750,26000,122250,26000"
4754pts [
4755"109750,26000"
4756"122250,26000"
4757]
4758)
4759start &22
4760end &150
4761sat 32
4762eat 32
4763st 0
4764sf 1
4765si 0
4766tg (WTG
4767uid 338,0
4768ps "ConnStartEndStrategy"
4769stg "STSignalDisplayStrategy"
4770f (Text
4771uid 339,0
4772va (VaSet
4773)
4774xt "111000,25000,113700,26000"
4775st "wiz_wr"
4776blo "111000,25800"
4777tm "WireNameMgr"
4778)
4779)
4780on &68
4781)
4782*160 (Wire
4783uid 374,0
4784shape (OrthoPolyLine
4785uid 375,0
4786va (VaSet
4787vasetType 3
4788lineWidth 2
4789)
4790xt "109750,42000,122250,48000"
4791pts [
4792"109750,42000"
4793"120000,42000"
4794"120000,48000"
4795"122250,48000"
4796]
4797)
4798start &41
4799end &72
4800sat 32
4801eat 32
4802sty 1
4803st 0
4804sf 1
4805si 0
4806tg (WTG
4807uid 376,0
4808ps "ConnStartEndStrategy"
4809stg "STSignalDisplayStrategy"
4810f (Text
4811uid 377,0
4812va (VaSet
4813)
4814xt "111000,41000,117500,42000"
4815st "sensor_cs : (3:0)"
4816blo "111000,41800"
4817tm "WireNameMgr"
4818)
4819)
4820on &76
4821)
4822*161 (Wire
4823uid 380,0
4824shape (OrthoPolyLine
4825uid 381,0
4826va (VaSet
4827vasetType 3
4828)
4829xt "109750,51000,122250,51000"
4830pts [
4831"109750,51000"
4832"122250,51000"
4833]
4834)
4835start &38
4836end &70
4837sat 32
4838eat 32
4839st 0
4840sf 1
4841si 0
4842tg (WTG
4843uid 382,0
4844ps "ConnStartEndStrategy"
4845stg "STSignalDisplayStrategy"
4846f (Text
4847uid 383,0
4848va (VaSet
4849)
4850xt "111000,50000,112700,51000"
4851st "sclk"
4852blo "111000,50800"
4853tm "WireNameMgr"
4854)
4855)
4856on &77
4857)
4858*162 (Wire
4859uid 386,0
4860shape (OrthoPolyLine
4861uid 387,0
4862va (VaSet
4863vasetType 3
4864)
4865xt "109750,52000,122250,52000"
4866pts [
4867"109750,52000"
4868"122250,52000"
4869]
4870)
4871start &39
4872end &71
4873sat 32
4874eat 32
4875st 0
4876sf 1
4877si 0
4878tg (WTG
4879uid 388,0
4880ps "ConnStartEndStrategy"
4881stg "STSignalDisplayStrategy"
4882f (Text
4883uid 389,0
4884va (VaSet
4885)
4886xt "111000,51000,112400,52000"
4887st "sio"
4888blo "111000,51800"
4889tm "WireNameMgr"
4890)
4891)
4892on &78
4893)
4894*163 (Wire
4895uid 426,0
4896shape (OrthoPolyLine
4897uid 427,0
4898va (VaSet
4899vasetType 3
4900)
4901xt "58750,32000,80250,32000"
4902pts [
4903"58750,32000"
4904"80250,32000"
4905]
4906)
4907start &80
4908end &15
4909sat 32
4910eat 32
4911st 0
4912sf 1
4913tg (WTG
4914uid 428,0
4915ps "ConnStartEndStrategy"
4916stg "STSignalDisplayStrategy"
4917f (Text
4918uid 429,0
4919va (VaSet
4920)
4921xt "71000,31000,73800,32000"
4922st "trigger"
4923blo "71000,31800"
4924tm "WireNameMgr"
4925)
4926)
4927on &84
4928)
4929*164 (Wire
4930uid 442,0
4931shape (OrthoPolyLine
4932uid 443,0
4933va (VaSet
4934vasetType 3
4935lineWidth 2
4936)
4937xt "58000,34000,80250,42000"
4938pts [
4939"80250,34000"
4940"64000,34000"
4941"64000,42000"
4942"58000,42000"
4943]
4944)
4945start &17
4946end &85
4947sat 32
4948eat 2
4949sty 1
4950st 0
4951sf 1
4952si 0
4953tg (WTG
4954uid 446,0
4955ps "ConnStartEndStrategy"
4956stg "STSignalDisplayStrategy"
4957f (Text
4958uid 447,0
4959va (VaSet
4960)
4961xt "71000,33000,76900,34000"
4962st "board_id : (3:0)"
4963blo "71000,33800"
4964tm "WireNameMgr"
4965)
4966)
4967on &89
4968)
4969*165 (Wire
4970uid 450,0
4971shape (OrthoPolyLine
4972uid 451,0
4973va (VaSet
4974vasetType 3
4975lineWidth 2
4976)
4977xt "58000,35000,80250,43000"
4978pts [
4979"80250,35000"
4980"65000,35000"
4981"65000,43000"
4982"58000,43000"
4983]
4984)
4985start &18
4986end &85
4987sat 32
4988eat 2
4989sty 1
4990st 0
4991sf 1
4992si 0
4993tg (WTG
4994uid 454,0
4995ps "ConnStartEndStrategy"
4996stg "STSignalDisplayStrategy"
4997f (Text
4998uid 455,0
4999va (VaSet
5000)
5001xt "71000,34000,76700,35000"
5002st "crate_id : (1:0)"
5003blo "71000,34800"
5004tm "WireNameMgr"
5005)
5006)
5007on &90
5008)
5009*166 (Wire
5010uid 530,0
5011shape (OrthoPolyLine
5012uid 531,0
5013va (VaSet
5014vasetType 3
5015lineWidth 2
5016)
5017xt "58000,42000,80250,53000"
5018pts [
5019"80250,42000"
5020"68000,42000"
5021"68000,53000"
5022"58000,53000"
5023]
5024)
5025start &28
5026end &99
5027sat 32
5028eat 2
5029sty 1
5030st 0
5031sf 1
5032si 0
5033tg (WTG
5034uid 534,0
5035ps "ConnStartEndStrategy"
5036stg "STSignalDisplayStrategy"
5037f (Text
5038uid 535,0
5039va (VaSet
5040)
5041xt "71000,41000,79000,42000"
5042st "adc_otr_array : (3:0)"
5043blo "71000,41800"
5044tm "WireNameMgr"
5045)
5046)
5047on &103
5048)
5049*167 (Wire
5050uid 538,0
5051shape (OrthoPolyLine
5052uid 539,0
5053va (VaSet
5054vasetType 3
5055lineWidth 2
5056)
5057xt "58000,48000,80250,55000"
5058pts [
5059"80250,48000"
5060"70000,48000"
5061"70000,55000"
5062"58000,55000"
5063]
5064)
5065start &29
5066end &99
5067sat 32
5068eat 2
5069sty 1
5070st 0
5071sf 1
5072si 0
5073tg (WTG
5074uid 542,0
5075ps "ConnStartEndStrategy"
5076stg "STSignalDisplayStrategy"
5077f (Text
5078uid 543,0
5079va (VaSet
5080)
5081xt "71000,47000,76900,48000"
5082st "adc_data_array"
5083blo "71000,47800"
5084tm "WireNameMgr"
5085)
5086)
5087on &104
5088)
5089*168 (Wire
5090uid 546,0
5091shape (OrthoPolyLine
5092uid 547,0
5093va (VaSet
5094vasetType 3
5095)
5096xt "58000,43000,80250,54000"
5097pts [
5098"80250,43000"
5099"69000,43000"
5100"69000,54000"
5101"58000,54000"
5102]
5103)
5104start &16
5105end &99
5106sat 32
5107eat 1
5108st 0
5109sf 1
5110si 0
5111tg (WTG
5112uid 550,0
5113ps "ConnStartEndStrategy"
5114stg "STSignalDisplayStrategy"
5115f (Text
5116uid 551,0
5117va (VaSet
5118)
5119xt "71000,42000,74200,43000"
5120st "adc_oeb"
5121blo "71000,42800"
5122tm "WireNameMgr"
5123)
5124)
5125on &105
5126)
5127*169 (Wire
5128uid 554,0
5129shape (OrthoPolyLine
5130uid 555,0
5131va (VaSet
5132vasetType 3
5133)
5134xt "40750,54000,50000,54000"
5135pts [
5136"50000,54000"
5137"40750,54000"
5138]
5139)
5140start &99
5141end &95
5142sat 2
5143eat 32
5144st 0
5145sf 1
5146tg (WTG
5147uid 558,0
5148ps "ConnStartEndStrategy"
5149stg "STSignalDisplayStrategy"
5150f (Text
5151uid 559,0
5152va (VaSet
5153)
5154xt "42000,53000,45200,54000"
5155st "adc_oeb"
5156blo "42000,53800"
5157tm "WireNameMgr"
5158)
5159)
5160on &105
5161)
5162*170 (Wire
5163uid 562,0
5164shape (OrthoPolyLine
5165uid 563,0
5166va (VaSet
5167vasetType 3
5168)
5169xt "40750,53000,50000,53000"
5170pts [
5171"40750,53000"
5172"50000,53000"
5173]
5174)
5175start &94
5176end &99
5177sat 32
5178eat 1
5179st 0
5180sf 1
5181tg (WTG
5182uid 566,0
5183ps "ConnStartEndStrategy"
5184stg "STSignalDisplayStrategy"
5185f (Text
5186uid 567,0
5187va (VaSet
5188)
5189xt "42000,52000,44900,53000"
5190st "adc_otr"
5191blo "42000,52800"
5192tm "WireNameMgr"
5193)
5194)
5195on &106
5196)
5197*171 (Wire
5198uid 570,0
5199shape (OrthoPolyLine
5200uid 571,0
5201va (VaSet
5202vasetType 3
5203lineWidth 2
5204)
5205xt "40750,55000,50000,55000"
5206pts [
5207"40750,55000"
5208"50000,55000"
5209]
5210)
5211start &93
5212end &99
5213sat 32
5214eat 1
5215sty 1
5216st 0
5217sf 1
5218tg (WTG
5219uid 574,0
5220ps "ConnStartEndStrategy"
5221stg "STSignalDisplayStrategy"
5222f (Text
5223uid 575,0
5224va (VaSet
5225)
5226xt "42000,54000,48400,55000"
5227st "adc_data : (11:0)"
5228blo "42000,54800"
5229tm "WireNameMgr"
5230)
5231)
5232on &107
5233)
5234*172 (Wire
5235uid 578,0
5236shape (OrthoPolyLine
5237uid 579,0
5238va (VaSet
5239vasetType 3
5240)
5241xt "24000,53000,29250,53000"
5242pts [
5243"29250,53000"
5244"24000,53000"
5245]
5246)
5247start &92
5248sat 32
5249eat 16
5250st 0
5251sf 1
5252tg (WTG
5253uid 582,0
5254ps "ConnStartEndStrategy"
5255stg "STSignalDisplayStrategy"
5256f (Text
5257uid 583,0
5258va (VaSet
5259)
5260xt "25000,52000,29000,53000"
5261st "ADC_CLK"
5262blo "25000,52800"
5263tm "WireNameMgr"
5264)
5265)
5266on &144
5267)
5268*173 (Wire
5269uid 769,0
5270shape (OrthoPolyLine
5271uid 770,0
5272va (VaSet
5273vasetType 3
5274)
5275xt "109750,24000,116000,24000"
5276pts [
5277"109750,24000"
5278"116000,24000"
5279]
5280)
5281start &13
5282sat 32
5283eat 16
5284st 0
5285sf 1
5286si 0
5287tg (WTG
5288uid 773,0
5289ps "ConnStartEndStrategy"
5290stg "STSignalDisplayStrategy"
5291f (Text
5292uid 774,0
5293va (VaSet
5294)
5295xt "111000,23000,114600,24000"
5296st "wiz_reset"
5297blo "111000,23800"
5298tm "WireNameMgr"
5299)
5300)
5301on &108
5302)
5303*174 (Wire
5304uid 777,0
5305shape (OrthoPolyLine
5306uid 778,0
5307va (VaSet
5308vasetType 3
5309lineWidth 2
5310)
5311xt "109750,70000,116000,70000"
5312pts [
5313"109750,70000"
5314"116000,70000"
5315]
5316)
5317start &14
5318sat 32
5319eat 16
5320sty 1
5321st 0
5322sf 1
5323si 0
5324tg (WTG
5325uid 781,0
5326ps "ConnStartEndStrategy"
5327stg "STSignalDisplayStrategy"
5328f (Text
5329uid 782,0
5330va (VaSet
5331)
5332xt "111000,69000,115000,70000"
5333st "led : (7:0)"
5334blo "111000,69800"
5335tm "WireNameMgr"
5336)
5337)
5338on &109
5339)
5340*175 (Wire
5341uid 785,0
5342shape (OrthoPolyLine
5343uid 786,0
5344va (VaSet
5345vasetType 3
5346)
5347xt "109750,28000,116000,28000"
5348pts [
5349"109750,28000"
5350"116000,28000"
5351]
5352)
5353start &21
5354sat 32
5355eat 16
5356st 0
5357sf 1
5358si 0
5359tg (WTG
5360uid 789,0
5361ps "ConnStartEndStrategy"
5362stg "STSignalDisplayStrategy"
5363f (Text
5364uid 790,0
5365va (VaSet
5366)
5367xt "111000,27000,113700,28000"
5368st "wiz_cs"
5369blo "111000,27800"
5370tm "WireNameMgr"
5371)
5372)
5373on &110
5374)
5375*176 (Wire
5376uid 793,0
5377shape (OrthoPolyLine
5378uid 794,0
5379va (VaSet
5380vasetType 3
5381)
5382xt "109750,27000,122250,27000"
5383pts [
5384"122250,27000"
5385"109750,27000"
5386]
5387)
5388start &151
5389end &24
5390sat 32
5391eat 32
5392st 0
5393sf 1
5394si 0
5395tg (WTG
5396uid 797,0
5397ps "ConnStartEndStrategy"
5398stg "STSignalDisplayStrategy"
5399f (Text
5400uid 798,0
5401va (VaSet
5402)
5403xt "111000,26000,113700,27000"
5404st "wiz_int"
5405blo "111000,26800"
5406tm "WireNameMgr"
5407)
5408)
5409on &111
5410)
5411*177 (Wire
5412uid 801,0
5413shape (OrthoPolyLine
5414uid 802,0
5415va (VaSet
5416vasetType 3
5417)
5418xt "109750,40000,116000,40000"
5419pts [
5420"109750,40000"
5421"116000,40000"
5422]
5423)
5424start &40
5425sat 32
5426eat 16
5427st 0
5428sf 1
5429si 0
5430tg (WTG
5431uid 805,0
5432ps "ConnStartEndStrategy"
5433stg "STSignalDisplayStrategy"
5434f (Text
5435uid 806,0
5436va (VaSet
5437)
5438xt "111000,39000,113800,40000"
5439st "dac_cs"
5440blo "111000,39800"
5441tm "WireNameMgr"
5442)
5443)
5444on &112
5445)
5446*178 (Wire
5447uid 809,0
5448shape (OrthoPolyLine
5449uid 810,0
5450va (VaSet
5451vasetType 3
5452)
5453xt "109750,53000,116000,53000"
5454pts [
5455"109750,53000"
5456"116000,53000"
5457]
5458)
5459start &42
5460sat 32
5461eat 16
5462st 0
5463sf 1
5464si 0
5465tg (WTG
5466uid 813,0
5467ps "ConnStartEndStrategy"
5468stg "STSignalDisplayStrategy"
5469f (Text
5470uid 814,0
5471va (VaSet
5472)
5473xt "111000,52000,113000,53000"
5474st "mosi"
5475blo "111000,52800"
5476tm "WireNameMgr"
5477)
5478)
5479on &113
5480)
5481*179 (Wire
5482uid 817,0
5483shape (OrthoPolyLine
5484uid 818,0
5485va (VaSet
5486vasetType 3
5487)
5488xt "70000,66000,80250,66000"
5489pts [
5490"80250,66000"
5491"70000,66000"
5492]
5493)
5494start &43
5495sat 32
5496eat 16
5497st 0
5498sf 1
5499si 0
5500tg (WTG
5501uid 821,0
5502ps "ConnStartEndStrategy"
5503stg "STSignalDisplayStrategy"
5504f (Text
5505uid 822,0
5506va (VaSet
5507)
5508xt "71000,65000,74000,66000"
5509st "denable"
5510blo "71000,65800"
5511tm "WireNameMgr"
5512)
5513)
5514on &114
5515)
5516*180 (Wire
5517uid 825,0
5518shape (OrthoPolyLine
5519uid 826,0
5520va (VaSet
5521vasetType 3
5522)
5523xt "70000,23000,80250,23000"
5524pts [
5525"80250,23000"
5526"70000,23000"
5527]
5528)
5529start &25
5530sat 32
5531eat 16
5532st 0
5533sf 1
5534si 0
5535tg (WTG
5536uid 829,0
5537ps "ConnStartEndStrategy"
5538stg "STSignalDisplayStrategy"
5539f (Text
5540uid 830,0
5541va (VaSet
5542)
5543xt "71000,22000,75500,23000"
5544st "CLK_25_PS"
5545blo "71000,22800"
5546tm "WireNameMgr"
5547)
5548)
5549on &115
5550)
5551*181 (Wire
5552uid 833,0
5553shape (OrthoPolyLine
5554uid 834,0
5555va (VaSet
5556vasetType 3
5557)
5558xt "70000,22000,80250,22000"
5559pts [
5560"80250,22000"
5561"70000,22000"
5562]
5563)
5564start &26
5565sat 32
5566eat 16
5567st 0
5568sf 1
5569si 0
5570tg (WTG
5571uid 837,0
5572ps "ConnStartEndStrategy"
5573stg "STSignalDisplayStrategy"
5574f (Text
5575uid 838,0
5576va (VaSet
5577)
5578xt "71000,21000,74100,22000"
5579st "CLK_50"
5580blo "71000,21800"
5581tm "WireNameMgr"
5582)
5583)
5584on &116
5585)
5586*182 (Wire
5587uid 841,0
5588shape (OrthoPolyLine
5589uid 842,0
5590va (VaSet
5591vasetType 3
5592lineWidth 2
5593)
5594xt "70000,62000,80250,62000"
5595pts [
5596"80250,62000"
5597"70000,62000"
5598]
5599)
5600start &30
5601sat 32
5602eat 16
5603sty 1
5604st 0
5605sf 1
5606si 0
5607tg (WTG
5608uid 845,0
5609ps "ConnStartEndStrategy"
5610stg "STSignalDisplayStrategy"
5611f (Text
5612uid 846,0
5613va (VaSet
5614)
5615xt "71000,61000,79500,62000"
5616st "drs_channel_id : (3:0)"
5617blo "71000,61800"
5618tm "WireNameMgr"
5619)
5620)
5621on &117
5622)
5623*183 (Wire
5624uid 849,0
5625shape (OrthoPolyLine
5626uid 850,0
5627va (VaSet
5628vasetType 3
5629)
5630xt "70000,67000,80250,67000"
5631pts [
5632"80250,67000"
5633"70000,67000"
5634]
5635)
5636start &31
5637ss 0
5638sat 32
5639eat 16
5640st 0
5641sf 1
5642si 0
5643tg (WTG
5644uid 853,0
5645ps "ConnStartEndStrategy"
5646stg "STSignalDisplayStrategy"
5647f (Text
5648uid 854,0
5649va (VaSet
5650)
5651xt "71000,66000,75300,67000"
5652st "drs_dwrite"
5653blo "71000,66800"
5654tm "WireNameMgr"
5655)
5656)
5657on &118
5658)
5659*184 (Wire
5660uid 857,0
5661shape (OrthoPolyLine
5662uid 858,0
5663va (VaSet
5664vasetType 3
5665)
5666xt "70000,64000,80250,64000"
5667pts [
5668"80250,64000"
5669"70000,64000"
5670]
5671)
5672start &36
5673sat 32
5674eat 16
5675st 0
5676sf 1
5677si 0
5678tg (WTG
5679uid 861,0
5680ps "ConnStartEndStrategy"
5681stg "STSignalDisplayStrategy"
5682f (Text
5683uid 862,0
5684va (VaSet
5685)
5686xt "71000,63000,75200,64000"
5687st "RSRLOAD"
5688blo "71000,63800"
5689tm "WireNameMgr"
5690)
5691)
5692on &119
5693)
5694*185 (Wire
5695uid 865,0
5696shape (OrthoPolyLine
5697uid 866,0
5698va (VaSet
5699vasetType 3
5700)
5701xt "70000,65000,80250,65000"
5702pts [
5703"80250,65000"
5704"70000,65000"
5705]
5706)
5707start &37
5708sat 32
5709eat 16
5710st 0
5711sf 1
5712si 0
5713tg (WTG
5714uid 869,0
5715ps "ConnStartEndStrategy"
5716stg "STSignalDisplayStrategy"
5717f (Text
5718uid 870,0
5719va (VaSet
5720)
5721xt "71000,64000,74000,65000"
5722st "SRCLK"
5723blo "71000,64800"
5724tm "WireNameMgr"
5725)
5726)
5727on &120
5728)
5729*186 (Wire
5730uid 873,0
5731shape (OrthoPolyLine
5732uid 874,0
5733va (VaSet
5734vasetType 3
5735)
5736xt "70000,58000,80250,58000"
5737pts [
5738"70000,58000"
5739"80250,58000"
5740]
5741)
5742end &32
5743sat 16
5744eat 32
5745st 0
5746sf 1
5747si 0
5748tg (WTG
5749uid 877,0
5750ps "ConnStartEndStrategy"
5751stg "STSignalDisplayStrategy"
5752f (Text
5753uid 878,0
5754va (VaSet
5755)
5756xt "71000,57000,76400,58000"
5757st "SROUT_in_0"
5758blo "71000,57800"
5759tm "WireNameMgr"
5760)
5761)
5762on &121
5763)
5764*187 (Wire
5765uid 881,0
5766shape (OrthoPolyLine
5767uid 882,0
5768va (VaSet
5769vasetType 3
5770)
5771xt "70000,59000,80250,59000"
5772pts [
5773"70000,59000"
5774"80250,59000"
5775]
5776)
5777end &33
5778sat 16
5779eat 32
5780st 0
5781sf 1
5782si 0
5783tg (WTG
5784uid 885,0
5785ps "ConnStartEndStrategy"
5786stg "STSignalDisplayStrategy"
5787f (Text
5788uid 886,0
5789va (VaSet
5790)
5791xt "71000,58000,76400,59000"
5792st "SROUT_in_1"
5793blo "71000,58800"
5794tm "WireNameMgr"
5795)
5796)
5797on &122
5798)
5799*188 (Wire
5800uid 889,0
5801shape (OrthoPolyLine
5802uid 890,0
5803va (VaSet
5804vasetType 3
5805)
5806xt "70000,60000,80250,60000"
5807pts [
5808"70000,60000"
5809"80250,60000"
5810]
5811)
5812end &34
5813sat 16
5814eat 32
5815st 0
5816sf 1
5817si 0
5818tg (WTG
5819uid 893,0
5820ps "ConnStartEndStrategy"
5821stg "STSignalDisplayStrategy"
5822f (Text
5823uid 894,0
5824va (VaSet
5825)
5826xt "71000,59000,76400,60000"
5827st "SROUT_in_2"
5828blo "71000,59800"
5829tm "WireNameMgr"
5830)
5831)
5832on &123
5833)
5834*189 (Wire
5835uid 897,0
5836shape (OrthoPolyLine
5837uid 898,0
5838va (VaSet
5839vasetType 3
5840)
5841xt "70000,61000,80250,61000"
5842pts [
5843"70000,61000"
5844"80250,61000"
5845]
5846)
5847end &35
5848sat 16
5849eat 32
5850st 0
5851sf 1
5852si 0
5853tg (WTG
5854uid 901,0
5855ps "ConnStartEndStrategy"
5856stg "STSignalDisplayStrategy"
5857f (Text
5858uid 902,0
5859va (VaSet
5860)
5861xt "71000,60000,76400,61000"
5862st "SROUT_in_3"
5863blo "71000,60800"
5864tm "WireNameMgr"
5865)
5866)
5867on &124
5868)
5869*190 (Wire
5870uid 1437,0
5871shape (OrthoPolyLine
5872uid 1438,0
5873va (VaSet
5874vasetType 3
5875)
5876xt "73000,72000,80250,72000"
5877pts [
5878"80250,72000"
5879"73000,72000"
5880]
5881)
5882start &53
5883sat 32
5884eat 16
5885st 0
5886sf 1
5887si 0
5888tg (WTG
5889uid 1441,0
5890ps "ConnStartEndStrategy"
5891stg "STSignalDisplayStrategy"
5892f (Text
5893uid 1442,0
5894va (VaSet
5895)
5896xt "76000,72000,79700,73000"
5897st "SRIN_out"
5898blo "76000,72800"
5899tm "WireNameMgr"
5900)
5901)
5902on &125
5903)
5904*191 (Wire
5905uid 1445,0
5906shape (OrthoPolyLine
5907uid 1446,0
5908va (VaSet
5909vasetType 3
5910)
5911xt "109750,80000,115000,80000"
5912pts [
5913"109750,80000"
5914"115000,80000"
5915]
5916)
5917start &46
5918sat 32
5919eat 16
5920st 0
5921sf 1
5922si 0
5923tg (WTG
5924uid 1449,0
5925ps "ConnStartEndStrategy"
5926stg "STSignalDisplayStrategy"
5927f (Text
5928uid 1450,0
5929va (VaSet
5930)
5931xt "111000,79000,113500,80000"
5932st "amber"
5933blo "111000,79800"
5934tm "WireNameMgr"
5935)
5936)
5937on &126
5938)
5939*192 (Wire
5940uid 1453,0
5941shape (OrthoPolyLine
5942uid 1454,0
5943va (VaSet
5944vasetType 3
5945)
5946xt "109750,79000,114000,79000"
5947pts [
5948"109750,79000"
5949"114000,79000"
5950]
5951)
5952start &52
5953sat 32
5954eat 16
5955st 0
5956sf 1
5957si 0
5958tg (WTG
5959uid 1457,0
5960ps "ConnStartEndStrategy"
5961stg "STSignalDisplayStrategy"
5962f (Text
5963uid 1458,0
5964va (VaSet
5965)
5966xt "111000,78000,112500,79000"
5967st "red"
5968blo "111000,78800"
5969tm "WireNameMgr"
5970)
5971)
5972on &127
5973)
5974*193 (Wire
5975uid 1461,0
5976shape (OrthoPolyLine
5977uid 1462,0
5978va (VaSet
5979vasetType 3
5980)
5981xt "109750,78000,114000,78000"
5982pts [
5983"109750,78000"
5984"114000,78000"
5985]
5986)
5987start &50
5988sat 32
5989eat 16
5990st 0
5991sf 1
5992si 0
5993tg (WTG
5994uid 1465,0
5995ps "ConnStartEndStrategy"
5996stg "STSignalDisplayStrategy"
5997f (Text
5998uid 1466,0
5999va (VaSet
6000)
6001xt "111000,77000,113400,78000"
6002st "green"
6003blo "111000,77800"
6004tm "WireNameMgr"
6005)
6006)
6007on &128
6008)
6009*194 (Wire
6010uid 1469,0
6011shape (OrthoPolyLine
6012uid 1470,0
6013va (VaSet
6014vasetType 3
6015lineWidth 2
6016)
6017xt "109750,77000,121000,77000"
6018pts [
6019"109750,77000"
6020"121000,77000"
6021]
6022)
6023start &47
6024sat 32
6025eat 16
6026sty 1
6027st 0
6028sf 1
6029si 0
6030tg (WTG
6031uid 1473,0
6032ps "ConnStartEndStrategy"
6033stg "STSignalDisplayStrategy"
6034f (Text
6035uid 1474,0
6036va (VaSet
6037)
6038xt "111000,76000,119600,77000"
6039st "counter_result : (11:0)"
6040blo "111000,76800"
6041tm "WireNameMgr"
6042)
6043)
6044on &129
6045)
6046*195 (Wire
6047uid 1477,0
6048shape (OrthoPolyLine
6049uid 1478,0
6050va (VaSet
6051vasetType 3
6052)
6053xt "109750,75000,120000,75000"
6054pts [
6055"109750,75000"
6056"120000,75000"
6057]
6058)
6059start &45
6060sat 32
6061eat 16
6062st 0
6063sf 1
6064si 0
6065tg (WTG
6066uid 1481,0
6067ps "ConnStartEndStrategy"
6068stg "STSignalDisplayStrategy"
6069f (Text
6070uid 1482,0
6071va (VaSet
6072)
6073xt "111000,74000,119200,75000"
6074st "alarm_refclk_too_low"
6075blo "111000,74800"
6076tm "WireNameMgr"
6077)
6078)
6079on &130
6080)
6081*196 (Wire
6082uid 1485,0
6083shape (OrthoPolyLine
6084uid 1486,0
6085va (VaSet
6086vasetType 3
6087)
6088xt "109750,74000,121000,74000"
6089pts [
6090"109750,74000"
6091"121000,74000"
6092]
6093)
6094start &44
6095sat 32
6096eat 16
6097st 0
6098sf 1
6099si 0
6100tg (WTG
6101uid 1489,0
6102ps "ConnStartEndStrategy"
6103stg "STSignalDisplayStrategy"
6104f (Text
6105uid 1490,0
6106va (VaSet
6107)
6108xt "111000,73000,119600,74000"
6109st "alarm_refclk_too_high"
6110blo "111000,73800"
6111tm "WireNameMgr"
6112)
6113)
6114on &131
6115)
6116*197 (Wire
6117uid 1503,0
6118shape (OrthoPolyLine
6119uid 1504,0
6120va (VaSet
6121vasetType 3
6122lineWidth 2
6123)
6124xt "73000,75000,80250,75000"
6125pts [
6126"73000,75000"
6127"80250,75000"
6128]
6129)
6130end &48
6131sat 16
6132eat 32
6133sty 1
6134st 0
6135sf 1
6136si 0
6137tg (WTG
6138uid 1507,0
6139ps "ConnStartEndStrategy"
6140stg "STSignalDisplayStrategy"
6141f (Text
6142uid 1508,0
6143va (VaSet
6144)
6145xt "74000,74000,79500,75000"
6146st "D_T_in : (1:0)"
6147blo "74000,74800"
6148tm "WireNameMgr"
6149)
6150)
6151on &136
6152)
6153*198 (Wire
6154uid 1529,0
6155shape (OrthoPolyLine
6156uid 1530,0
6157va (VaSet
6158vasetType 3
6159)
6160xt "66750,76000,80250,79000"
6161pts [
6162"66750,79000"
6163"70000,79000"
6164"70000,76000"
6165"80250,76000"
6166]
6167)
6168start &138
6169end &49
6170sat 32
6171eat 32
6172st 0
6173sf 1
6174si 0
6175tg (WTG
6176uid 1531,0
6177ps "ConnStartEndStrategy"
6178stg "STSignalDisplayStrategy"
6179f (Text
6180uid 1532,0
6181va (VaSet
6182)
6183xt "68750,78000,72650,79000"
6184st "REF_CLK"
6185blo "68750,78800"
6186tm "WireNameMgr"
6187)
6188)
6189on &145
6190)
6191*199 (Wire
6192uid 1533,0
6193shape (OrthoPolyLine
6194uid 1534,0
6195va (VaSet
6196vasetType 3
6197)
6198xt "35000,70000,45000,70000"
6199pts [
6200"35000,70000"
6201"45000,70000"
6202]
6203)
6204start &132
6205sat 2
6206eat 16
6207st 0
6208sf 1
6209si 0
6210tg (WTG
6211uid 1539,0
6212ps "ConnStartEndStrategy"
6213stg "STSignalDisplayStrategy"
6214f (Text
6215uid 1540,0
6216va (VaSet
6217)
6218xt "37000,69000,42500,70000"
6219st "D_T_in : (1:0)"
6220blo "37000,69800"
6221tm "WireNameMgr"
6222)
6223)
6224on &136
6225)
6226*200 (Wire
6227uid 1561,0
6228shape (OrthoPolyLine
6229uid 1562,0
6230va (VaSet
6231vasetType 3
6232lineWidth 2
6233)
6234xt "72000,77000,80250,77000"
6235pts [
6236"72000,77000"
6237"80250,77000"
6238]
6239)
6240end &51
6241sat 16
6242eat 32
6243sty 1
6244st 0
6245sf 1
6246si 0
6247tg (WTG
6248uid 1565,0
6249ps "ConnStartEndStrategy"
6250stg "STSignalDisplayStrategy"
6251f (Text
6252uid 1566,0
6253va (VaSet
6254)
6255xt "73000,76000,79100,77000"
6256st "plllock_in : (3:0)"
6257blo "73000,76800"
6258tm "WireNameMgr"
6259)
6260)
6261on &143
6262)
6263*201 (Wire
6264uid 1567,0
6265shape (OrthoPolyLine
6266uid 1568,0
6267va (VaSet
6268vasetType 3
6269)
6270xt "35000,71000,45000,71000"
6271pts [
6272"35000,71000"
6273"45000,71000"
6274]
6275)
6276start &132
6277sat 2
6278eat 16
6279st 0
6280sf 1
6281si 0
6282tg (WTG
6283uid 1573,0
6284ps "ConnStartEndStrategy"
6285stg "STSignalDisplayStrategy"
6286f (Text
6287uid 1574,0
6288va (VaSet
6289)
6290xt "37000,70000,43100,71000"
6291st "plllock_in : (3:0)"
6292blo "37000,70800"
6293tm "WireNameMgr"
6294)
6295)
6296on &143
6297)
6298*202 (Wire
6299uid 1684,0
6300shape (OrthoPolyLine
6301uid 1685,0
6302va (VaSet
6303vasetType 3
6304)
6305xt "70000,24000,80250,24000"
6306pts [
6307"80250,24000"
6308"70000,24000"
6309]
6310)
6311start &54
6312sat 32
6313eat 16
6314st 0
6315sf 1
6316si 0
6317tg (WTG
6318uid 1688,0
6319ps "ConnStartEndStrategy"
6320stg "STSignalDisplayStrategy"
6321f (Text
6322uid 1689,0
6323va (VaSet
6324)
6325xt "71000,23000,75000,24000"
6326st "ADC_CLK"
6327blo "71000,23800"
6328tm "WireNameMgr"
6329)
6330)
6331on &144
6332)
6333]
6334bg "65535,65535,65535"
6335grid (Grid
6336origin "0,0"
6337isVisible 1
6338isActive 1
6339xSpacing 1000
6340xySpacing 1000
6341xShown 1
6342yShown 1
6343color "26368,26368,26368"
6344)
6345packageList *203 (PackageList
6346uid 41,0
6347stg "VerticalLayoutStrategy"
6348textVec [
6349*204 (Text
6350uid 42,0
6351va (VaSet
6352font "arial,8,1"
6353)
6354xt "-87000,0,-81600,1000"
6355st "Package List"
6356blo "-87000,800"
6357)
6358*205 (MLText
6359uid 43,0
6360va (VaSet
6361)
6362xt "-87000,1000,-72500,11000"
6363st "LIBRARY ieee;
6364USE ieee.std_logic_1164.all;
6365USE ieee.std_logic_arith.all;
6366USE ieee.std_logic_unsigned.all;
6367
6368LIBRARY FACT_FAD_lib;
6369USE FACT_FAD_lib.fad_definitions.all;
6370USE ieee.std_logic_textio.all;
6371LIBRARY std;
6372USE std.textio.all;"
6373tm "PackageList"
6374)
6375]
6376)
6377compDirBlock (MlTextGroup
6378uid 44,0
6379stg "VerticalLayoutStrategy"
6380textVec [
6381*206 (Text
6382uid 45,0
6383va (VaSet
6384isHidden 1
6385font "Arial,8,1"
6386)
6387xt "20000,0,28100,1000"
6388st "Compiler Directives"
6389blo "20000,800"
6390)
6391*207 (Text
6392uid 46,0
6393va (VaSet
6394isHidden 1
6395font "Arial,8,1"
6396)
6397xt "20000,1000,29600,2000"
6398st "Pre-module directives:"
6399blo "20000,1800"
6400)
6401*208 (MLText
6402uid 47,0
6403va (VaSet
6404isHidden 1
6405)
6406xt "20000,2000,27500,4000"
6407st "`resetall
6408`timescale 1ns/10ps"
6409tm "BdCompilerDirectivesTextMgr"
6410)
6411*209 (Text
6412uid 48,0
6413va (VaSet
6414isHidden 1
6415font "Arial,8,1"
6416)
6417xt "20000,4000,30100,5000"
6418st "Post-module directives:"
6419blo "20000,4800"
6420)
6421*210 (MLText
6422uid 49,0
6423va (VaSet
6424isHidden 1
6425)
6426xt "20000,0,20000,0"
6427tm "BdCompilerDirectivesTextMgr"
6428)
6429*211 (Text
6430uid 50,0
6431va (VaSet
6432isHidden 1
6433font "Arial,8,1"
6434)
6435xt "20000,5000,29900,6000"
6436st "End-module directives:"
6437blo "20000,5800"
6438)
6439*212 (MLText
6440uid 51,0
6441va (VaSet
6442isHidden 1
6443)
6444xt "20000,6000,20000,6000"
6445tm "BdCompilerDirectivesTextMgr"
6446)
6447]
6448associable 1
6449)
6450windowSize "0,0,1681,1030"
6451viewArea "59994,4224,152100,60168"
6452cachedDiagramExtent "-92000,0,146000,98000"
6453pageSetupInfo (PageSetupInfo
6454ptrCmd ""
6455toPrinter 1
6456exportedDirectories [
6457"$HDS_PROJECT_DIR/HTMLExport"
6458]
6459exportStdIncludeRefs 1
6460exportStdPackageRefs 1
6461)
6462hasePageBreakOrigin 1
6463pageBreakOrigin "-146000,0"
6464lastUid 2345,0
6465defaultCommentText (CommentText
6466shape (Rectangle
6467layer 0
6468va (VaSet
6469vasetType 1
6470fg "65280,65280,46080"
6471lineColor "0,0,32768"
6472)
6473xt "0,0,15000,5000"
6474)
6475text (MLText
6476va (VaSet
6477fg "0,0,32768"
6478)
6479xt "200,200,2000,1200"
6480st "
6481Text
6482"
6483tm "CommentText"
6484wrapOption 3
6485visibleHeight 4600
6486visibleWidth 14600
6487)
6488)
6489defaultPanel (Panel
6490shape (RectFrame
6491va (VaSet
6492vasetType 1
6493fg "65535,65535,65535"
6494lineColor "32768,0,0"
6495lineWidth 2
6496)
6497xt "0,0,20000,20000"
6498)
6499title (TextAssociate
6500ps "TopLeftStrategy"
6501text (Text
6502va (VaSet
6503font "Arial,8,1"
6504)
6505xt "1000,1000,3800,2000"
6506st "Panel0"
6507blo "1000,1800"
6508tm "PanelText"
6509)
6510)
6511)
6512defaultBlk (Blk
6513shape (Rectangle
6514va (VaSet
6515vasetType 1
6516fg "39936,56832,65280"
6517lineColor "0,0,32768"
6518lineWidth 2
6519)
6520xt "0,0,8000,10000"
6521)
6522ttg (MlTextGroup
6523ps "CenterOffsetStrategy"
6524stg "VerticalLayoutStrategy"
6525textVec [
6526*213 (Text
6527va (VaSet
6528font "Arial,8,1"
6529)
6530xt "2200,3500,5800,4500"
6531st "<library>"
6532blo "2200,4300"
6533tm "BdLibraryNameMgr"
6534)
6535*214 (Text
6536va (VaSet
6537font "Arial,8,1"
6538)
6539xt "2200,4500,5600,5500"
6540st "<block>"
6541blo "2200,5300"
6542tm "BlkNameMgr"
6543)
6544*215 (Text
6545va (VaSet
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7489*239 (RowExpandColHdr
7490tm "RowExpandColHdrMgr"
7491)
7492*240 (GroupColHdr
7493tm "GroupColHdrMgr"
7494)
7495*241 (NameColHdr
7496tm "BlockDiagramNameColHdrMgr"
7497)
7498*242 (ModeColHdr
7499tm "BlockDiagramModeColHdrMgr"
7500)
7501*243 (TypeColHdr
7502tm "BlockDiagramTypeColHdrMgr"
7503)
7504*244 (BoundsColHdr
7505tm "BlockDiagramBoundsColHdrMgr"
7506)
7507*245 (InitColHdr
7508tm "BlockDiagramInitColHdrMgr"
7509)
7510*246 (EolColHdr
7511tm "BlockDiagramEolColHdrMgr"
7512)
7513*247 (LeafLogPort
7514port (LogicalPort
7515m 4
7516decl (Decl
7517n "clk"
7518t "STD_LOGIC"
7519preAdd 0
7520posAdd 0
7521o 1
7522suid 1,0
7523)
7524)
7525uid 340,0
7526)
7527*248 (LeafLogPort
7528port (LogicalPort
7529m 4
7530decl (Decl
7531n "wiz_addr"
7532t "std_logic_vector"
7533b "(9 DOWNTO 0)"
7534o 2
7535suid 2,0
7536)
7537)
7538uid 342,0
7539)
7540*249 (LeafLogPort
7541port (LogicalPort
7542m 4
7543decl (Decl
7544n "wiz_data"
7545t "std_logic_vector"
7546b "(15 DOWNTO 0)"
7547o 3
7548suid 3,0
7549)
7550)
7551uid 344,0
7552)
7553*250 (LeafLogPort
7554port (LogicalPort
7555m 4
7556decl (Decl
7557n "wiz_rd"
7558t "std_logic"
7559o 4
7560suid 4,0
7561i "'1'"
7562)
7563)
7564uid 346,0
7565)
7566*251 (LeafLogPort
7567port (LogicalPort
7568m 4
7569decl (Decl
7570n "wiz_wr"
7571t "std_logic"
7572o 5
7573suid 5,0
7574i "'1'"
7575)
7576)
7577uid 348,0
7578)
7579*252 (LeafLogPort
7580port (LogicalPort
7581m 4
7582decl (Decl
7583n "sensor_cs"
7584t "std_logic_vector"
7585b "(3 DOWNTO 0)"
7586o 6
7587suid 6,0
7588)
7589)
7590uid 404,0
7591)
7592*253 (LeafLogPort
7593port (LogicalPort
7594m 4
7595decl (Decl
7596n "sclk"
7597t "std_logic"
7598o 7
7599suid 7,0
7600)
7601)
7602uid 406,0
7603)
7604*254 (LeafLogPort
7605port (LogicalPort
7606m 4
7607decl (Decl
7608n "sio"
7609t "std_logic"
7610preAdd 0
7611posAdd 0
7612o 8
7613suid 8,0
7614)
7615)
7616uid 408,0
7617)
7618*255 (LeafLogPort
7619port (LogicalPort
7620m 4
7621decl (Decl
7622n "trigger"
7623t "std_logic"
7624preAdd 0
7625posAdd 0
7626o 9
7627suid 9,0
7628)
7629)
7630uid 456,0
7631)
7632*256 (LeafLogPort
7633port (LogicalPort
7634m 4
7635decl (Decl
7636n "board_id"
7637t "std_logic_vector"
7638b "(3 downto 0)"
7639preAdd 0
7640posAdd 0
7641o 10
7642suid 10,0
7643)
7644)
7645uid 458,0
7646)
7647*257 (LeafLogPort
7648port (LogicalPort
7649m 4
7650decl (Decl
7651n "crate_id"
7652t "std_logic_vector"
7653b "(1 downto 0)"
7654o 11
7655suid 11,0
7656)
7657)
7658uid 460,0
7659)
7660*258 (LeafLogPort
7661port (LogicalPort
7662m 4
7663decl (Decl
7664n "adc_otr_array"
7665t "std_logic_vector"
7666b "(3 DOWNTO 0)"
7667o 12
7668suid 12,0
7669)
7670)
7671uid 584,0
7672)
7673*259 (LeafLogPort
7674port (LogicalPort
7675m 4
7676decl (Decl
7677n "adc_data_array"
7678t "adc_data_array_type"
7679o 13
7680suid 13,0
7681)
7682)
7683uid 586,0
7684)
7685*260 (LeafLogPort
7686port (LogicalPort
7687m 4
7688decl (Decl
7689n "adc_oeb"
7690t "std_logic"
7691preAdd 0
7692posAdd 0
7693o 14
7694suid 14,0
7695)
7696)
7697uid 588,0
7698)
7699*261 (LeafLogPort
7700port (LogicalPort
7701m 4
7702decl (Decl
7703n "adc_otr"
7704t "STD_LOGIC"
7705preAdd 0
7706posAdd 0
7707o 16
7708suid 16,0
7709)
7710)
7711uid 590,0
7712)
7713*262 (LeafLogPort
7714port (LogicalPort
7715m 4
7716decl (Decl
7717n "adc_data"
7718t "std_logic_vector"
7719b "(11 DOWNTO 0)"
7720preAdd 0
7721posAdd 0
7722o 17
7723suid 17,0
7724)
7725)
7726uid 592,0
7727)
7728*263 (LeafLogPort
7729port (LogicalPort
7730m 4
7731decl (Decl
7732n "wiz_reset"
7733t "std_logic"
7734o 21
7735suid 23,0
7736i "'1'"
7737)
7738)
7739uid 903,0
7740)
7741*264 (LeafLogPort
7742port (LogicalPort
7743m 4
7744decl (Decl
7745n "led"
7746t "std_logic_vector"
7747b "(7 DOWNTO 0)"
7748posAdd 0
7749o 22
7750suid 24,0
7751i "(OTHERS => '0')"
7752)
7753)
7754uid 905,0
7755)
7756*265 (LeafLogPort
7757port (LogicalPort
7758m 4
7759decl (Decl
7760n "wiz_cs"
7761t "std_logic"
7762o 23
7763suid 25,0
7764i "'1'"
7765)
7766)
7767uid 907,0
7768)
7769*266 (LeafLogPort
7770port (LogicalPort
7771m 4
7772decl (Decl
7773n "wiz_int"
7774t "std_logic"
7775o 24
7776suid 26,0
7777)
7778)
7779uid 909,0
7780)
7781*267 (LeafLogPort
7782port (LogicalPort
7783m 4
7784decl (Decl
7785n "dac_cs"
7786t "std_logic"
7787o 25
7788suid 27,0
7789)
7790)
7791uid 911,0
7792)
7793*268 (LeafLogPort
7794port (LogicalPort
7795m 4
7796decl (Decl
7797n "mosi"
7798t "std_logic"
7799o 26
7800suid 28,0
7801i "'0'"
7802)
7803)
7804uid 913,0
7805)
7806*269 (LeafLogPort
7807port (LogicalPort
7808m 4
7809decl (Decl
7810n "denable"
7811t "std_logic"
7812eolc "-- default domino wave off"
7813posAdd 0
7814o 27
7815suid 29,0
7816i "'0'"
7817)
7818)
7819uid 915,0
7820)
7821*270 (LeafLogPort
7822port (LogicalPort
7823m 4
7824decl (Decl
7825n "CLK_25_PS"
7826t "std_logic"
7827o 28
7828suid 30,0
7829)
7830)
7831uid 917,0
7832)
7833*271 (LeafLogPort
7834port (LogicalPort
7835m 4
7836decl (Decl
7837n "CLK_50"
7838t "std_logic"
7839o 29
7840suid 31,0
7841)
7842)
7843uid 919,0
7844)
7845*272 (LeafLogPort
7846port (LogicalPort
7847m 4
7848decl (Decl
7849n "drs_channel_id"
7850t "std_logic_vector"
7851b "(3 downto 0)"
7852o 30
7853suid 32,0
7854i "(others => '0')"
7855)
7856)
7857uid 921,0
7858)
7859*273 (LeafLogPort
7860port (LogicalPort
7861m 4
7862decl (Decl
7863n "drs_dwrite"
7864t "std_logic"
7865o 31
7866suid 33,0
7867i "'1'"
7868)
7869)
7870uid 923,0
7871)
7872*274 (LeafLogPort
7873port (LogicalPort
7874m 4
7875decl (Decl
7876n "RSRLOAD"
7877t "std_logic"
7878o 32
7879suid 34,0
7880i "'0'"
7881)
7882)
7883uid 925,0
7884)
7885*275 (LeafLogPort
7886port (LogicalPort
7887m 4
7888decl (Decl
7889n "SRCLK"
7890t "std_logic"
7891o 33
7892suid 35,0
7893i "'0'"
7894)
7895)
7896uid 927,0
7897)
7898*276 (LeafLogPort
7899port (LogicalPort
7900m 4
7901decl (Decl
7902n "SROUT_in_0"
7903t "std_logic"
7904o 30
7905suid 36,0
7906)
7907)
7908uid 929,0
7909)
7910*277 (LeafLogPort
7911port (LogicalPort
7912m 4
7913decl (Decl
7914n "SROUT_in_1"
7915t "std_logic"
7916o 31
7917suid 37,0
7918)
7919)
7920uid 931,0
7921)
7922*278 (LeafLogPort
7923port (LogicalPort
7924m 4
7925decl (Decl
7926n "SROUT_in_2"
7927t "std_logic"
7928o 32
7929suid 38,0
7930)
7931)
7932uid 933,0
7933)
7934*279 (LeafLogPort
7935port (LogicalPort
7936m 4
7937decl (Decl
7938n "SROUT_in_3"
7939t "std_logic"
7940o 33
7941suid 39,0
7942)
7943)
7944uid 935,0
7945)
7946*280 (LeafLogPort
7947port (LogicalPort
7948m 4
7949decl (Decl
7950n "SRIN_out"
7951t "std_logic"
7952o 34
7953suid 40,0
7954i "'0'"
7955)
7956)
7957uid 1541,0
7958)
7959*281 (LeafLogPort
7960port (LogicalPort
7961m 4
7962decl (Decl
7963n "amber"
7964t "std_logic"
7965o 35
7966suid 41,0
7967)
7968)
7969uid 1543,0
7970)
7971*282 (LeafLogPort
7972port (LogicalPort
7973m 4
7974decl (Decl
7975n "red"
7976t "std_logic"
7977o 36
7978suid 42,0
7979)
7980)
7981uid 1545,0
7982)
7983*283 (LeafLogPort
7984port (LogicalPort
7985m 4
7986decl (Decl
7987n "green"
7988t "std_logic"
7989o 37
7990suid 43,0
7991)
7992)
7993uid 1547,0
7994)
7995*284 (LeafLogPort
7996port (LogicalPort
7997m 4
7998decl (Decl
7999n "counter_result"
8000t "std_logic_vector"
8001b "(11 DOWNTO 0)"
8002o 38
8003suid 44,0
8004)
8005)
8006uid 1549,0
8007)
8008*285 (LeafLogPort
8009port (LogicalPort
8010m 4
8011decl (Decl
8012n "alarm_refclk_too_low"
8013t "std_logic"
8014posAdd 0
8015o 39
8016suid 45,0
8017)
8018)
8019uid 1551,0
8020)
8021*286 (LeafLogPort
8022port (LogicalPort
8023m 4
8024decl (Decl
8025n "alarm_refclk_too_high"
8026t "std_logic"
8027o 40
8028suid 46,0
8029)
8030)
8031uid 1553,0
8032)
8033*287 (LeafLogPort
8034port (LogicalPort
8035m 4
8036decl (Decl
8037n "D_T_in"
8038t "std_logic_vector"
8039b "(1 DOWNTO 0)"
8040o 41
8041suid 47,0
8042)
8043)
8044uid 1555,0
8045)
8046*288 (LeafLogPort
8047port (LogicalPort
8048m 4
8049decl (Decl
8050n "plllock_in"
8051t "std_logic_vector"
8052b "(3 DOWNTO 0)"
8053eolc "-- high level, if dominowave is running and DRS PLL locked"
8054o 43
8055suid 49,0
8056)
8057)
8058uid 1575,0
8059)
8060*289 (LeafLogPort
8061port (LogicalPort
8062lang 2
8063m 4
8064decl (Decl
8065n "ADC_CLK"
8066t "std_logic"
8067o 44
8068suid 50,0
8069)
8070)
8071uid 1690,0
8072)
8073*290 (LeafLogPort
8074port (LogicalPort
8075m 4
8076decl (Decl
8077n "REF_CLK"
8078t "STD_LOGIC"
8079o 42
8080suid 51,0
8081i "'0'"
8082)
8083)
8084uid 2003,0
8085)
8086]
8087)
8088pdm (PhysicalDM
8089displayShortBounds 1
8090editShortBounds 1
8091uid 67,0
8092optionalChildren [
8093*291 (Sheet
8094sheetRow (SheetRow
8095headerVa (MVa
8096cellColor "49152,49152,49152"
8097fontColor "0,0,0"
8098font "Tahoma,10,0"
8099)
8100cellVa (MVa
8101cellColor "65535,65535,65535"
8102fontColor "0,0,0"
8103font "Tahoma,10,0"
8104)
8105groupVa (MVa
8106cellColor "39936,56832,65280"
8107fontColor "0,0,0"
8108font "Tahoma,10,0"
8109)
8110emptyMRCItem *292 (MRCItem
8111litem &234
8112pos 44
8113dimension 20
8114)
8115uid 69,0
8116optionalChildren [
8117*293 (MRCItem
8118litem &235
8119pos 0
8120dimension 20
8121uid 70,0
8122)
8123*294 (MRCItem
8124litem &236
8125pos 1
8126dimension 23
8127uid 71,0
8128)
8129*295 (MRCItem
8130litem &237
8131pos 2
8132hidden 1
8133dimension 20
8134uid 72,0
8135)
8136*296 (MRCItem
8137litem &247
8138pos 0
8139dimension 20
8140uid 341,0
8141)
8142*297 (MRCItem
8143litem &248
8144pos 1
8145dimension 20
8146uid 343,0
8147)
8148*298 (MRCItem
8149litem &249
8150pos 2
8151dimension 20
8152uid 345,0
8153)
8154*299 (MRCItem
8155litem &250
8156pos 3
8157dimension 20
8158uid 347,0
8159)
8160*300 (MRCItem
8161litem &251
8162pos 4
8163dimension 20
8164uid 349,0
8165)
8166*301 (MRCItem
8167litem &252
8168pos 5
8169dimension 20
8170uid 405,0
8171)
8172*302 (MRCItem
8173litem &253
8174pos 6
8175dimension 20
8176uid 407,0
8177)
8178*303 (MRCItem
8179litem &254
8180pos 7
8181dimension 20
8182uid 409,0
8183)
8184*304 (MRCItem
8185litem &255
8186pos 8
8187dimension 20
8188uid 457,0
8189)
8190*305 (MRCItem
8191litem &256
8192pos 9
8193dimension 20
8194uid 459,0
8195)
8196*306 (MRCItem
8197litem &257
8198pos 10
8199dimension 20
8200uid 461,0
8201)
8202*307 (MRCItem
8203litem &258
8204pos 11
8205dimension 20
8206uid 585,0
8207)
8208*308 (MRCItem
8209litem &259
8210pos 12
8211dimension 20
8212uid 587,0
8213)
8214*309 (MRCItem
8215litem &260
8216pos 13
8217dimension 20
8218uid 589,0
8219)
8220*310 (MRCItem
8221litem &261
8222pos 14
8223dimension 20
8224uid 591,0
8225)
8226*311 (MRCItem
8227litem &262
8228pos 15
8229dimension 20
8230uid 593,0
8231)
8232*312 (MRCItem
8233litem &263
8234pos 16
8235dimension 20
8236uid 904,0
8237)
8238*313 (MRCItem
8239litem &264
8240pos 17
8241dimension 20
8242uid 906,0
8243)
8244*314 (MRCItem
8245litem &265
8246pos 18
8247dimension 20
8248uid 908,0
8249)
8250*315 (MRCItem
8251litem &266
8252pos 19
8253dimension 20
8254uid 910,0
8255)
8256*316 (MRCItem
8257litem &267
8258pos 20
8259dimension 20
8260uid 912,0
8261)
8262*317 (MRCItem
8263litem &268
8264pos 21
8265dimension 20
8266uid 914,0
8267)
8268*318 (MRCItem
8269litem &269
8270pos 22
8271dimension 20
8272uid 916,0
8273)
8274*319 (MRCItem
8275litem &270
8276pos 23
8277dimension 20
8278uid 918,0
8279)
8280*320 (MRCItem
8281litem &271
8282pos 24
8283dimension 20
8284uid 920,0
8285)
8286*321 (MRCItem
8287litem &272
8288pos 25
8289dimension 20
8290uid 922,0
8291)
8292*322 (MRCItem
8293litem &273
8294pos 26
8295dimension 20
8296uid 924,0
8297)
8298*323 (MRCItem
8299litem &274
8300pos 27
8301dimension 20
8302uid 926,0
8303)
8304*324 (MRCItem
8305litem &275
8306pos 28
8307dimension 20
8308uid 928,0
8309)
8310*325 (MRCItem
8311litem &276
8312pos 29
8313dimension 20
8314uid 930,0
8315)
8316*326 (MRCItem
8317litem &277
8318pos 30
8319dimension 20
8320uid 932,0
8321)
8322*327 (MRCItem
8323litem &278
8324pos 31
8325dimension 20
8326uid 934,0
8327)
8328*328 (MRCItem
8329litem &279
8330pos 32
8331dimension 20
8332uid 936,0
8333)
8334*329 (MRCItem
8335litem &280
8336pos 33
8337dimension 20
8338uid 1542,0
8339)
8340*330 (MRCItem
8341litem &281
8342pos 34
8343dimension 20
8344uid 1544,0
8345)
8346*331 (MRCItem
8347litem &282
8348pos 35
8349dimension 20
8350uid 1546,0
8351)
8352*332 (MRCItem
8353litem &283
8354pos 36
8355dimension 20
8356uid 1548,0
8357)
8358*333 (MRCItem
8359litem &284
8360pos 37
8361dimension 20
8362uid 1550,0
8363)
8364*334 (MRCItem
8365litem &285
8366pos 38
8367dimension 20
8368uid 1552,0
8369)
8370*335 (MRCItem
8371litem &286
8372pos 39
8373dimension 20
8374uid 1554,0
8375)
8376*336 (MRCItem
8377litem &287
8378pos 40
8379dimension 20
8380uid 1556,0
8381)
8382*337 (MRCItem
8383litem &288
8384pos 41
8385dimension 20
8386uid 1576,0
8387)
8388*338 (MRCItem
8389litem &289
8390pos 42
8391dimension 20
8392uid 1691,0
8393)
8394*339 (MRCItem
8395litem &290
8396pos 43
8397dimension 20
8398uid 2004,0
8399)
8400]
8401)
8402sheetCol (SheetCol
8403propVa (MVa
8404cellColor "0,49152,49152"
8405fontColor "0,0,0"
8406font "Tahoma,10,0"
8407textAngle 90
8408)
8409uid 73,0
8410optionalChildren [
8411*340 (MRCItem
8412litem &238
8413pos 0
8414dimension 20
8415uid 74,0
8416)
8417*341 (MRCItem
8418litem &240
8419pos 1
8420dimension 50
8421uid 75,0
8422)
8423*342 (MRCItem
8424litem &241
8425pos 2
8426dimension 100
8427uid 76,0
8428)
8429*343 (MRCItem
8430litem &242
8431pos 3
8432dimension 50
8433uid 77,0
8434)
8435*344 (MRCItem
8436litem &243
8437pos 4
8438dimension 100
8439uid 78,0
8440)
8441*345 (MRCItem
8442litem &244
8443pos 5
8444dimension 100
8445uid 79,0
8446)
8447*346 (MRCItem
8448litem &245
8449pos 6
8450dimension 50
8451uid 80,0
8452)
8453*347 (MRCItem
8454litem &246
8455pos 7
8456dimension 80
8457uid 81,0
8458)
8459]
8460)
8461fixedCol 4
8462fixedRow 2
8463name "Ports"
8464uid 68,0
8465vaOverrides [
8466]
8467)
8468]
8469)
8470uid 53,0
8471)
8472genericsCommonDM (CommonDM
8473ldm (LogicalDM
8474emptyRow *348 (LEmptyRow
8475)
8476uid 83,0
8477optionalChildren [
8478*349 (RefLabelRowHdr
8479)
8480*350 (TitleRowHdr
8481)
8482*351 (FilterRowHdr
8483)
8484*352 (RefLabelColHdr
8485tm "RefLabelColHdrMgr"
8486)
8487*353 (RowExpandColHdr
8488tm "RowExpandColHdrMgr"
8489)
8490*354 (GroupColHdr
8491tm "GroupColHdrMgr"
8492)
8493*355 (NameColHdr
8494tm "GenericNameColHdrMgr"
8495)
8496*356 (TypeColHdr
8497tm "GenericTypeColHdrMgr"
8498)
8499*357 (InitColHdr
8500tm "GenericValueColHdrMgr"
8501)
8502*358 (PragmaColHdr
8503tm "GenericPragmaColHdrMgr"
8504)
8505*359 (EolColHdr
8506tm "GenericEolColHdrMgr"
8507)
8508]
8509)
8510pdm (PhysicalDM
8511displayShortBounds 1
8512editShortBounds 1
8513uid 95,0
8514optionalChildren [
8515*360 (Sheet
8516sheetRow (SheetRow
8517headerVa (MVa
8518cellColor "49152,49152,49152"
8519fontColor "0,0,0"
8520font "Tahoma,10,0"
8521)
8522cellVa (MVa
8523cellColor "65535,65535,65535"
8524fontColor "0,0,0"
8525font "Tahoma,10,0"
8526)
8527groupVa (MVa
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8529fontColor "0,0,0"
8530font "Tahoma,10,0"
8531)
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8534pos 0
8535dimension 20
8536)
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8540litem &349
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8543uid 98,0
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8545*363 (MRCItem
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8547pos 1
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8549uid 99,0
8550)
8551*364 (MRCItem
8552litem &351
8553pos 2
8554hidden 1
8555dimension 20
8556uid 100,0
8557)
8558]
8559)
8560sheetCol (SheetCol
8561propVa (MVa
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8565textAngle 90
8566)
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8574)
8575*366 (MRCItem
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8579uid 103,0
8580)
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8597uid 106,0
8598)
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8600litem &358
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8604)
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8607pos 6
8608dimension 80
8609uid 108,0
8610)
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8612)
8613fixedCol 3
8614fixedRow 2
8615name "Ports"
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8620]
8621)
8622uid 82,0
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8625activeModelName "BlockDiag"
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