source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak @ 10883

Last change on this file since 10883 was 10883, checked in by neise, 9 years ago
one week of changes in zurich :-(
File size: 124.8 KB
Line 
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991xt "100800,21500,108000,22500"
992st "wiz_data : (15:0)"
993ju 2
994blo "108000,22300"
995)
996)
997thePort (LogicalPort
998m 2
999decl (Decl
1000n "wiz_data"
1001t "std_logic_vector"
1002b "(15 DOWNTO 0)"
1003o 52
1004suid 27,0
1005)
1006)
1007)
1008*21 (CptPort
1009uid 141,0
1010ps "OnEdgeStrategy"
1011shape (Triangle
1012uid 142,0
1013ro 90
1014va (VaSet
1015vasetType 1
1016fg "0,65535,0"
1017)
1018xt "109000,27625,109750,28375"
1019)
1020tg (CPTG
1021uid 143,0
1022ps "CptPortTextPlaceStrategy"
1023stg "RightVerticalLayoutStrategy"
1024f (Text
1025uid 144,0
1026va (VaSet
1027)
1028xt "105000,27500,108000,28500"
1029st "wiz_cs"
1030ju 2
1031blo "108000,28300"
1032)
1033)
1034thePort (LogicalPort
1035m 1
1036decl (Decl
1037n "wiz_cs"
1038t "std_logic"
1039o 47
1040suid 28,0
1041i "'1'"
1042)
1043)
1044)
1045*22 (CptPort
1046uid 145,0
1047ps "OnEdgeStrategy"
1048shape (Triangle
1049uid 146,0
1050ro 90
1051va (VaSet
1052vasetType 1
1053fg "0,65535,0"
1054)
1055xt "109000,25625,109750,26375"
1056)
1057tg (CPTG
1058uid 147,0
1059ps "CptPortTextPlaceStrategy"
1060stg "RightVerticalLayoutStrategy"
1061f (Text
1062uid 148,0
1063va (VaSet
1064)
1065xt "104800,25500,108000,26500"
1066st "wiz_wr"
1067ju 2
1068blo "108000,26300"
1069)
1070)
1071thePort (LogicalPort
1072m 1
1073decl (Decl
1074n "wiz_wr"
1075t "std_logic"
1076o 50
1077suid 29,0
1078i "'1'"
1079)
1080)
1081)
1082*23 (CptPort
1083uid 149,0
1084ps "OnEdgeStrategy"
1085shape (Triangle
1086uid 150,0
1087ro 90
1088va (VaSet
1089vasetType 1
1090fg "0,65535,0"
1091)
1092xt "109000,24625,109750,25375"
1093)
1094tg (CPTG
1095uid 151,0
1096ps "CptPortTextPlaceStrategy"
1097stg "RightVerticalLayoutStrategy"
1098f (Text
1099uid 152,0
1100va (VaSet
1101)
1102xt "104900,24500,108000,25500"
1103st "wiz_rd"
1104ju 2
1105blo "108000,25300"
1106)
1107)
1108thePort (LogicalPort
1109m 1
1110decl (Decl
1111n "wiz_rd"
1112t "std_logic"
1113o 48
1114suid 30,0
1115i "'1'"
1116)
1117)
1118)
1119*24 (CptPort
1120uid 153,0
1121ps "OnEdgeStrategy"
1122shape (Triangle
1123uid 154,0
1124ro 270
1125va (VaSet
1126vasetType 1
1127fg "0,65535,0"
1128)
1129xt "109000,26625,109750,27375"
1130)
1131tg (CPTG
1132uid 155,0
1133ps "CptPortTextPlaceStrategy"
1134stg "RightVerticalLayoutStrategy"
1135f (Text
1136uid 156,0
1137va (VaSet
1138)
1139xt "104800,26500,108000,27500"
1140st "wiz_int"
1141ju 2
1142blo "108000,27300"
1143)
1144)
1145thePort (LogicalPort
1146decl (Decl
1147n "wiz_int"
1148t "std_logic"
1149o 15
1150suid 31,0
1151)
1152)
1153)
1154*25 (CptPort
1155uid 157,0
1156ps "OnEdgeStrategy"
1157shape (Triangle
1158uid 158,0
1159ro 270
1160va (VaSet
1161vasetType 1
1162fg "0,65535,0"
1163)
1164xt "80250,22625,81000,23375"
1165)
1166tg (CPTG
1167uid 159,0
1168ps "CptPortTextPlaceStrategy"
1169stg "VerticalLayoutStrategy"
1170f (Text
1171uid 160,0
1172va (VaSet
1173)
1174xt "82000,22500,86800,23500"
1175st "CLK_25_PS"
1176blo "82000,23300"
1177)
1178)
1179thePort (LogicalPort
1180m 1
1181decl (Decl
1182n "CLK_25_PS"
1183t "std_logic"
1184o 17
1185suid 35,0
1186)
1187)
1188)
1189*26 (CptPort
1190uid 161,0
1191ps "OnEdgeStrategy"
1192shape (Triangle
1193uid 162,0
1194ro 270
1195va (VaSet
1196vasetType 1
1197fg "0,65535,0"
1198)
1199xt "80250,21625,81000,22375"
1200)
1201tg (CPTG
1202uid 163,0
1203ps "CptPortTextPlaceStrategy"
1204stg "VerticalLayoutStrategy"
1205f (Text
1206uid 164,0
1207va (VaSet
1208)
1209xt "82000,21500,85300,22500"
1210st "CLK_50"
1211blo "82000,22300"
1212)
1213)
1214thePort (LogicalPort
1215m 1
1216decl (Decl
1217n "CLK_50"
1218t "std_logic"
1219preAdd 0
1220posAdd 0
1221o 18
1222suid 37,0
1223)
1224)
1225)
1226*27 (CptPort
1227uid 165,0
1228ps "OnEdgeStrategy"
1229shape (Triangle
1230uid 166,0
1231ro 90
1232va (VaSet
1233vasetType 1
1234fg "0,65535,0"
1235)
1236xt "80250,20625,81000,21375"
1237)
1238tg (CPTG
1239uid 167,0
1240ps "CptPortTextPlaceStrategy"
1241stg "VerticalLayoutStrategy"
1242f (Text
1243uid 168,0
1244va (VaSet
1245)
1246xt "82000,20500,83900,21500"
1247st "CLK"
1248blo "82000,21300"
1249)
1250)
1251thePort (LogicalPort
1252decl (Decl
1253n "CLK"
1254t "std_logic"
1255o 1
1256suid 38,0
1257)
1258)
1259)
1260*28 (CptPort
1261uid 169,0
1262ps "OnEdgeStrategy"
1263shape (Triangle
1264uid 170,0
1265ro 90
1266va (VaSet
1267vasetType 1
1268fg "0,65535,0"
1269)
1270xt "80250,41625,81000,42375"
1271)
1272tg (CPTG
1273uid 171,0
1274ps "CptPortTextPlaceStrategy"
1275stg "VerticalLayoutStrategy"
1276f (Text
1277uid 172,0
1278va (VaSet
1279)
1280xt "82000,41500,91300,42500"
1281st "adc_otr_array : (3:0)"
1282blo "82000,42300"
1283)
1284)
1285thePort (LogicalPort
1286decl (Decl
1287n "adc_otr_array"
1288t "std_logic_vector"
1289b "(3 DOWNTO 0)"
1290o 9
1291suid 40,0
1292)
1293)
1294)
1295*29 (CptPort
1296uid 173,0
1297ps "OnEdgeStrategy"
1298shape (Triangle
1299uid 174,0
1300ro 90
1301va (VaSet
1302vasetType 1
1303fg "0,65535,0"
1304)
1305xt "80250,47625,81000,48375"
1306)
1307tg (CPTG
1308uid 175,0
1309ps "CptPortTextPlaceStrategy"
1310stg "VerticalLayoutStrategy"
1311f (Text
1312uid 176,0
1313va (VaSet
1314)
1315xt "82000,47500,88900,48500"
1316st "adc_data_array"
1317blo "82000,48300"
1318)
1319)
1320thePort (LogicalPort
1321decl (Decl
1322n "adc_data_array"
1323t "adc_data_array_type"
1324o 8
1325suid 41,0
1326)
1327)
1328)
1329*30 (CptPort
1330uid 177,0
1331ps "OnEdgeStrategy"
1332shape (Triangle
1333uid 178,0
1334ro 270
1335va (VaSet
1336vasetType 1
1337fg "0,65535,0"
1338)
1339xt "80250,61625,81000,62375"
1340)
1341tg (CPTG
1342uid 179,0
1343ps "CptPortTextPlaceStrategy"
1344stg "VerticalLayoutStrategy"
1345f (Text
1346uid 180,0
1347va (VaSet
1348)
1349xt "82000,61500,91500,62500"
1350st "drs_channel_id : (3:0)"
1351blo "82000,62300"
1352)
1353)
1354thePort (LogicalPort
1355m 1
1356decl (Decl
1357n "drs_channel_id"
1358t "std_logic_vector"
1359b "(3 downto 0)"
1360o 35
1361suid 48,0
1362i "(others => '0')"
1363)
1364)
1365)
1366*31 (CptPort
1367uid 181,0
1368ps "OnEdgeStrategy"
1369shape (Triangle
1370uid 182,0
1371ro 270
1372va (VaSet
1373vasetType 1
1374fg "0,65535,0"
1375)
1376xt "80250,66625,81000,67375"
1377)
1378tg (CPTG
1379uid 183,0
1380ps "CptPortTextPlaceStrategy"
1381stg "VerticalLayoutStrategy"
1382f (Text
1383uid 184,0
1384va (VaSet
1385)
1386xt "82000,66500,87200,67500"
1387st "drs_dwrite"
1388blo "82000,67300"
1389)
1390)
1391thePort (LogicalPort
1392m 1
1393decl (Decl
1394n "drs_dwrite"
1395t "std_logic"
1396o 36
1397suid 49,0
1398i "'1'"
1399)
1400)
1401)
1402*32 (CptPort
1403uid 185,0
1404ps "OnEdgeStrategy"
1405shape (Triangle
1406uid 186,0
1407ro 90
1408va (VaSet
1409vasetType 1
1410fg "0,65535,0"
1411)
1412xt "80250,57625,81000,58375"
1413)
1414tg (CPTG
1415uid 187,0
1416ps "CptPortTextPlaceStrategy"
1417stg "VerticalLayoutStrategy"
1418f (Text
1419uid 188,0
1420va (VaSet
1421)
1422xt "82000,57500,87800,58500"
1423st "SROUT_in_0"
1424blo "82000,58300"
1425)
1426)
1427thePort (LogicalPort
1428decl (Decl
1429n "SROUT_in_0"
1430t "std_logic"
1431o 4
1432suid 52,0
1433)
1434)
1435)
1436*33 (CptPort
1437uid 189,0
1438ps "OnEdgeStrategy"
1439shape (Triangle
1440uid 190,0
1441ro 90
1442va (VaSet
1443vasetType 1
1444fg "0,65535,0"
1445)
1446xt "80250,58625,81000,59375"
1447)
1448tg (CPTG
1449uid 191,0
1450ps "CptPortTextPlaceStrategy"
1451stg "VerticalLayoutStrategy"
1452f (Text
1453uid 192,0
1454va (VaSet
1455)
1456xt "82000,58500,87700,59500"
1457st "SROUT_in_1"
1458blo "82000,59300"
1459)
1460)
1461thePort (LogicalPort
1462decl (Decl
1463n "SROUT_in_1"
1464t "std_logic"
1465o 5
1466suid 53,0
1467)
1468)
1469)
1470*34 (CptPort
1471uid 193,0
1472ps "OnEdgeStrategy"
1473shape (Triangle
1474uid 194,0
1475ro 90
1476va (VaSet
1477vasetType 1
1478fg "0,65535,0"
1479)
1480xt "80250,59625,81000,60375"
1481)
1482tg (CPTG
1483uid 195,0
1484ps "CptPortTextPlaceStrategy"
1485stg "VerticalLayoutStrategy"
1486f (Text
1487uid 196,0
1488va (VaSet
1489)
1490xt "82000,59500,87800,60500"
1491st "SROUT_in_2"
1492blo "82000,60300"
1493)
1494)
1495thePort (LogicalPort
1496decl (Decl
1497n "SROUT_in_2"
1498t "std_logic"
1499o 6
1500suid 54,0
1501)
1502)
1503)
1504*35 (CptPort
1505uid 197,0
1506ps "OnEdgeStrategy"
1507shape (Triangle
1508uid 198,0
1509ro 90
1510va (VaSet
1511vasetType 1
1512fg "0,65535,0"
1513)
1514xt "80250,60625,81000,61375"
1515)
1516tg (CPTG
1517uid 199,0
1518ps "CptPortTextPlaceStrategy"
1519stg "VerticalLayoutStrategy"
1520f (Text
1521uid 200,0
1522va (VaSet
1523)
1524xt "82000,60500,87800,61500"
1525st "SROUT_in_3"
1526blo "82000,61300"
1527)
1528)
1529thePort (LogicalPort
1530decl (Decl
1531n "SROUT_in_3"
1532t "std_logic"
1533o 7
1534suid 55,0
1535)
1536)
1537)
1538*36 (CptPort
1539uid 201,0
1540ps "OnEdgeStrategy"
1541shape (Triangle
1542uid 202,0
1543ro 270
1544va (VaSet
1545vasetType 1
1546fg "0,65535,0"
1547)
1548xt "80250,63625,81000,64375"
1549)
1550tg (CPTG
1551uid 203,0
1552ps "CptPortTextPlaceStrategy"
1553stg "VerticalLayoutStrategy"
1554f (Text
1555uid 204,0
1556va (VaSet
1557)
1558xt "82000,63500,86200,64500"
1559st "RSRLOAD"
1560blo "82000,64300"
1561)
1562)
1563thePort (LogicalPort
1564m 1
1565decl (Decl
1566n "RSRLOAD"
1567t "std_logic"
1568o 23
1569suid 56,0
1570i "'0'"
1571)
1572)
1573)
1574*37 (CptPort
1575uid 205,0
1576ps "OnEdgeStrategy"
1577shape (Triangle
1578uid 206,0
1579ro 270
1580va (VaSet
1581vasetType 1
1582fg "0,65535,0"
1583)
1584xt "80250,64625,81000,65375"
1585)
1586tg (CPTG
1587uid 207,0
1588ps "CptPortTextPlaceStrategy"
1589stg "VerticalLayoutStrategy"
1590f (Text
1591uid 208,0
1592va (VaSet
1593)
1594xt "82000,64500,84900,65500"
1595st "SRCLK"
1596blo "82000,65300"
1597)
1598)
1599thePort (LogicalPort
1600m 1
1601decl (Decl
1602n "SRCLK"
1603t "std_logic"
1604o 24
1605suid 57,0
1606i "'0'"
1607)
1608)
1609)
1610*38 (CptPort
1611uid 209,0
1612ps "OnEdgeStrategy"
1613shape (Triangle
1614uid 210,0
1615ro 90
1616va (VaSet
1617vasetType 1
1618fg "0,65535,0"
1619)
1620xt "109000,50625,109750,51375"
1621)
1622tg (CPTG
1623uid 211,0
1624ps "CptPortTextPlaceStrategy"
1625stg "RightVerticalLayoutStrategy"
1626f (Text
1627uid 212,0
1628va (VaSet
1629)
1630xt "106100,50500,108000,51500"
1631st "sclk"
1632ju 2
1633blo "108000,51300"
1634)
1635)
1636thePort (LogicalPort
1637m 1
1638decl (Decl
1639n "sclk"
1640t "std_logic"
1641o 42
1642suid 62,0
1643)
1644)
1645)
1646*39 (CptPort
1647uid 213,0
1648ps "OnEdgeStrategy"
1649shape (Diamond
1650uid 214,0
1651ro 90
1652va (VaSet
1653vasetType 1
1654fg "0,65535,0"
1655)
1656xt "109000,51625,109750,52375"
1657)
1658tg (CPTG
1659uid 215,0
1660ps "CptPortTextPlaceStrategy"
1661stg "RightVerticalLayoutStrategy"
1662f (Text
1663uid 216,0
1664va (VaSet
1665)
1666xt "106600,51500,108000,52500"
1667st "sio"
1668ju 2
1669blo "108000,52300"
1670)
1671)
1672thePort (LogicalPort
1673m 2
1674decl (Decl
1675n "sio"
1676t "std_logic"
1677preAdd 0
1678posAdd 0
1679o 51
1680suid 63,0
1681)
1682)
1683)
1684*40 (CptPort
1685uid 217,0
1686ps "OnEdgeStrategy"
1687shape (Triangle
1688uid 218,0
1689ro 90
1690va (VaSet
1691vasetType 1
1692fg "0,65535,0"
1693)
1694xt "109000,39625,109750,40375"
1695)
1696tg (CPTG
1697uid 219,0
1698ps "CptPortTextPlaceStrategy"
1699stg "RightVerticalLayoutStrategy"
1700f (Text
1701uid 220,0
1702va (VaSet
1703)
1704xt "105000,39500,108000,40500"
1705st "dac_cs"
1706ju 2
1707blo "108000,40300"
1708)
1709)
1710thePort (LogicalPort
1711m 1
1712decl (Decl
1713n "dac_cs"
1714t "std_logic"
1715o 31
1716suid 64,0
1717)
1718)
1719)
1720*41 (CptPort
1721uid 221,0
1722ps "OnEdgeStrategy"
1723shape (Triangle
1724uid 222,0
1725ro 90
1726va (VaSet
1727vasetType 1
1728fg "0,65535,0"
1729)
1730xt "109000,41625,109750,42375"
1731)
1732tg (CPTG
1733uid 223,0
1734ps "CptPortTextPlaceStrategy"
1735stg "RightVerticalLayoutStrategy"
1736f (Text
1737uid 224,0
1738va (VaSet
1739)
1740xt "101000,41500,108000,42500"
1741st "sensor_cs : (3:0)"
1742ju 2
1743blo "108000,42300"
1744)
1745)
1746thePort (LogicalPort
1747m 1
1748decl (Decl
1749n "sensor_cs"
1750t "std_logic_vector"
1751b "(3 DOWNTO 0)"
1752o 43
1753suid 65,0
1754)
1755)
1756)
1757*42 (CptPort
1758uid 225,0
1759ps "OnEdgeStrategy"
1760shape (Triangle
1761uid 226,0
1762ro 90
1763va (VaSet
1764vasetType 1
1765fg "0,65535,0"
1766)
1767xt "109000,52625,109750,53375"
1768)
1769tg (CPTG
1770uid 227,0
1771ps "CptPortTextPlaceStrategy"
1772stg "RightVerticalLayoutStrategy"
1773f (Text
1774uid 228,0
1775va (VaSet
1776)
1777xt "106000,52500,108000,53500"
1778st "mosi"
1779ju 2
1780blo "108000,53300"
1781)
1782)
1783thePort (LogicalPort
1784m 1
1785decl (Decl
1786n "mosi"
1787t "std_logic"
1788o 40
1789suid 66,0
1790i "'0'"
1791)
1792)
1793)
1794*43 (CptPort
1795uid 229,0
1796ps "OnEdgeStrategy"
1797shape (Triangle
1798uid 230,0
1799ro 270
1800va (VaSet
1801vasetType 1
1802fg "0,65535,0"
1803)
1804xt "80250,65625,81000,66375"
1805)
1806tg (CPTG
1807uid 231,0
1808ps "CptPortTextPlaceStrategy"
1809stg "VerticalLayoutStrategy"
1810f (Text
1811uid 232,0
1812va (VaSet
1813)
1814xt "82000,65500,85200,66500"
1815st "denable"
1816blo "82000,66300"
1817)
1818)
1819thePort (LogicalPort
1820m 1
1821decl (Decl
1822n "denable"
1823t "std_logic"
1824eolc "-- default domino wave off"
1825posAdd 0
1826o 34
1827suid 67,0
1828i "'0'"
1829)
1830)
1831)
1832*44 (CptPort
1833uid 1395,0
1834ps "OnEdgeStrategy"
1835shape (Triangle
1836uid 1396,0
1837ro 90
1838va (VaSet
1839vasetType 1
1840fg "0,65535,0"
1841)
1842xt "109000,73625,109750,74375"
1843)
1844tg (CPTG
1845uid 1397,0
1846ps "CptPortTextPlaceStrategy"
1847stg "RightVerticalLayoutStrategy"
1848f (Text
1849uid 1398,0
1850va (VaSet
1851)
1852xt "98000,73500,108000,74500"
1853st "alarm_refclk_too_high"
1854ju 2
1855blo "108000,74300"
1856)
1857)
1858thePort (LogicalPort
1859m 1
1860decl (Decl
1861n "alarm_refclk_too_high"
1862t "std_logic"
1863o 27
1864suid 95,0
1865)
1866)
1867)
1868*45 (CptPort
1869uid 1399,0
1870ps "OnEdgeStrategy"
1871shape (Triangle
1872uid 1400,0
1873ro 90
1874va (VaSet
1875vasetType 1
1876fg "0,65535,0"
1877)
1878xt "109000,74625,109750,75375"
1879)
1880tg (CPTG
1881uid 1401,0
1882ps "CptPortTextPlaceStrategy"
1883stg "RightVerticalLayoutStrategy"
1884f (Text
1885uid 1402,0
1886va (VaSet
1887)
1888xt "98400,74500,108000,75500"
1889st "alarm_refclk_too_low"
1890ju 2
1891blo "108000,75300"
1892)
1893)
1894thePort (LogicalPort
1895m 1
1896decl (Decl
1897n "alarm_refclk_too_low"
1898t "std_logic"
1899posAdd 0
1900o 28
1901suid 96,0
1902)
1903)
1904)
1905*46 (CptPort
1906uid 1403,0
1907ps "OnEdgeStrategy"
1908shape (Triangle
1909uid 1404,0
1910ro 90
1911va (VaSet
1912vasetType 1
1913fg "0,65535,0"
1914)
1915xt "109000,79625,109750,80375"
1916)
1917tg (CPTG
1918uid 1405,0
1919ps "CptPortTextPlaceStrategy"
1920stg "RightVerticalLayoutStrategy"
1921f (Text
1922uid 1406,0
1923va (VaSet
1924)
1925xt "105300,79500,108000,80500"
1926st "amber"
1927ju 2
1928blo "108000,80300"
1929)
1930)
1931thePort (LogicalPort
1932m 1
1933decl (Decl
1934n "amber"
1935t "std_logic"
1936o 29
1937suid 87,0
1938)
1939)
1940)
1941*47 (CptPort
1942uid 1407,0
1943ps "OnEdgeStrategy"
1944shape (Triangle
1945uid 1408,0
1946ro 90
1947va (VaSet
1948vasetType 1
1949fg "0,65535,0"
1950)
1951xt "109000,76625,109750,77375"
1952)
1953tg (CPTG
1954uid 1409,0
1955ps "CptPortTextPlaceStrategy"
1956stg "RightVerticalLayoutStrategy"
1957f (Text
1958uid 1410,0
1959va (VaSet
1960)
1961xt "98400,76500,108000,77500"
1962st "counter_result : (11:0)"
1963ju 2
1964blo "108000,77300"
1965)
1966)
1967thePort (LogicalPort
1968m 1
1969decl (Decl
1970n "counter_result"
1971t "std_logic_vector"
1972b "(11 DOWNTO 0)"
1973o 30
1974suid 94,0
1975)
1976)
1977)
1978*48 (CptPort
1979uid 1411,0
1980ps "OnEdgeStrategy"
1981shape (Triangle
1982uid 1412,0
1983ro 90
1984va (VaSet
1985vasetType 1
1986fg "0,65535,0"
1987)
1988xt "80250,74625,81000,75375"
1989)
1990tg (CPTG
1991uid 1413,0
1992ps "CptPortTextPlaceStrategy"
1993stg "VerticalLayoutStrategy"
1994f (Text
1995uid 1414,0
1996va (VaSet
1997)
1998xt "82000,74500,87500,75500"
1999st "D_T_in : (1:0)"
2000blo "82000,75300"
2001)
2002)
2003thePort (LogicalPort
2004decl (Decl
2005n "D_T_in"
2006t "std_logic_vector"
2007b "(1 DOWNTO 0)"
2008o 2
2009suid 91,0
2010)
2011)
2012)
2013*49 (CptPort
2014uid 1415,0
2015ps "OnEdgeStrategy"
2016shape (Triangle
2017uid 1416,0
2018ro 90
2019va (VaSet
2020vasetType 1
2021fg "0,65535,0"
2022)
2023xt "80250,75625,81000,76375"
2024)
2025tg (CPTG
2026uid 1417,0
2027ps "CptPortTextPlaceStrategy"
2028stg "VerticalLayoutStrategy"
2029f (Text
2030uid 1418,0
2031va (VaSet
2032)
2033xt "82000,75500,88100,76500"
2034st "drs_refclk_in"
2035blo "82000,76300"
2036)
2037)
2038thePort (LogicalPort
2039decl (Decl
2040n "drs_refclk_in"
2041t "std_logic"
2042eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
2043o 12
2044suid 92,0
2045)
2046)
2047)
2048*50 (CptPort
2049uid 1419,0
2050ps "OnEdgeStrategy"
2051shape (Triangle
2052uid 1420,0
2053ro 90
2054va (VaSet
2055vasetType 1
2056fg "0,65535,0"
2057)
2058xt "109000,77625,109750,78375"
2059)
2060tg (CPTG
2061uid 1421,0
2062ps "CptPortTextPlaceStrategy"
2063stg "RightVerticalLayoutStrategy"
2064f (Text
2065uid 1422,0
2066va (VaSet
2067)
2068xt "105600,77500,108000,78500"
2069st "green"
2070ju 2
2071blo "108000,78300"
2072)
2073)
2074thePort (LogicalPort
2075m 1
2076decl (Decl
2077n "green"
2078t "std_logic"
2079o 37
2080suid 86,0
2081)
2082)
2083)
2084*51 (CptPort
2085uid 1423,0
2086ps "OnEdgeStrategy"
2087shape (Triangle
2088uid 1424,0
2089ro 90
2090va (VaSet
2091vasetType 1
2092fg "0,65535,0"
2093)
2094xt "80250,76625,81000,77375"
2095)
2096tg (CPTG
2097uid 1425,0
2098ps "CptPortTextPlaceStrategy"
2099stg "VerticalLayoutStrategy"
2100f (Text
2101uid 1426,0
2102va (VaSet
2103)
2104xt "82000,76500,88700,77500"
2105st "plllock_in : (3:0)"
2106blo "82000,77300"
2107)
2108)
2109thePort (LogicalPort
2110decl (Decl
2111n "plllock_in"
2112t "std_logic_vector"
2113b "(3 DOWNTO 0)"
2114eolc "-- high level, if dominowave is running and DRS PLL locked"
2115o 13
2116suid 93,0
2117)
2118)
2119)
2120*52 (CptPort
2121uid 1427,0
2122ps "OnEdgeStrategy"
2123shape (Triangle
2124uid 1428,0
2125ro 90
2126va (VaSet
2127vasetType 1
2128fg "0,65535,0"
2129)
2130xt "109000,78625,109750,79375"
2131)
2132tg (CPTG
2133uid 1429,0
2134ps "CptPortTextPlaceStrategy"
2135stg "RightVerticalLayoutStrategy"
2136f (Text
2137uid 1430,0
2138va (VaSet
2139)
2140xt "106300,78500,108000,79500"
2141st "red"
2142ju 2
2143blo "108000,79300"
2144)
2145)
2146thePort (LogicalPort
2147m 1
2148decl (Decl
2149n "red"
2150t "std_logic"
2151o 41
2152suid 88,0
2153)
2154)
2155)
2156*53 (CptPort
2157uid 1431,0
2158ps "OnEdgeStrategy"
2159shape (Triangle
2160uid 1432,0
2161ro 270
2162va (VaSet
2163vasetType 1
2164fg "0,65535,0"
2165)
2166xt "80250,71625,81000,72375"
2167)
2168tg (CPTG
2169uid 1433,0
2170ps "CptPortTextPlaceStrategy"
2171stg "VerticalLayoutStrategy"
2172f (Text
2173uid 1434,0
2174va (VaSet
2175)
2176xt "82000,71500,86200,72500"
2177st "SRIN_out"
2178blo "82000,72300"
2179)
2180)
2181thePort (LogicalPort
2182m 1
2183decl (Decl
2184n "SRIN_out"
2185t "std_logic"
2186o 25
2187suid 85,0
2188i "'0'"
2189)
2190)
2191)
2192*54 (CptPort
2193uid 1678,0
2194ps "OnEdgeStrategy"
2195shape (Triangle
2196uid 1679,0
2197ro 270
2198va (VaSet
2199vasetType 1
2200fg "0,65535,0"
2201)
2202xt "80250,23625,81000,24375"
2203)
2204tg (CPTG
2205uid 1680,0
2206ps "CptPortTextPlaceStrategy"
2207stg "VerticalLayoutStrategy"
2208f (Text
2209uid 1681,0
2210va (VaSet
2211)
2212xt "82000,23500,86000,24500"
2213st "ADC_CLK"
2214blo "82000,24300"
2215)
2216)
2217thePort (LogicalPort
2218lang 2
2219m 1
2220decl (Decl
2221n "ADC_CLK"
2222t "std_logic"
2223o 16
2224suid 97,0
2225)
2226)
2227)
2228*55 (CptPort
2229uid 2651,0
2230ps "OnEdgeStrategy"
2231shape (Triangle
2232uid 2652,0
2233ro 90
2234va (VaSet
2235vasetType 1
2236fg "0,65535,0"
2237)
2238xt "109000,80625,109750,81375"
2239)
2240tg (CPTG
2241uid 2653,0
2242ps "CptPortTextPlaceStrategy"
2243stg "RightVerticalLayoutStrategy"
2244f (Text
2245uid 2654,0
2246va (VaSet
2247)
2248xt "97600,80500,108000,81500"
2249st "debug_data_ram_empty"
2250ju 2
2251blo "108000,81300"
2252)
2253)
2254thePort (LogicalPort
2255m 1
2256decl (Decl
2257n "debug_data_ram_empty"
2258t "std_logic"
2259o 32
2260suid 104,0
2261)
2262)
2263)
2264*56 (CptPort
2265uid 2655,0
2266ps "OnEdgeStrategy"
2267shape (Triangle
2268uid 2656,0
2269ro 90
2270va (VaSet
2271vasetType 1
2272fg "0,65535,0"
2273)
2274xt "109000,81625,109750,82375"
2275)
2276tg (CPTG
2277uid 2657,0
2278ps "CptPortTextPlaceStrategy"
2279stg "RightVerticalLayoutStrategy"
2280f (Text
2281uid 2658,0
2282va (VaSet
2283)
2284xt "100500,81500,108000,82500"
2285st "debug_data_valid"
2286ju 2
2287blo "108000,82300"
2288)
2289)
2290thePort (LogicalPort
2291m 1
2292decl (Decl
2293n "debug_data_valid"
2294t "std_logic"
2295o 33
2296suid 105,0
2297)
2298)
2299)
2300*57 (CptPort
2301uid 2659,0
2302ps "OnEdgeStrategy"
2303shape (Triangle
2304uid 2660,0
2305ro 90
2306va (VaSet
2307vasetType 1
2308fg "0,65535,0"
2309)
2310xt "109000,82625,109750,83375"
2311)
2312tg (CPTG
2313uid 2661,0
2314ps "CptPortTextPlaceStrategy"
2315stg "RightVerticalLayoutStrategy"
2316f (Text
2317uid 2662,0
2318va (VaSet
2319)
2320xt "101100,82500,108000,83500"
2321st "DG_state : (7:0)"
2322ju 2
2323blo "108000,83300"
2324)
2325)
2326thePort (LogicalPort
2327m 1
2328decl (Decl
2329n "DG_state"
2330t "std_logic_vector"
2331b "(7 downto 0)"
2332prec "-- for debugging"
2333preAdd 0
2334o 19
2335suid 108,0
2336)
2337)
2338)
2339*58 (CptPort
2340uid 2663,0
2341ps "OnEdgeStrategy"
2342shape (Triangle
2343uid 2664,0
2344ro 90
2345va (VaSet
2346vasetType 1
2347fg "0,65535,0"
2348)
2349xt "80250,77625,81000,78375"
2350)
2351tg (CPTG
2352uid 2665,0
2353ps "CptPortTextPlaceStrategy"
2354stg "VerticalLayoutStrategy"
2355f (Text
2356uid 2666,0
2357va (VaSet
2358)
2359xt "82000,77500,90100,78500"
2360st "FTM_RS485_rx_d"
2361blo "82000,78300"
2362)
2363)
2364thePort (LogicalPort
2365decl (Decl
2366n "FTM_RS485_rx_d"
2367t "std_logic"
2368o 3
2369suid 99,0
2370)
2371)
2372)
2373*59 (CptPort
2374uid 2667,0
2375ps "OnEdgeStrategy"
2376shape (Triangle
2377uid 2668,0
2378ro 90
2379va (VaSet
2380vasetType 1
2381fg "0,65535,0"
2382)
2383xt "109000,83625,109750,84375"
2384)
2385tg (CPTG
2386uid 2669,0
2387ps "CptPortTextPlaceStrategy"
2388stg "RightVerticalLayoutStrategy"
2389f (Text
2390uid 2670,0
2391va (VaSet
2392)
2393xt "99600,83500,108000,84500"
2394st "FTM_RS485_rx_en"
2395ju 2
2396blo "108000,84300"
2397)
2398)
2399thePort (LogicalPort
2400m 1
2401decl (Decl
2402n "FTM_RS485_rx_en"
2403t "std_logic"
2404o 20
2405suid 101,0
2406)
2407)
2408)
2409*60 (CptPort
2410uid 2671,0
2411ps "OnEdgeStrategy"
2412shape (Triangle
2413uid 2672,0
2414ro 90
2415va (VaSet
2416vasetType 1
2417fg "0,65535,0"
2418)
2419xt "109000,84625,109750,85375"
2420)
2421tg (CPTG
2422uid 2673,0
2423ps "CptPortTextPlaceStrategy"
2424stg "RightVerticalLayoutStrategy"
2425f (Text
2426uid 2674,0
2427va (VaSet
2428)
2429xt "99900,84500,108000,85500"
2430st "FTM_RS485_tx_d"
2431ju 2
2432blo "108000,85300"
2433)
2434)
2435thePort (LogicalPort
2436m 1
2437decl (Decl
2438n "FTM_RS485_tx_d"
2439t "std_logic"
2440o 21
2441suid 100,0
2442)
2443)
2444)
2445*61 (CptPort
2446uid 2675,0
2447ps "OnEdgeStrategy"
2448shape (Triangle
2449uid 2676,0
2450ro 90
2451va (VaSet
2452vasetType 1
2453fg "0,65535,0"
2454)
2455xt "109000,85625,109750,86375"
2456)
2457tg (CPTG
2458uid 2677,0
2459ps "CptPortTextPlaceStrategy"
2460stg "RightVerticalLayoutStrategy"
2461f (Text
2462uid 2678,0
2463va (VaSet
2464)
2465xt "99600,85500,108000,86500"
2466st "FTM_RS485_tx_en"
2467ju 2
2468blo "108000,86300"
2469)
2470)
2471thePort (LogicalPort
2472m 1
2473decl (Decl
2474n "FTM_RS485_tx_en"
2475t "std_logic"
2476o 22
2477suid 102,0
2478)
2479)
2480)
2481*62 (CptPort
2482uid 2679,0
2483ps "OnEdgeStrategy"
2484shape (Triangle
2485uid 2680,0
2486ro 90
2487va (VaSet
2488vasetType 1
2489fg "0,65535,0"
2490)
2491xt "109000,86625,109750,87375"
2492)
2493tg (CPTG
2494uid 2681,0
2495ps "CptPortTextPlaceStrategy"
2496stg "RightVerticalLayoutStrategy"
2497f (Text
2498uid 2682,0
2499va (VaSet
2500)
2501xt "96600,86500,108000,87500"
2502st "mem_manager_state : (3:0)"
2503ju 2
2504blo "108000,87300"
2505)
2506)
2507thePort (LogicalPort
2508lang 2
2509m 1
2510decl (Decl
2511n "mem_manager_state"
2512t "std_logic_vector"
2513b "(3 DOWNTO 0)"
2514eolc "-- state is encoded here ... useful for debugging."
2515posAdd 0
2516o 39
2517suid 106,0
2518)
2519)
2520)
2521*63 (CptPort
2522uid 2683,0
2523ps "OnEdgeStrategy"
2524shape (Triangle
2525uid 2684,0
2526ro 90
2527va (VaSet
2528vasetType 1
2529fg "0,65535,0"
2530)
2531xt "109000,87625,109750,88375"
2532)
2533tg (CPTG
2534uid 2685,0
2535ps "CptPortTextPlaceStrategy"
2536stg "RightVerticalLayoutStrategy"
2537f (Text
2538uid 2686,0
2539va (VaSet
2540)
2541xt "102400,87500,108000,88500"
2542st "trigger_veto"
2543ju 2
2544blo "108000,88300"
2545)
2546)
2547thePort (LogicalPort
2548m 1
2549decl (Decl
2550n "trigger_veto"
2551t "std_logic"
2552o 44
2553suid 98,0
2554i "'1'"
2555)
2556)
2557)
2558*64 (CptPort
2559uid 2687,0
2560ps "OnEdgeStrategy"
2561shape (Triangle
2562uid 2688,0
2563ro 90
2564va (VaSet
2565vasetType 1
2566fg "0,65535,0"
2567)
2568xt "109000,88625,109750,89375"
2569)
2570tg (CPTG
2571uid 2689,0
2572ps "CptPortTextPlaceStrategy"
2573stg "RightVerticalLayoutStrategy"
2574f (Text
2575uid 2690,0
2576va (VaSet
2577)
2578xt "99600,88500,108000,89500"
2579st "w5300_state : (7:0)"
2580ju 2
2581blo "108000,89300"
2582)
2583)
2584thePort (LogicalPort
2585m 1
2586decl (Decl
2587n "w5300_state"
2588t "std_logic_vector"
2589b "(7 DOWNTO 0)"
2590eolc "-- state is encoded here ... useful for debugging."
2591posAdd 0
2592o 45
2593suid 103,0
2594)
2595)
2596)
2597]
2598shape (Rectangle
2599uid 234,0
2600va (VaSet
2601vasetType 1
2602fg "0,65535,0"
2603lineColor "0,32896,0"
2604lineWidth 2
2605)
2606xt "81000,19000,109000,90000"
2607)
2608oxt "15000,-8000,43000,46000"
2609ttg (MlTextGroup
2610uid 235,0
2611ps "CenterOffsetStrategy"
2612stg "VerticalLayoutStrategy"
2613textVec [
2614*65 (Text
2615uid 236,0
2616va (VaSet
2617font "Arial,8,1"
2618)
2619xt "83200,81000,89400,82000"
2620st "FACT_FAD_lib"
2621blo "83200,81800"
2622tm "BdLibraryNameMgr"
2623)
2624*66 (Text
2625uid 237,0
2626va (VaSet
2627font "Arial,8,1"
2628)
2629xt "83200,82000,87400,83000"
2630st "FAD_main"
2631blo "83200,82800"
2632tm "CptNameMgr"
2633)
2634*67 (Text
2635uid 238,0
2636va (VaSet
2637font "Arial,8,1"
2638)
2639xt "83200,83000,90000,84000"
2640st "I_mainTB_FPGA"
2641blo "83200,83800"
2642tm "InstanceNameMgr"
2643)
2644]
2645)
2646ga (GenericAssociation
2647uid 239,0
2648ps "EdgeToEdgeStrategy"
2649matrix (Matrix
2650uid 240,0
2651text (MLText
2652uid 241,0
2653va (VaSet
2654font "Courier New,8,0"
2655)
2656xt "81000,18200,101000,19000"
2657st "RAMADDRWIDTH64b = 15    ( integer )  "
2658)
2659header ""
2660)
2661elements [
2662(GiElement
2663name "RAMADDRWIDTH64b"
2664type "integer"
2665value "15"
2666)
2667]
2668)
2669viewicon (ZoomableIcon
2670uid 242,0
2671sl 0
2672va (VaSet
2673vasetType 1
2674fg "49152,49152,49152"
2675)
2676xt "81250,88250,82750,89750"
2677iconName "BlockDiagram.png"
2678iconMaskName "BlockDiagram.msk"
2679ftype 1
2680)
2681viewiconposition 0
2682portVis (PortSigDisplay
2683)
2684archFileType "UNKNOWN"
2685)
2686*68 (SaComponent
2687uid 274,0
2688optionalChildren [
2689*69 (CptPort
2690uid 266,0
2691ps "OnEdgeStrategy"
2692shape (Triangle
2693uid 267,0
2694ro 90
2695va (VaSet
2696vasetType 1
2697fg "0,65535,0"
2698)
2699xt "58000,20625,58750,21375"
2700)
2701tg (CPTG
2702uid 268,0
2703ps "CptPortTextPlaceStrategy"
2704stg "RightVerticalLayoutStrategy"
2705f (Text
2706uid 269,0
2707va (VaSet
2708)
2709xt "55700,20500,57000,21500"
2710st "clk"
2711ju 2
2712blo "57000,21300"
2713)
2714)
2715thePort (LogicalPort
2716m 1
2717decl (Decl
2718n "clk"
2719t "STD_LOGIC"
2720o 1
2721i "'0'"
2722)
2723)
2724)
2725*70 (CptPort
2726uid 270,0
2727ps "OnEdgeStrategy"
2728shape (Triangle
2729uid 271,0
2730ro 90
2731va (VaSet
2732vasetType 1
2733fg "0,65535,0"
2734)
2735xt "58000,21625,58750,22375"
2736)
2737tg (CPTG
2738uid 272,0
2739ps "CptPortTextPlaceStrategy"
2740stg "RightVerticalLayoutStrategy"
2741f (Text
2742uid 273,0
2743va (VaSet
2744)
2745xt "55700,21500,57000,22500"
2746st "rst"
2747ju 2
2748blo "57000,22300"
2749)
2750)
2751thePort (LogicalPort
2752m 1
2753decl (Decl
2754n "rst"
2755t "STD_LOGIC"
2756o 2
2757i "'0'"
2758)
2759)
2760)
2761]
2762shape (Rectangle
2763uid 275,0
2764va (VaSet
2765vasetType 1
2766fg "0,49152,49152"
2767lineColor "0,0,50000"
2768lineWidth 2
2769)
2770xt "50000,19000,58000,24000"
2771)
2772oxt "0,0,8000,10000"
2773ttg (MlTextGroup
2774uid 276,0
2775ps "CenterOffsetStrategy"
2776stg "VerticalLayoutStrategy"
2777textVec [
2778*71 (Text
2779uid 277,0
2780va (VaSet
2781font "Arial,8,1"
2782)
2783xt "50150,24000,57850,25000"
2784st "FACT_FAD_TB_lib"
2785blo "50150,24800"
2786tm "BdLibraryNameMgr"
2787)
2788*72 (Text
2789uid 278,0
2790va (VaSet
2791font "Arial,8,1"
2792)
2793xt "50150,25000,56850,26000"
2794st "clock_generator"
2795blo "50150,25800"
2796tm "CptNameMgr"
2797)
2798*73 (Text
2799uid 279,0
2800va (VaSet
2801font "Arial,8,1"
2802)
2803xt "50150,26000,56750,27000"
2804st "I_mainTB_clock"
2805blo "50150,26800"
2806tm "InstanceNameMgr"
2807)
2808]
2809)
2810ga (GenericAssociation
2811uid 280,0
2812ps "EdgeToEdgeStrategy"
2813matrix (Matrix
2814uid 281,0
2815text (MLText
2816uid 282,0
2817va (VaSet
2818font "Courier New,8,0"
2819)
2820xt "50000,17400,68500,19000"
2821st "clock_period = 20 ns    ( time ) 
2822reset_time   = 50 ns    ( time )  "
2823)
2824header ""
2825)
2826elements [
2827(GiElement
2828name "clock_period"
2829type "time"
2830value "20 ns"
2831)
2832(GiElement
2833name "reset_time"
2834type "time"
2835value "50 ns"
2836)
2837]
2838)
2839viewicon (ZoomableIcon
2840uid 283,0
2841sl 0
2842va (VaSet
2843vasetType 1
2844fg "49152,49152,49152"
2845)
2846xt "50250,22250,51750,23750"
2847iconName "VhdlFileViewIcon.png"
2848iconMaskName "VhdlFileViewIcon.msk"
2849ftype 10
2850)
2851ordering 1
2852viewiconposition 0
2853portVis (PortSigDisplay
2854)
2855archFileType "UNKNOWN"
2856)
2857*74 (Net
2858uid 284,0
2859decl (Decl
2860n "clk"
2861t "STD_LOGIC"
2862preAdd 0
2863posAdd 0
2864o 1
2865suid 1,0
2866)
2867declText (MLText
2868uid 285,0
2869va (VaSet
2870font "Courier New,8,0"
2871)
2872xt "-90000,46200,-68000,47000"
2873st "SIGNAL clk                   : STD_LOGIC
2874"
2875)
2876)
2877*75 (Net
2878uid 316,0
2879decl (Decl
2880n "wiz_addr"
2881t "std_logic_vector"
2882b "(9 DOWNTO 0)"
2883o 2
2884suid 2,0
2885)
2886declText (MLText
2887uid 317,0
2888va (VaSet
2889font "Courier New,8,0"
2890)
2891xt "-90000,63000,-58500,63800"
2892st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)
2893"
2894)
2895)
2896*76 (Net
2897uid 322,0
2898decl (Decl
2899n "wiz_data"
2900t "std_logic_vector"
2901b "(15 DOWNTO 0)"
2902o 3
2903suid 3,0
2904)
2905declText (MLText
2906uid 323,0
2907va (VaSet
2908font "Courier New,8,0"
2909)
2910xt "-90000,64600,-58000,65400"
2911st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)
2912"
2913)
2914)
2915*77 (Net
2916uid 328,0
2917decl (Decl
2918n "wiz_rd"
2919t "std_logic"
2920o 4
2921suid 4,0
2922i "'1'"
2923)
2924declText (MLText
2925uid 329,0
2926va (VaSet
2927font "Courier New,8,0"
2928)
2929xt "-90000,66200,-55000,67000"
2930st "SIGNAL wiz_rd                : std_logic                    := '1'
2931"
2932)
2933)
2934*78 (Net
2935uid 334,0
2936decl (Decl
2937n "wiz_wr"
2938t "std_logic"
2939o 5
2940suid 5,0
2941i "'1'"
2942)
2943declText (MLText
2944uid 335,0
2945va (VaSet
2946font "Courier New,8,0"
2947)
2948xt "-90000,67800,-55000,68600"
2949st "SIGNAL wiz_wr                : std_logic                    := '1'
2950"
2951)
2952)
2953*79 (SaComponent
2954uid 362,0
2955optionalChildren [
2956*80 (CptPort
2957uid 350,0
2958ps "OnEdgeStrategy"
2959shape (Triangle
2960uid 351,0
2961ro 90
2962va (VaSet
2963vasetType 1
2964fg "0,65535,0"
2965)
2966xt "122250,50625,123000,51375"
2967)
2968tg (CPTG
2969uid 352,0
2970ps "CptPortTextPlaceStrategy"
2971stg "VerticalLayoutStrategy"
2972f (Text
2973uid 353,0
2974va (VaSet
2975)
2976xt "124000,50500,125700,51500"
2977st "sclk"
2978blo "124000,51300"
2979)
2980)
2981thePort (LogicalPort
2982decl (Decl
2983n "sclk"
2984t "std_logic"
2985preAdd 0
2986posAdd 0
2987o 1
2988suid 1,0
2989)
2990)
2991)
2992*81 (CptPort
2993uid 354,0
2994ps "OnEdgeStrategy"
2995shape (Diamond
2996uid 355,0
2997ro 270
2998va (VaSet
2999vasetType 1
3000fg "0,65535,0"
3001)
3002xt "122250,51625,123000,52375"
3003)
3004tg (CPTG
3005uid 356,0
3006ps "CptPortTextPlaceStrategy"
3007stg "VerticalLayoutStrategy"
3008f (Text
3009uid 357,0
3010va (VaSet
3011)
3012xt "124000,51500,125400,52500"
3013st "sio"
3014blo "124000,52300"
3015)
3016)
3017thePort (LogicalPort
3018m 2
3019decl (Decl
3020n "sio"
3021t "std_logic"
3022preAdd 0
3023posAdd 0
3024o 2
3025suid 2,0
3026)
3027)
3028)
3029*82 (CptPort
3030uid 358,0
3031ps "OnEdgeStrategy"
3032shape (Triangle
3033uid 359,0
3034ro 90
3035va (VaSet
3036vasetType 1
3037fg "0,65535,0"
3038)
3039xt "122250,47625,123000,48375"
3040)
3041tg (CPTG
3042uid 360,0
3043ps "CptPortTextPlaceStrategy"
3044stg "VerticalLayoutStrategy"
3045f (Text
3046uid 361,0
3047va (VaSet
3048)
3049xt "124000,47500,130500,48500"
3050st "sensor_cs : (3:0)"
3051blo "124000,48300"
3052)
3053)
3054thePort (LogicalPort
3055decl (Decl
3056n "sensor_cs"
3057t "std_logic_vector"
3058b "(3 downto 0)"
3059preAdd 0
3060posAdd 0
3061o 3
3062suid 3,0
3063)
3064)
3065)
3066]
3067shape (Rectangle
3068uid 363,0
3069va (VaSet
3070vasetType 1
3071fg "0,49152,49152"
3072lineColor "0,0,50000"
3073lineWidth 2
3074)
3075xt "123000,46000,133000,56000"
3076)
3077oxt "30000,3000,40000,13000"
3078ttg (MlTextGroup
3079uid 364,0
3080ps "CenterOffsetStrategy"
3081stg "VerticalLayoutStrategy"
3082textVec [
3083*83 (Text
3084uid 365,0
3085va (VaSet
3086font "Arial,8,1"
3087)
3088xt "123200,56000,130900,57000"
3089st "FACT_FAD_TB_lib"
3090blo "123200,56800"
3091tm "BdLibraryNameMgr"
3092)
3093*84 (Text
3094uid 366,0
3095va (VaSet
3096font "Arial,8,1"
3097)
3098xt "123200,57000,130800,58000"
3099st "max6662_emulator"
3100blo "123200,57800"
3101tm "CptNameMgr"
3102)
3103*85 (Text
3104uid 367,0
3105va (VaSet
3106font "Arial,8,1"
3107)
3108xt "123200,58000,131000,59000"
3109st "I_mainTB_max6662"
3110blo "123200,58800"
3111tm "InstanceNameMgr"
3112)
3113]
3114)
3115ga (GenericAssociation
3116uid 368,0
3117ps "EdgeToEdgeStrategy"
3118matrix (Matrix
3119uid 369,0
3120text (MLText
3121uid 370,0
3122va (VaSet
3123font "Courier New,8,0"
3124)
3125xt "123000,45200,143000,46000"
3126st "DRS_TEMPERATURE = 51    ( integer )  "
3127)
3128header ""
3129)
3130elements [
3131(GiElement
3132name "DRS_TEMPERATURE"
3133type "integer"
3134value "51"
3135)
3136]
3137)
3138viewicon (ZoomableIcon
3139uid 371,0
3140sl 0
3141va (VaSet
3142vasetType 1
3143fg "49152,49152,49152"
3144)
3145xt "123250,54250,124750,55750"
3146iconName "VhdlFileViewIcon.png"
3147iconMaskName "VhdlFileViewIcon.msk"
3148ftype 10
3149)
3150ordering 1
3151viewiconposition 0
3152portVis (PortSigDisplay
3153sIVOD 1
3154)
3155archFileType "UNKNOWN"
3156)
3157*86 (Net
3158uid 372,0
3159decl (Decl
3160n "sensor_cs"
3161t "std_logic_vector"
3162b "(3 DOWNTO 0)"
3163o 6
3164suid 6,0
3165)
3166declText (MLText
3167uid 373,0
3168va (VaSet
3169font "Courier New,8,0"
3170)
3171xt "-90000,59000,-58500,59800"
3172st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)
3173"
3174)
3175)
3176*87 (Net
3177uid 378,0
3178decl (Decl
3179n "sclk"
3180t "std_logic"
3181o 7
3182suid 7,0
3183)
3184declText (MLText
3185uid 379,0
3186va (VaSet
3187font "Courier New,8,0"
3188)
3189xt "-90000,58200,-68000,59000"
3190st "SIGNAL sclk                  : std_logic
3191"
3192)
3193)
3194*88 (Net
3195uid 384,0
3196decl (Decl
3197n "sio"
3198t "std_logic"
3199preAdd 0
3200posAdd 0
3201o 8
3202suid 8,0
3203)
3204declText (MLText
3205uid 385,0
3206va (VaSet
3207font "Courier New,8,0"
3208)
3209xt "-90000,59800,-68000,60600"
3210st "SIGNAL sio                   : std_logic
3211"
3212)
3213)
3214*89 (SaComponent
3215uid 414,0
3216optionalChildren [
3217*90 (CptPort
3218uid 410,0
3219ps "OnEdgeStrategy"
3220shape (Triangle
3221uid 411,0
3222ro 90
3223va (VaSet
3224vasetType 1
3225fg "0,65535,0"
3226)
3227xt "58000,31625,58750,32375"
3228)
3229tg (CPTG
3230uid 412,0
3231ps "CptPortTextPlaceStrategy"
3232stg "RightVerticalLayoutStrategy"
3233f (Text
3234uid 413,0
3235va (VaSet
3236)
3237xt "54200,31500,57000,32500"
3238st "trigger"
3239ju 2
3240blo "57000,32300"
3241)
3242)
3243thePort (LogicalPort
3244m 1
3245decl (Decl
3246n "trigger"
3247t "std_logic"
3248preAdd 0
3249posAdd 0
3250o 1
3251suid 1,0
3252)
3253)
3254)
3255]
3256shape (Rectangle
3257uid 415,0
3258va (VaSet
3259vasetType 1
3260fg "0,49152,49152"
3261lineColor "0,0,50000"
3262lineWidth 2
3263)
3264xt "50000,30000,58000,36000"
3265)
3266oxt "19000,4000,29000,14000"
3267ttg (MlTextGroup
3268uid 416,0
3269ps "CenterOffsetStrategy"
3270stg "VerticalLayoutStrategy"
3271textVec [
3272*91 (Text
3273uid 417,0
3274va (VaSet
3275font "Arial,8,1"
3276)
3277xt "50200,36000,57900,37000"
3278st "FACT_FAD_TB_lib"
3279blo "50200,36800"
3280tm "BdLibraryNameMgr"
3281)
3282*92 (Text
3283uid 418,0
3284va (VaSet
3285font "Arial,8,1"
3286)
3287xt "50200,37000,57500,38000"
3288st "trigger_generator"
3289blo "50200,37800"
3290tm "CptNameMgr"
3291)
3292*93 (Text
3293uid 419,0
3294va (VaSet
3295font "Arial,8,1"
3296)
3297xt "50200,38000,57400,39000"
3298st "I_mainTB_trigger"
3299blo "50200,38800"
3300tm "InstanceNameMgr"
3301)
3302]
3303)
3304ga (GenericAssociation
3305uid 420,0
3306ps "EdgeToEdgeStrategy"
3307matrix (Matrix
3308uid 421,0
3309text (MLText
3310uid 422,0
3311va (VaSet
3312font "Courier New,8,0"
3313)
3314xt "50000,28400,68500,30000"
3315st "TRIGGER_RATE = 1 ms     ( time ) 
3316PULSE_WIDTH  = 20 ns    ( time )  "
3317)
3318header ""
3319)
3320elements [
3321(GiElement
3322name "TRIGGER_RATE"
3323type "time"
3324value "1 ms"
3325)
3326(GiElement
3327name "PULSE_WIDTH"
3328type "time"
3329value "20 ns"
3330)
3331]
3332)
3333viewicon (ZoomableIcon
3334uid 423,0
3335sl 0
3336va (VaSet
3337vasetType 1
3338fg "49152,49152,49152"
3339)
3340xt "50250,34250,51750,35750"
3341iconName "VhdlFileViewIcon.png"
3342iconMaskName "VhdlFileViewIcon.msk"
3343ftype 10
3344)
3345ordering 1
3346viewiconposition 0
3347portVis (PortSigDisplay
3348sIVOD 1
3349)
3350archFileType "UNKNOWN"
3351)
3352*94 (Net
3353uid 424,0
3354decl (Decl
3355n "trigger"
3356t "std_logic"
3357preAdd 0
3358posAdd 0
3359o 9
3360suid 9,0
3361)
3362declText (MLText
3363uid 425,0
3364va (VaSet
3365font "Courier New,8,0"
3366)
3367xt "-90000,60600,-68000,61400"
3368st "SIGNAL trigger               : std_logic
3369"
3370)
3371)
3372*95 (HdlText
3373uid 430,0
3374optionalChildren [
3375*96 (EmbeddedText
3376uid 436,0
3377commentText (CommentText
3378uid 437,0
3379ps "CenterOffsetStrategy"
3380shape (Rectangle
3381uid 438,0
3382va (VaSet
3383vasetType 1
3384fg "65535,65535,65535"
3385lineColor "0,0,32768"
3386lineWidth 2
3387)
3388xt "50000,45000,60000,49000"
3389)
3390oxt "0,0,18000,5000"
3391text (MLText
3392uid 439,0
3393va (VaSet
3394)
3395xt "50200,45200,58200,49200"
3396st "
3397-- eb_ID 1: hard-wired IDs
3398board_id <= \"0101\";
3399crate_id <= \"01\";
3400
3401"
3402tm "HdlTextMgr"
3403wrapOption 3
3404visibleHeight 4000
3405visibleWidth 10000
3406)
3407)
3408)
3409]
3410shape (Rectangle
3411uid 431,0
3412va (VaSet
3413vasetType 1
3414fg "65535,65535,37120"
3415lineColor "0,0,32768"
3416lineWidth 2
3417)
3418xt "50000,40000,58000,45000"
3419)
3420oxt "0,0,8000,10000"
3421ttg (MlTextGroup
3422uid 432,0
3423ps "CenterOffsetStrategy"
3424stg "VerticalLayoutStrategy"
3425textVec [
3426*97 (Text
3427uid 433,0
3428va (VaSet
3429font "Arial,8,1"
3430)
3431xt "51150,41000,57350,42000"
3432st "eb_mainTB_ID"
3433blo "51150,41800"
3434tm "HdlTextNameMgr"
3435)
3436*98 (Text
3437uid 434,0
3438va (VaSet
3439font "Arial,8,1"
3440)
3441xt "51150,42000,51950,43000"
3442st "1"
3443blo "51150,42800"
3444tm "HdlTextNumberMgr"
3445)
3446]
3447)
3448viewicon (ZoomableIcon
3449uid 435,0
3450sl 0
3451va (VaSet
3452vasetType 1
3453fg "49152,49152,49152"
3454)
3455xt "50250,43250,51750,44750"
3456iconName "TextFile.png"
3457iconMaskName "TextFile.msk"
3458ftype 21
3459)
3460viewiconposition 0
3461)
3462*99 (Net
3463uid 440,0
3464decl (Decl
3465n "board_id"
3466t "std_logic_vector"
3467b "(3 downto 0)"
3468preAdd 0
3469posAdd 0
3470o 10
3471suid 10,0
3472)
3473declText (MLText
3474uid 441,0
3475va (VaSet
3476font "Courier New,8,0"
3477)
3478xt "-90000,45400,-58500,46200"
3479st "SIGNAL board_id              : std_logic_vector(3 downto 0)
3480"
3481)
3482)
3483*100 (Net
3484uid 448,0
3485decl (Decl
3486n "crate_id"
3487t "std_logic_vector"
3488b "(1 downto 0)"
3489o 11
3490suid 11,0
3491)
3492declText (MLText
3493uid 449,0
3494va (VaSet
3495font "Courier New,8,0"
3496)
3497xt "-90000,47800,-58500,48600"
3498st "SIGNAL crate_id              : std_logic_vector(1 downto 0)
3499"
3500)
3501)
3502*101 (SaComponent
3503uid 508,0
3504optionalChildren [
3505*102 (CptPort
3506uid 489,0
3507ps "OnEdgeStrategy"
3508shape (Triangle
3509uid 490,0
3510ro 90
3511va (VaSet
3512vasetType 1
3513fg "0,65535,0"
3514)
3515xt "29250,52625,30000,53375"
3516)
3517tg (CPTG
3518uid 491,0
3519ps "CptPortTextPlaceStrategy"
3520stg "VerticalLayoutStrategy"
3521f (Text
3522uid 492,0
3523va (VaSet
3524)
3525xt "31000,52500,32300,53500"
3526st "clk"
3527blo "31000,53300"
3528)
3529)
3530thePort (LogicalPort
3531decl (Decl
3532n "clk"
3533t "STD_LOGIC"
3534preAdd 0
3535posAdd 0
3536o 1
3537suid 1,0
3538)
3539)
3540)
3541*103 (CptPort
3542uid 493,0
3543ps "OnEdgeStrategy"
3544shape (Triangle
3545uid 494,0
3546ro 90
3547va (VaSet
3548vasetType 1
3549fg "0,65535,0"
3550)
3551xt "40000,54625,40750,55375"
3552)
3553tg (CPTG
3554uid 495,0
3555ps "CptPortTextPlaceStrategy"
3556stg "RightVerticalLayoutStrategy"
3557f (Text
3558uid 496,0
3559va (VaSet
3560)
3561xt "34200,54500,39000,55500"
3562st "data : (11:0)"
3563ju 2
3564blo "39000,55300"
3565)
3566)
3567thePort (LogicalPort
3568m 1
3569decl (Decl
3570n "data"
3571t "STD_LOGIC_VECTOR"
3572b "(11 DOWNTO 0)"
3573preAdd 0
3574posAdd 0
3575o 2
3576suid 2,0
3577)
3578)
3579)
3580*104 (CptPort
3581uid 497,0
3582ps "OnEdgeStrategy"
3583shape (Triangle
3584uid 498,0
3585ro 90
3586va (VaSet
3587vasetType 1
3588fg "0,65535,0"
3589)
3590xt "40000,52625,40750,53375"
3591)
3592tg (CPTG
3593uid 499,0
3594ps "CptPortTextPlaceStrategy"
3595stg "RightVerticalLayoutStrategy"
3596f (Text
3597uid 500,0
3598va (VaSet
3599)
3600xt "37700,52500,39000,53500"
3601st "otr"
3602ju 2
3603blo "39000,53300"
3604)
3605)
3606thePort (LogicalPort
3607m 1
3608decl (Decl
3609n "otr"
3610t "STD_LOGIC"
3611preAdd 0
3612posAdd 0
3613o 3
3614suid 3,0
3615)
3616)
3617)
3618*105 (CptPort
3619uid 501,0
3620ps "OnEdgeStrategy"
3621shape (Triangle
3622uid 502,0
3623ro 270
3624va (VaSet
3625vasetType 1
3626fg "0,65535,0"
3627)
3628xt "40000,53625,40750,54375"
3629)
3630tg (CPTG
3631uid 503,0
3632ps "CptPortTextPlaceStrategy"
3633stg "RightVerticalLayoutStrategy"
3634f (Text
3635uid 504,0
3636va (VaSet
3637)
3638xt "37400,53500,39000,54500"
3639st "oeb"
3640ju 2
3641blo "39000,54300"
3642)
3643)
3644thePort (LogicalPort
3645decl (Decl
3646n "oeb"
3647t "STD_LOGIC"
3648preAdd 0
3649posAdd 0
3650o 4
3651suid 4,0
3652)
3653)
3654)
3655]
3656shape (Rectangle
3657uid 509,0
3658va (VaSet
3659vasetType 1
3660fg "0,49152,49152"
3661lineColor "0,0,50000"
3662lineWidth 2
3663)
3664xt "30000,51000,40000,58000"
3665)
3666oxt "29000,7000,39000,17000"
3667ttg (MlTextGroup
3668uid 510,0
3669ps "CenterOffsetStrategy"
3670stg "VerticalLayoutStrategy"
3671textVec [
3672*106 (Text
3673uid 511,0
3674va (VaSet
3675font "Arial,8,1"
3676)
3677xt "30200,58000,37900,59000"
3678st "FACT_FAD_TB_lib"
3679blo "30200,58800"
3680tm "BdLibraryNameMgr"
3681)
3682*107 (Text
3683uid 512,0
3684va (VaSet
3685font "Arial,8,1"
3686)
3687xt "30200,59000,36000,60000"
3688st "adc_emulator"
3689blo "30200,59800"
3690tm "CptNameMgr"
3691)
3692*108 (Text
3693uid 513,0
3694va (VaSet
3695font "Arial,8,1"
3696)
3697xt "30200,60000,36200,61000"
3698st "I_mainTB_adc"
3699blo "30200,60800"
3700tm "InstanceNameMgr"
3701)
3702]
3703)
3704ga (GenericAssociation
3705uid 514,0
3706ps "EdgeToEdgeStrategy"
3707matrix (Matrix
3708uid 515,0
3709text (MLText
3710uid 516,0
3711va (VaSet
3712font "Courier New,8,0"
3713)
3714xt "30000,50200,65500,51000"
3715st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\"    ( string )  "
3716)
3717header ""
3718)
3719elements [
3720(GiElement
3721name "INPUT_FILE"
3722type "string"
3723value "\"../memory_files/analog_input_ch0.txt\""
3724)
3725]
3726)
3727viewicon (ZoomableIcon
3728uid 517,0
3729sl 0
3730va (VaSet
3731vasetType 1
3732fg "49152,49152,49152"
3733)
3734xt "30250,56250,31750,57750"
3735iconName "VhdlFileViewIcon.png"
3736iconMaskName "VhdlFileViewIcon.msk"
3737ftype 10
3738)
3739ordering 1
3740viewiconposition 0
3741portVis (PortSigDisplay
3742sIVOD 1
3743)
3744archFileType "UNKNOWN"
3745)
3746*109 (HdlText
3747uid 518,0
3748optionalChildren [
3749*110 (EmbeddedText
3750uid 524,0
3751commentText (CommentText
3752uid 525,0
3753ps "CenterOffsetStrategy"
3754shape (Rectangle
3755uid 526,0
3756va (VaSet
3757vasetType 1
3758fg "65535,65535,65535"
3759lineColor "0,0,32768"
3760lineWidth 2
3761)
3762xt "50000,57000,62000,67000"
3763)
3764oxt "0,0,18000,5000"
3765text (MLText
3766uid 527,0
3767va (VaSet
3768)
3769xt "50200,57200,60900,67200"
3770st "
3771-- eb_adc 2: ADC routing
3772adc_data_array(0) <= adc_data;
3773adc_data_array(1) <= adc_data;
3774adc_data_array(2) <= adc_data;
3775adc_data_array(3) <= adc_data;
3776adc_otr_array(0) <= adc_otr;
3777adc_otr_array(1) <= adc_otr;
3778adc_otr_array(2) <= adc_otr;
3779adc_otr_array(3) <= adc_otr;
3780
3781"
3782tm "HdlTextMgr"
3783wrapOption 3
3784visibleHeight 10000
3785visibleWidth 12000
3786)
3787)
3788)
3789]
3790shape (Rectangle
3791uid 519,0
3792va (VaSet
3793vasetType 1
3794fg "65535,65535,37120"
3795lineColor "0,0,32768"
3796lineWidth 2
3797)
3798xt "50000,51000,58000,57000"
3799)
3800oxt "0,0,8000,10000"
3801ttg (MlTextGroup
3802uid 520,0
3803ps "CenterOffsetStrategy"
3804stg "VerticalLayoutStrategy"
3805textVec [
3806*111 (Text
3807uid 521,0
3808va (VaSet
3809font "Arial,8,1"
3810)
3811xt "51150,52000,57850,53000"
3812st "eb_mainTB_adc"
3813blo "51150,52800"
3814tm "HdlTextNameMgr"
3815)
3816*112 (Text
3817uid 522,0
3818va (VaSet
3819font "Arial,8,1"
3820)
3821xt "51150,53000,51950,54000"
3822st "2"
3823blo "51150,53800"
3824tm "HdlTextNumberMgr"
3825)
3826]
3827)
3828viewicon (ZoomableIcon
3829uid 523,0
3830sl 0
3831va (VaSet
3832vasetType 1
3833fg "49152,49152,49152"
3834)
3835xt "50250,55250,51750,56750"
3836iconName "TextFile.png"
3837iconMaskName "TextFile.msk"
3838ftype 21
3839)
3840viewiconposition 0
3841)
3842*113 (Net
3843uid 528,0
3844decl (Decl
3845n "adc_otr_array"
3846t "std_logic_vector"
3847b "(3 DOWNTO 0)"
3848o 12
3849suid 12,0
3850)
3851declText (MLText
3852uid 529,0
3853va (VaSet
3854font "Courier New,8,0"
3855)
3856xt "-90000,42200,-58500,43000"
3857st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)
3858"
3859)
3860)
3861*114 (Net
3862uid 536,0
3863decl (Decl
3864n "adc_data_array"
3865t "adc_data_array_type"
3866o 13
3867suid 13,0
3868)
3869declText (MLText
3870uid 537,0
3871va (VaSet
3872font "Courier New,8,0"
3873)
3874xt "-90000,39800,-63000,40600"
3875st "SIGNAL adc_data_array        : adc_data_array_type
3876"
3877)
3878)
3879*115 (Net
3880uid 544,0
3881decl (Decl
3882n "adc_oeb"
3883t "std_logic"
3884preAdd 0
3885posAdd 0
3886o 14
3887suid 14,0
3888)
3889declText (MLText
3890uid 545,0
3891va (VaSet
3892font "Courier New,8,0"
3893)
3894xt "-90000,40600,-68000,41400"
3895st "SIGNAL adc_oeb               : std_logic
3896"
3897)
3898)
3899*116 (Net
3900uid 560,0
3901decl (Decl
3902n "adc_otr"
3903t "STD_LOGIC"
3904preAdd 0
3905posAdd 0
3906o 16
3907suid 16,0
3908)
3909declText (MLText
3910uid 561,0
3911va (VaSet
3912font "Courier New,8,0"
3913)
3914xt "-90000,41400,-68000,42200"
3915st "SIGNAL adc_otr               : STD_LOGIC
3916"
3917)
3918)
3919*117 (Net
3920uid 568,0
3921decl (Decl
3922n "adc_data"
3923t "std_logic_vector"
3924b "(11 DOWNTO 0)"
3925preAdd 0
3926posAdd 0
3927o 17
3928suid 17,0
3929)
3930declText (MLText
3931uid 569,0
3932va (VaSet
3933font "Courier New,8,0"
3934)
3935xt "-90000,39000,-58000,39800"
3936st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)
3937"
3938)
3939)
3940*118 (Net
3941uid 767,0
3942decl (Decl
3943n "wiz_reset"
3944t "std_logic"
3945o 21
3946suid 23,0
3947i "'1'"
3948)
3949declText (MLText
3950uid 768,0
3951va (VaSet
3952font "Courier New,8,0"
3953)
3954xt "-90000,67000,-55000,67800"
3955st "SIGNAL wiz_reset             : std_logic                    := '1'
3956"
3957)
3958)
3959*119 (Net
3960uid 775,0
3961decl (Decl
3962n "led"
3963t "std_logic_vector"
3964b "(7 DOWNTO 0)"
3965posAdd 0
3966o 22
3967suid 24,0
3968i "(OTHERS => '0')"
3969)
3970declText (MLText
3971uid 776,0
3972va (VaSet
3973font "Courier New,8,0"
3974)
3975xt "-90000,54200,-49000,55000"
3976st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
3977"
3978)
3979)
3980*120 (Net
3981uid 783,0
3982decl (Decl
3983n "wiz_cs"
3984t "std_logic"
3985o 23
3986suid 25,0
3987i "'1'"
3988)
3989declText (MLText
3990uid 784,0
3991va (VaSet
3992font "Courier New,8,0"
3993)
3994xt "-90000,63800,-55000,64600"
3995st "SIGNAL wiz_cs                : std_logic                    := '1'
3996"
3997)
3998)
3999*121 (Net
4000uid 791,0
4001decl (Decl
4002n "wiz_int"
4003t "std_logic"
4004o 24
4005suid 26,0
4006)
4007declText (MLText
4008uid 792,0
4009va (VaSet
4010font "Courier New,8,0"
4011)
4012xt "-90000,65400,-68000,66200"
4013st "SIGNAL wiz_int               : std_logic
4014"
4015)
4016)
4017*122 (Net
4018uid 799,0
4019decl (Decl
4020n "dac_cs"
4021t "std_logic"
4022o 25
4023suid 27,0
4024)
4025declText (MLText
4026uid 800,0
4027va (VaSet
4028font "Courier New,8,0"
4029)
4030xt "-90000,48600,-68000,49400"
4031st "SIGNAL dac_cs                : std_logic
4032"
4033)
4034)
4035*123 (Net
4036uid 807,0
4037decl (Decl
4038n "mosi"
4039t "std_logic"
4040o 26
4041suid 28,0
4042i "'0'"
4043)
4044declText (MLText
4045uid 808,0
4046va (VaSet
4047font "Courier New,8,0"
4048)
4049xt "-90000,55800,-55000,56600"
4050st "SIGNAL mosi                  : std_logic                    := '0'
4051"
4052)
4053)
4054*124 (Net
4055uid 815,0
4056decl (Decl
4057n "denable"
4058t "std_logic"
4059eolc "-- default domino wave off"
4060posAdd 0
4061o 27
4062suid 29,0
4063i "'0'"
4064)
4065declText (MLText
4066uid 816,0
4067va (VaSet
4068font "Courier New,8,0"
4069)
4070xt "-90000,51000,-41500,51800"
4071st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off
4072"
4073)
4074)
4075*125 (Net
4076uid 823,0
4077decl (Decl
4078n "CLK_25_PS"
4079t "std_logic"
4080o 28
4081suid 30,0
4082)
4083declText (MLText
4084uid 824,0
4085va (VaSet
4086font "Courier New,8,0"
4087)
4088xt "-90000,25400,-68000,26200"
4089st "SIGNAL CLK_25_PS             : std_logic
4090"
4091)
4092)
4093*126 (Net
4094uid 831,0
4095decl (Decl
4096n "CLK_50"
4097t "std_logic"
4098o 29
4099suid 31,0
4100)
4101declText (MLText
4102uid 832,0
4103va (VaSet
4104font "Courier New,8,0"
4105)
4106xt "-90000,26200,-68000,27000"
4107st "SIGNAL CLK_50                : std_logic
4108"
4109)
4110)
4111*127 (Net
4112uid 839,0
4113decl (Decl
4114n "drs_channel_id"
4115t "std_logic_vector"
4116b "(3 downto 0)"
4117o 30
4118suid 32,0
4119i "(others => '0')"
4120)
4121declText (MLText
4122uid 840,0
4123va (VaSet
4124font "Courier New,8,0"
4125)
4126xt "-90000,51800,-49000,52600"
4127st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')
4128"
4129)
4130)
4131*128 (Net
4132uid 847,0
4133decl (Decl
4134n "drs_dwrite"
4135t "std_logic"
4136o 31
4137suid 33,0
4138i "'1'"
4139)
4140declText (MLText
4141uid 848,0
4142va (VaSet
4143font "Courier New,8,0"
4144)
4145xt "-90000,52600,-55000,53400"
4146st "SIGNAL drs_dwrite            : std_logic                    := '1'
4147"
4148)
4149)
4150*129 (Net
4151uid 855,0
4152decl (Decl
4153n "RSRLOAD"
4154t "std_logic"
4155o 32
4156suid 34,0
4157i "'0'"
4158)
4159declText (MLText
4160uid 856,0
4161va (VaSet
4162font "Courier New,8,0"
4163)
4164xt "-90000,33400,-55000,34200"
4165st "SIGNAL RSRLOAD               : std_logic                    := '0'
4166"
4167)
4168)
4169*130 (Net
4170uid 863,0
4171decl (Decl
4172n "SRCLK"
4173t "std_logic"
4174o 33
4175suid 35,0
4176i "'0'"
4177)
4178declText (MLText
4179uid 864,0
4180va (VaSet
4181font "Courier New,8,0"
4182)
4183xt "-90000,34200,-55000,35000"
4184st "SIGNAL SRCLK                 : std_logic                    := '0'
4185"
4186)
4187)
4188*131 (Net
4189uid 871,0
4190decl (Decl
4191n "SROUT_in_0"
4192t "std_logic"
4193o 30
4194suid 36,0
4195)
4196declText (MLText
4197uid 872,0
4198va (VaSet
4199font "Courier New,8,0"
4200)
4201xt "-90000,35800,-68000,36600"
4202st "SIGNAL SROUT_in_0            : std_logic
4203"
4204)
4205)
4206*132 (Net
4207uid 879,0
4208decl (Decl
4209n "SROUT_in_1"
4210t "std_logic"
4211o 31
4212suid 37,0
4213)
4214declText (MLText
4215uid 880,0
4216va (VaSet
4217font "Courier New,8,0"
4218)
4219xt "-90000,36600,-68000,37400"
4220st "SIGNAL SROUT_in_1            : std_logic
4221"
4222)
4223)
4224*133 (Net
4225uid 887,0
4226decl (Decl
4227n "SROUT_in_2"
4228t "std_logic"
4229o 32
4230suid 38,0
4231)
4232declText (MLText
4233uid 888,0
4234va (VaSet
4235font "Courier New,8,0"
4236)
4237xt "-90000,37400,-68000,38200"
4238st "SIGNAL SROUT_in_2            : std_logic
4239"
4240)
4241)
4242*134 (Net
4243uid 895,0
4244decl (Decl
4245n "SROUT_in_3"
4246t "std_logic"
4247o 33
4248suid 39,0
4249)
4250declText (MLText
4251uid 896,0
4252va (VaSet
4253font "Courier New,8,0"
4254)
4255xt "-90000,38200,-68000,39000"
4256st "SIGNAL SROUT_in_3            : std_logic
4257"
4258)
4259)
4260*135 (Net
4261uid 1435,0
4262decl (Decl
4263n "SRIN_out"
4264t "std_logic"
4265o 34
4266suid 40,0
4267i "'0'"
4268)
4269declText (MLText
4270uid 1436,0
4271va (VaSet
4272font "Courier New,8,0"
4273)
4274xt "-90000,35000,-55000,35800"
4275st "SIGNAL SRIN_out              : std_logic                    := '0'
4276"
4277)
4278)
4279*136 (Net
4280uid 1443,0
4281decl (Decl
4282n "amber"
4283t "std_logic"
4284o 35
4285suid 41,0
4286)
4287declText (MLText
4288uid 1444,0
4289va (VaSet
4290font "Courier New,8,0"
4291)
4292xt "-90000,44600,-68000,45400"
4293st "SIGNAL amber                 : std_logic
4294"
4295)
4296)
4297*137 (Net
4298uid 1451,0
4299decl (Decl
4300n "red"
4301t "std_logic"
4302o 36
4303suid 42,0
4304)
4305declText (MLText
4306uid 1452,0
4307va (VaSet
4308font "Courier New,8,0"
4309)
4310xt "-90000,57400,-68000,58200"
4311st "SIGNAL red                   : std_logic
4312"
4313)
4314)
4315*138 (Net
4316uid 1459,0
4317decl (Decl
4318n "green"
4319t "std_logic"
4320o 37
4321suid 43,0
4322)
4323declText (MLText
4324uid 1460,0
4325va (VaSet
4326font "Courier New,8,0"
4327)
4328xt "-90000,53400,-68000,54200"
4329st "SIGNAL green                 : std_logic
4330"
4331)
4332)
4333*139 (Net
4334uid 1467,0
4335decl (Decl
4336n "counter_result"
4337t "std_logic_vector"
4338b "(11 DOWNTO 0)"
4339o 38
4340suid 44,0
4341)
4342declText (MLText
4343uid 1468,0
4344va (VaSet
4345font "Courier New,8,0"
4346)
4347xt "-90000,47000,-58000,47800"
4348st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)
4349"
4350)
4351)
4352*140 (Net
4353uid 1475,0
4354decl (Decl
4355n "alarm_refclk_too_low"
4356t "std_logic"
4357posAdd 0
4358o 39
4359suid 45,0
4360)
4361declText (MLText
4362uid 1476,0
4363va (VaSet
4364font "Courier New,8,0"
4365)
4366xt "-90000,43800,-68000,44600"
4367st "SIGNAL alarm_refclk_too_low  : std_logic
4368"
4369)
4370)
4371*141 (Net
4372uid 1483,0
4373decl (Decl
4374n "alarm_refclk_too_high"
4375t "std_logic"
4376o 40
4377suid 46,0
4378)
4379declText (MLText
4380uid 1484,0
4381va (VaSet
4382font "Courier New,8,0"
4383)
4384xt "-90000,43000,-68000,43800"
4385st "SIGNAL alarm_refclk_too_high : std_logic
4386"
4387)
4388)
4389*142 (HdlText
4390uid 1491,0
4391optionalChildren [
4392*143 (EmbeddedText
4393uid 1497,0
4394commentText (CommentText
4395uid 1498,0
4396ps "CenterOffsetStrategy"
4397shape (Rectangle
4398uid 1499,0
4399va (VaSet
4400vasetType 1
4401fg "65535,65535,65535"
4402lineColor "0,0,32768"
4403lineWidth 2
4404)
4405xt "27000,72000,41000,77000"
4406)
4407oxt "0,0,18000,5000"
4408text (MLText
4409uid 1500,0
4410va (VaSet
4411)
4412xt "27200,72200,40200,77200"
4413st "
4414
4415D_T_in(1 downto 0) <= \"00\";
4416plllock_in(3 downto 0) <= \"1111\";
4417SROUT_in_0 <= '1';
4418SROUT_in_1 <= '0';
4419SROUT_in_2 <= '1';
4420SROUT_in_3 <= '0';
4421
4422"
4423tm "HdlTextMgr"
4424wrapOption 3
4425visibleHeight 5000
4426visibleWidth 14000
4427)
4428)
4429)
4430]
4431shape (Rectangle
4432uid 1492,0
4433va (VaSet
4434vasetType 1
4435fg "65535,65535,37120"
4436lineColor "0,0,32768"
4437lineWidth 2
4438)
4439xt "27000,69000,35000,72000"
4440)
4441oxt "0,0,8000,10000"
4442ttg (MlTextGroup
4443uid 1493,0
4444ps "CenterOffsetStrategy"
4445stg "VerticalLayoutStrategy"
4446textVec [
4447*144 (Text
4448uid 1494,0
4449va (VaSet
4450font "Arial,8,1"
4451)
4452xt "28150,69000,35250,70000"
4453st "eb_mainTB_adc1"
4454blo "28150,69800"
4455tm "HdlTextNameMgr"
4456)
4457*145 (Text
4458uid 1495,0
4459va (VaSet
4460font "Arial,8,1"
4461)
4462xt "28150,70000,28950,71000"
4463st "3"
4464blo "28150,70800"
4465tm "HdlTextNumberMgr"
4466)
4467]
4468)
4469viewicon (ZoomableIcon
4470uid 1496,0
4471sl 0
4472va (VaSet
4473vasetType 1
4474fg "49152,49152,49152"
4475)
4476xt "27250,70250,28750,71750"
4477iconName "TextFile.png"
4478iconMaskName "TextFile.msk"
4479ftype 21
4480)
4481viewiconposition 0
4482)
4483*146 (Net
4484uid 1501,0
4485decl (Decl
4486n "D_T_in"
4487t "std_logic_vector"
4488b "(1 DOWNTO 0)"
4489o 41
4490suid 47,0
4491)
4492declText (MLText
4493uid 1502,0
4494va (VaSet
4495font "Courier New,8,0"
4496)
4497xt "-90000,28600,-58500,29400"
4498st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)
4499"
4500)
4501)
4502*147 (SaComponent
4503uid 1509,0
4504optionalChildren [
4505*148 (CptPort
4506uid 1519,0
4507ps "OnEdgeStrategy"
4508shape (Triangle
4509uid 1520,0
4510ro 90
4511va (VaSet
4512vasetType 1
4513fg "0,65535,0"
4514)
4515xt "66000,78625,66750,79375"
4516)
4517tg (CPTG
4518uid 1521,0
4519ps "CptPortTextPlaceStrategy"
4520stg "RightVerticalLayoutStrategy"
4521f (Text
4522uid 1522,0
4523va (VaSet
4524)
4525xt "63700,78500,65000,79500"
4526st "clk"
4527ju 2
4528blo "65000,79300"
4529)
4530)
4531thePort (LogicalPort
4532m 1
4533decl (Decl
4534n "clk"
4535t "STD_LOGIC"
4536o 1
4537i "'0'"
4538)
4539)
4540)
4541*149 (CptPort
4542uid 1523,0
4543ps "OnEdgeStrategy"
4544shape (Triangle
4545uid 1524,0
4546ro 90
4547va (VaSet
4548vasetType 1
4549fg "0,65535,0"
4550)
4551xt "66000,79625,66750,80375"
4552)
4553tg (CPTG
4554uid 1525,0
4555ps "CptPortTextPlaceStrategy"
4556stg "RightVerticalLayoutStrategy"
4557f (Text
4558uid 1526,0
4559va (VaSet
4560)
4561xt "63700,79500,65000,80500"
4562st "rst"
4563ju 2
4564blo "65000,80300"
4565)
4566)
4567thePort (LogicalPort
4568m 1
4569decl (Decl
4570n "rst"
4571t "STD_LOGIC"
4572o 2
4573i "'0'"
4574)
4575)
4576)
4577]
4578shape (Rectangle
4579uid 1510,0
4580va (VaSet
4581vasetType 1
4582fg "0,49152,49152"
4583lineColor "0,0,50000"
4584lineWidth 2
4585)
4586xt "55000,77000,66000,82000"
4587)
4588oxt "0,0,8000,10000"
4589ttg (MlTextGroup
4590uid 1511,0
4591ps "CenterOffsetStrategy"
4592stg "VerticalLayoutStrategy"
4593textVec [
4594*150 (Text
4595uid 1512,0
4596va (VaSet
4597font "Arial,8,1"
4598)
4599xt "56150,78000,63850,79000"
4600st "FACT_FAD_TB_lib"
4601blo "56150,78800"
4602tm "BdLibraryNameMgr"
4603)
4604*151 (Text
4605uid 1513,0
4606va (VaSet
4607font "Arial,8,1"
4608)
4609xt "56150,79000,62850,80000"
4610st "clock_generator"
4611blo "56150,79800"
4612tm "CptNameMgr"
4613)
4614*152 (Text
4615uid 1514,0
4616va (VaSet
4617font "Arial,8,1"
4618)
4619xt "56150,80000,63150,81000"
4620st "I_mainTB_clock1"
4621blo "56150,80800"
4622tm "InstanceNameMgr"
4623)
4624]
4625)
4626ga (GenericAssociation
4627uid 1515,0
4628ps "EdgeToEdgeStrategy"
4629matrix (Matrix
4630uid 1516,0
4631text (MLText
4632uid 1517,0
4633va (VaSet
4634font "Courier New,8,0"
4635)
4636xt "55000,82400,73000,84000"
4637st "clock_period = 1 us    ( time ) 
4638reset_time   = 1 us    ( time )  "
4639)
4640header ""
4641)
4642elements [
4643(GiElement
4644name "clock_period"
4645type "time"
4646value "1 us"
4647)
4648(GiElement
4649name "reset_time"
4650type "time"
4651value "1 us"
4652)
4653]
4654)
4655viewicon (ZoomableIcon
4656uid 1518,0
4657sl 0
4658va (VaSet
4659vasetType 1
4660fg "49152,49152,49152"
4661)
4662xt "55250,80250,56750,81750"
4663iconName "VhdlFileViewIcon.png"
4664iconMaskName "VhdlFileViewIcon.msk"
4665ftype 10
4666)
4667ordering 1
4668viewiconposition 0
4669portVis (PortSigDisplay
4670)
4671archFileType "UNKNOWN"
4672)
4673*153 (Net
4674uid 1559,0
4675decl (Decl
4676n "plllock_in"
4677t "std_logic_vector"
4678b "(3 DOWNTO 0)"
4679eolc "-- high level, if dominowave is running and DRS PLL locked"
4680o 43
4681suid 49,0
4682)
4683declText (MLText
4684uid 1560,0
4685va (VaSet
4686font "Courier New,8,0"
4687)
4688xt "-90000,56600,-29000,57400"
4689st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
4690"
4691)
4692)
4693*154 (Net
4694uid 1682,0
4695lang 2
4696decl (Decl
4697n "ADC_CLK"
4698t "std_logic"
4699o 44
4700suid 50,0
4701)
4702declText (MLText
4703uid 1683,0
4704va (VaSet
4705font "Courier New,8,0"
4706)
4707xt "-90000,24600,-68000,25400"
4708st "SIGNAL ADC_CLK               : std_logic
4709"
4710)
4711)
4712*155 (Net
4713uid 2001,0
4714decl (Decl
4715n "REF_CLK"
4716t "STD_LOGIC"
4717o 42
4718suid 51,0
4719i "'0'"
4720)
4721declText (MLText
4722uid 2002,0
4723va (VaSet
4724font "Courier New,8,0"
4725)
4726xt "-90000,32600,-55000,33400"
4727st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'
4728"
4729)
4730)
4731*156 (SaComponent
4732uid 2336,0
4733optionalChildren [
4734*157 (CptPort
4735uid 2315,0
4736ps "OnEdgeStrategy"
4737shape (Triangle
4738uid 2316,0
4739ro 90
4740va (VaSet
4741vasetType 1
4742fg "0,65535,0"
4743)
4744xt "122250,20625,123000,21375"
4745)
4746tg (CPTG
4747uid 2317,0
4748ps "CptPortTextPlaceStrategy"
4749stg "VerticalLayoutStrategy"
4750f (Text
4751uid 2318,0
4752va (VaSet
4753)
4754xt "124000,20500,129100,21500"
4755st "addr : (9:0)"
4756blo "124000,21300"
4757)
4758)
4759thePort (LogicalPort
4760decl (Decl
4761n "addr"
4762t "std_logic_vector"
4763b "(9 DOWNTO 0)"
4764preAdd 0
4765posAdd 0
4766o 2
4767suid 1,0
4768)
4769)
4770)
4771*158 (CptPort
4772uid 2319,0
4773ps "OnEdgeStrategy"
4774shape (Diamond
4775uid 2320,0
4776ro 270
4777va (VaSet
4778vasetType 1
4779fg "0,65535,0"
4780)
4781xt "122250,21625,123000,22375"
4782)
4783tg (CPTG
4784uid 2321,0
4785ps "CptPortTextPlaceStrategy"
4786stg "VerticalLayoutStrategy"
4787f (Text
4788uid 2322,0
4789va (VaSet
4790)
4791xt "124000,21500,129400,22500"
4792st "data : (15:0)"
4793blo "124000,22300"
4794)
4795)
4796thePort (LogicalPort
4797m 2
4798decl (Decl
4799n "data"
4800t "std_logic_vector"
4801b "(15 DOWNTO 0)"
4802preAdd 0
4803posAdd 0
4804o 3
4805suid 2,0
4806)
4807)
4808)
4809*159 (CptPort
4810uid 2323,0
4811ps "OnEdgeStrategy"
4812shape (Triangle
4813uid 2324,0
4814ro 90
4815va (VaSet
4816vasetType 1
4817fg "0,65535,0"
4818)
4819xt "122250,24625,123000,25375"
4820)
4821tg (CPTG
4822uid 2325,0
4823ps "CptPortTextPlaceStrategy"
4824stg "VerticalLayoutStrategy"
4825f (Text
4826uid 2326,0
4827va (VaSet
4828)
4829xt "124000,24500,125300,25500"
4830st "rd"
4831blo "124000,25300"
4832)
4833)
4834thePort (LogicalPort
4835decl (Decl
4836n "rd"
4837t "std_logic"
4838preAdd 0
4839posAdd 0
4840o 4
4841suid 3,0
4842)
4843)
4844)
4845*160 (CptPort
4846uid 2327,0
4847ps "OnEdgeStrategy"
4848shape (Triangle
4849uid 2328,0
4850ro 90
4851va (VaSet
4852vasetType 1
4853fg "0,65535,0"
4854)
4855xt "122250,25625,123000,26375"
4856)
4857tg (CPTG
4858uid 2329,0
4859ps "CptPortTextPlaceStrategy"
4860stg "VerticalLayoutStrategy"
4861f (Text
4862uid 2330,0
4863va (VaSet
4864)
4865xt "124000,25500,125400,26500"
4866st "wr"
4867blo "124000,26300"
4868)
4869)
4870thePort (LogicalPort
4871decl (Decl
4872n "wr"
4873t "std_logic"
4874preAdd 0
4875posAdd 0
4876o 6
4877suid 4,0
4878)
4879)
4880)
4881*161 (CptPort
4882uid 2331,0
4883ps "OnEdgeStrategy"
4884shape (Triangle
4885uid 2332,0
4886ro 270
4887va (VaSet
4888vasetType 1
4889fg "0,65535,0"
4890)
4891xt "122250,26625,123000,27375"
4892)
4893tg (CPTG
4894uid 2333,0
4895ps "CptPortTextPlaceStrategy"
4896stg "VerticalLayoutStrategy"
4897f (Text
4898uid 2334,0
4899va (VaSet
4900)
4901xt "124000,26500,125400,27500"
4902st "int"
4903blo "124000,27300"
4904)
4905)
4906thePort (LogicalPort
4907m 1
4908decl (Decl
4909n "int"
4910t "std_logic"
4911o 1
4912suid 5,0
4913i "'1'"
4914)
4915)
4916)
4917*162 (CptPort
4918uid 2548,0
4919ps "OnEdgeStrategy"
4920shape (Triangle
4921uid 2549,0
4922ro 90
4923va (VaSet
4924vasetType 1
4925fg "0,65535,0"
4926)
4927xt "122250,27625,123000,28375"
4928)
4929tg (CPTG
4930uid 2550,0
4931ps "CptPortTextPlaceStrategy"
4932stg "VerticalLayoutStrategy"
4933f (Text
4934uid 2551,0
4935va (VaSet
4936)
4937xt "124000,27500,125200,28500"
4938st "cs"
4939blo "124000,28300"
4940)
4941)
4942thePort (LogicalPort
4943decl (Decl
4944n "cs"
4945t "std_logic"
4946o 5
4947suid 6,0
4948)
4949)
4950)
4951]
4952shape (Rectangle
4953uid 2337,0
4954va (VaSet
4955vasetType 1
4956fg "0,49152,49152"
4957lineColor "0,0,50000"
4958lineWidth 2
4959)
4960xt "123000,19000,133000,31000"
4961)
4962oxt "29000,0,39000,12000"
4963ttg (MlTextGroup
4964uid 2338,0
4965ps "CenterOffsetStrategy"
4966stg "VerticalLayoutStrategy"
4967textVec [
4968*163 (Text
4969uid 2339,0
4970va (VaSet
4971font "Arial,8,1"
4972)
4973xt "123200,31000,130900,32000"
4974st "FACT_FAD_TB_lib"
4975blo "123200,31800"
4976tm "BdLibraryNameMgr"
4977)
4978*164 (Text
4979uid 2340,0
4980va (VaSet
4981font "Arial,8,1"
4982)
4983xt "123200,32000,129800,33000"
4984st "w5300_emulator"
4985blo "123200,32800"
4986tm "CptNameMgr"
4987)
4988*165 (Text
4989uid 2341,0
4990va (VaSet
4991font "Arial,8,1"
4992)
4993xt "123200,33000,130000,34000"
4994st "I_mainTB_w5300"
4995blo "123200,33800"
4996tm "InstanceNameMgr"
4997)
4998]
4999)
5000ga (GenericAssociation
5001uid 2342,0
5002ps "EdgeToEdgeStrategy"
5003matrix (Matrix
5004uid 2343,0
5005text (MLText
5006uid 2344,0
5007va (VaSet
5008font "Courier New,8,0"
5009)
5010xt "123000,18000,123000,18000"
5011)
5012header ""
5013)
5014elements [
5015]
5016)
5017viewicon (ZoomableIcon
5018uid 2345,0
5019sl 0
5020va (VaSet
5021vasetType 1
5022fg "49152,49152,49152"
5023)
5024xt "123250,29250,124750,30750"
5025iconName "VhdlFileViewIcon.png"
5026iconMaskName "VhdlFileViewIcon.msk"
5027ftype 10
5028)
5029ordering 1
5030viewiconposition 0
5031portVis (PortSigDisplay
5032)
5033archFileType "UNKNOWN"
5034)
5035*166 (Net
5036uid 2705,0
5037decl (Decl
5038n "debug_data_ram_empty"
5039t "std_logic"
5040o 45
5041suid 53,0
5042)
5043declText (MLText
5044uid 2706,0
5045va (VaSet
5046font "Courier New,8,0"
5047)
5048xt "-90000,49400,-68000,50200"
5049st "SIGNAL debug_data_ram_empty  : std_logic
5050"
5051)
5052)
5053*167 (Net
5054uid 2713,0
5055decl (Decl
5056n "debug_data_valid"
5057t "std_logic"
5058o 46
5059suid 54,0
5060)
5061declText (MLText
5062uid 2714,0
5063va (VaSet
5064font "Courier New,8,0"
5065)
5066xt "-90000,50200,-68000,51000"
5067st "SIGNAL debug_data_valid      : std_logic
5068"
5069)
5070)
5071*168 (Net
5072uid 2721,0
5073decl (Decl
5074n "DG_state"
5075t "std_logic_vector"
5076b "(7 downto 0)"
5077prec "-- for debugging"
5078preAdd 0
5079o 47
5080suid 55,0
5081)
5082declText (MLText
5083uid 2722,0
5084va (VaSet
5085font "Courier New,8,0"
5086)
5087xt "-90000,27000,-58500,28600"
5088st "-- for debugging
5089SIGNAL DG_state              : std_logic_vector(7 downto 0)
5090"
5091)
5092)
5093*169 (Net
5094uid 2729,0
5095decl (Decl
5096n "FTM_RS485_rx_en"
5097t "std_logic"
5098o 48
5099suid 56,0
5100)
5101declText (MLText
5102uid 2730,0
5103va (VaSet
5104font "Courier New,8,0"
5105)
5106xt "-90000,30200,-68000,31000"
5107st "SIGNAL FTM_RS485_rx_en       : std_logic
5108"
5109)
5110)
5111*170 (Net
5112uid 2737,0
5113decl (Decl
5114n "FTM_RS485_tx_d"
5115t "std_logic"
5116o 49
5117suid 57,0
5118)
5119declText (MLText
5120uid 2738,0
5121va (VaSet
5122font "Courier New,8,0"
5123)
5124xt "-90000,31000,-68000,31800"
5125st "SIGNAL FTM_RS485_tx_d        : std_logic
5126"
5127)
5128)
5129*171 (Net
5130uid 2745,0
5131decl (Decl
5132n "FTM_RS485_tx_en"
5133t "std_logic"
5134o 50
5135suid 58,0
5136)
5137declText (MLText
5138uid 2746,0
5139va (VaSet
5140font "Courier New,8,0"
5141)
5142xt "-90000,31800,-68000,32600"
5143st "SIGNAL FTM_RS485_tx_en       : std_logic
5144"
5145)
5146)
5147*172 (Net
5148uid 2753,0
5149lang 2
5150decl (Decl
5151n "mem_manager_state"
5152t "std_logic_vector"
5153b "(3 DOWNTO 0)"
5154eolc "-- state is encoded here ... useful for debugging."
5155posAdd 0
5156o 51
5157suid 59,0
5158)
5159declText (MLText
5160uid 2754,0
5161va (VaSet
5162font "Courier New,8,0"
5163)
5164xt "-90000,55000,-33000,55800"
5165st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
5166"
5167)
5168)
5169*173 (Net
5170uid 2761,0
5171decl (Decl
5172n "trigger_veto"
5173t "std_logic"
5174o 52
5175suid 60,0
5176i "'1'"
5177)
5178declText (MLText
5179uid 2762,0
5180va (VaSet
5181font "Courier New,8,0"
5182)
5183xt "-90000,61400,-55000,62200"
5184st "SIGNAL trigger_veto          : std_logic                    := '1'
5185"
5186)
5187)
5188*174 (Net
5189uid 2769,0
5190decl (Decl
5191n "w5300_state"
5192t "std_logic_vector"
5193b "(7 DOWNTO 0)"
5194eolc "-- state is encoded here ... useful for debugging."
5195posAdd 0
5196o 53
5197suid 61,0
5198)
5199declText (MLText
5200uid 2770,0
5201va (VaSet
5202font "Courier New,8,0"
5203)
5204xt "-90000,62200,-33000,63000"
5205st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
5206"
5207)
5208)
5209*175 (Net
5210uid 2777,0
5211decl (Decl
5212n "FTM_RS485_rx_d"
5213t "std_logic"
5214o 54
5215suid 62,0
5216)
5217declText (MLText
5218uid 2778,0
5219va (VaSet
5220font "Courier New,8,0"
5221)
5222xt "-90000,29400,-68000,30200"
5223st "SIGNAL FTM_RS485_rx_d        : std_logic
5224"
5225)
5226)
5227*176 (Wire
5228uid 286,0
5229shape (OrthoPolyLine
5230uid 287,0
5231va (VaSet
5232vasetType 3
5233)
5234xt "58750,21000,80250,21000"
5235pts [
5236"58750,21000"
5237"80250,21000"
5238]
5239)
5240start &69
5241end &27
5242sat 32
5243eat 32
5244st 0
5245sf 1
5246si 0
5247tg (WTG
5248uid 288,0
5249ps "ConnStartEndStrategy"
5250stg "STSignalDisplayStrategy"
5251f (Text
5252uid 289,0
5253va (VaSet
5254)
5255xt "71000,20000,72300,21000"
5256st "clk"
5257blo "71000,20800"
5258tm "WireNameMgr"
5259)
5260)
5261on &74
5262)
5263*177 (Wire
5264uid 318,0
5265shape (OrthoPolyLine
5266uid 319,0
5267va (VaSet
5268vasetType 3
5269lineWidth 2
5270)
5271xt "109750,21000,122250,21000"
5272pts [
5273"109750,21000"
5274"122250,21000"
5275]
5276)
5277start &19
5278end &157
5279sat 32
5280eat 32
5281sty 1
5282st 0
5283sf 1
5284si 0
5285tg (WTG
5286uid 320,0
5287ps "ConnStartEndStrategy"
5288stg "STSignalDisplayStrategy"
5289f (Text
5290uid 321,0
5291va (VaSet
5292)
5293xt "111000,20000,117000,21000"
5294st "wiz_addr : (9:0)"
5295blo "111000,20800"
5296tm "WireNameMgr"
5297)
5298)
5299on &75
5300)
5301*178 (Wire
5302uid 324,0
5303shape (OrthoPolyLine
5304uid 325,0
5305va (VaSet
5306vasetType 3
5307lineWidth 2
5308)
5309xt "109750,22000,122250,22000"
5310pts [
5311"109750,22000"
5312"122250,22000"
5313]
5314)
5315start &20
5316end &158
5317sat 32
5318eat 32
5319sty 1
5320st 0
5321sf 1
5322si 0
5323tg (WTG
5324uid 326,0
5325ps "ConnStartEndStrategy"
5326stg "STSignalDisplayStrategy"
5327f (Text
5328uid 327,0
5329va (VaSet
5330)
5331xt "111000,21000,117300,22000"
5332st "wiz_data : (15:0)"
5333blo "111000,21800"
5334tm "WireNameMgr"
5335)
5336)
5337on &76
5338)
5339*179 (Wire
5340uid 330,0
5341shape (OrthoPolyLine
5342uid 331,0
5343va (VaSet
5344vasetType 3
5345)
5346xt "109750,25000,122250,25000"
5347pts [
5348"109750,25000"
5349"122250,25000"
5350]
5351)
5352start &23
5353end &159
5354sat 32
5355eat 32
5356st 0
5357sf 1
5358si 0
5359tg (WTG
5360uid 332,0
5361ps "ConnStartEndStrategy"
5362stg "STSignalDisplayStrategy"
5363f (Text
5364uid 333,0
5365va (VaSet
5366)
5367xt "111000,24000,113600,25000"
5368st "wiz_rd"
5369blo "111000,24800"
5370tm "WireNameMgr"
5371)
5372)
5373on &77
5374)
5375*180 (Wire
5376uid 336,0
5377shape (OrthoPolyLine
5378uid 337,0
5379va (VaSet
5380vasetType 3
5381)
5382xt "109750,26000,122250,26000"
5383pts [
5384"109750,26000"
5385"122250,26000"
5386]
5387)
5388start &22
5389end &160
5390sat 32
5391eat 32
5392st 0
5393sf 1
5394si 0
5395tg (WTG
5396uid 338,0
5397ps "ConnStartEndStrategy"
5398stg "STSignalDisplayStrategy"
5399f (Text
5400uid 339,0
5401va (VaSet
5402)
5403xt "111000,25000,113700,26000"
5404st "wiz_wr"
5405blo "111000,25800"
5406tm "WireNameMgr"
5407)
5408)
5409on &78
5410)
5411*181 (Wire
5412uid 374,0
5413shape (OrthoPolyLine
5414uid 375,0
5415va (VaSet
5416vasetType 3
5417lineWidth 2
5418)
5419xt "109750,42000,122250,48000"
5420pts [
5421"109750,42000"
5422"120000,42000"
5423"120000,48000"
5424"122250,48000"
5425]
5426)
5427start &41
5428end &82
5429sat 32
5430eat 32
5431sty 1
5432st 0
5433sf 1
5434si 0
5435tg (WTG
5436uid 376,0
5437ps "ConnStartEndStrategy"
5438stg "STSignalDisplayStrategy"
5439f (Text
5440uid 377,0
5441va (VaSet
5442)
5443xt "111000,41000,117500,42000"
5444st "sensor_cs : (3:0)"
5445blo "111000,41800"
5446tm "WireNameMgr"
5447)
5448)
5449on &86
5450)
5451*182 (Wire
5452uid 380,0
5453shape (OrthoPolyLine
5454uid 381,0
5455va (VaSet
5456vasetType 3
5457)
5458xt "109750,51000,122250,51000"
5459pts [
5460"109750,51000"
5461"122250,51000"
5462]
5463)
5464start &38
5465end &80
5466sat 32
5467eat 32
5468st 0
5469sf 1
5470si 0
5471tg (WTG
5472uid 382,0
5473ps "ConnStartEndStrategy"
5474stg "STSignalDisplayStrategy"
5475f (Text
5476uid 383,0
5477va (VaSet
5478)
5479xt "111000,50000,112700,51000"
5480st "sclk"
5481blo "111000,50800"
5482tm "WireNameMgr"
5483)
5484)
5485on &87
5486)
5487*183 (Wire
5488uid 386,0
5489shape (OrthoPolyLine
5490uid 387,0
5491va (VaSet
5492vasetType 3
5493)
5494xt "109750,52000,122250,52000"
5495pts [
5496"109750,52000"
5497"122250,52000"
5498]
5499)
5500start &39
5501end &81
5502sat 32
5503eat 32
5504st 0
5505sf 1
5506si 0
5507tg (WTG
5508uid 388,0
5509ps "ConnStartEndStrategy"
5510stg "STSignalDisplayStrategy"
5511f (Text
5512uid 389,0
5513va (VaSet
5514)
5515xt "111000,51000,112400,52000"
5516st "sio"
5517blo "111000,51800"
5518tm "WireNameMgr"
5519)
5520)
5521on &88
5522)
5523*184 (Wire
5524uid 426,0
5525shape (OrthoPolyLine
5526uid 427,0
5527va (VaSet
5528vasetType 3
5529)
5530xt "58750,32000,80250,32000"
5531pts [
5532"58750,32000"
5533"80250,32000"
5534]
5535)
5536start &90
5537end &15
5538sat 32
5539eat 32
5540st 0
5541sf 1
5542tg (WTG
5543uid 428,0
5544ps "ConnStartEndStrategy"
5545stg "STSignalDisplayStrategy"
5546f (Text
5547uid 429,0
5548va (VaSet
5549)
5550xt "71000,31000,73800,32000"
5551st "trigger"
5552blo "71000,31800"
5553tm "WireNameMgr"
5554)
5555)
5556on &94
5557)
5558*185 (Wire
5559uid 442,0
5560shape (OrthoPolyLine
5561uid 443,0
5562va (VaSet
5563vasetType 3
5564lineWidth 2
5565)
5566xt "58000,34000,80250,42000"
5567pts [
5568"80250,34000"
5569"64000,34000"
5570"64000,42000"
5571"58000,42000"
5572]
5573)
5574start &17
5575end &95
5576sat 32
5577eat 2
5578sty 1
5579st 0
5580sf 1
5581si 0
5582tg (WTG
5583uid 446,0
5584ps "ConnStartEndStrategy"
5585stg "STSignalDisplayStrategy"
5586f (Text
5587uid 447,0
5588va (VaSet
5589)
5590xt "71000,33000,76900,34000"
5591st "board_id : (3:0)"
5592blo "71000,33800"
5593tm "WireNameMgr"
5594)
5595)
5596on &99
5597)
5598*186 (Wire
5599uid 450,0
5600shape (OrthoPolyLine
5601uid 451,0
5602va (VaSet
5603vasetType 3
5604lineWidth 2
5605)
5606xt "58000,35000,80250,43000"
5607pts [
5608"80250,35000"
5609"65000,35000"
5610"65000,43000"
5611"58000,43000"
5612]
5613)
5614start &18
5615end &95
5616sat 32
5617eat 2
5618sty 1
5619st 0
5620sf 1
5621si 0
5622tg (WTG
5623uid 454,0
5624ps "ConnStartEndStrategy"
5625stg "STSignalDisplayStrategy"
5626f (Text
5627uid 455,0
5628va (VaSet
5629)
5630xt "71000,34000,76700,35000"
5631st "crate_id : (1:0)"
5632blo "71000,34800"
5633tm "WireNameMgr"
5634)
5635)
5636on &100
5637)
5638*187 (Wire
5639uid 530,0
5640shape (OrthoPolyLine
5641uid 531,0
5642va (VaSet
5643vasetType 3
5644lineWidth 2
5645)
5646xt "58000,42000,80250,53000"
5647pts [
5648"80250,42000"
5649"68000,42000"
5650"68000,53000"
5651"58000,53000"
5652]
5653)
5654start &28
5655end &109
5656sat 32
5657eat 2
5658sty 1
5659st 0
5660sf 1
5661si 0
5662tg (WTG
5663uid 534,0
5664ps "ConnStartEndStrategy"
5665stg "STSignalDisplayStrategy"
5666f (Text
5667uid 535,0
5668va (VaSet
5669)
5670xt "71000,41000,79000,42000"
5671st "adc_otr_array : (3:0)"
5672blo "71000,41800"
5673tm "WireNameMgr"
5674)
5675)
5676on &113
5677)
5678*188 (Wire
5679uid 538,0
5680shape (OrthoPolyLine
5681uid 539,0
5682va (VaSet
5683vasetType 3
5684lineWidth 2
5685)
5686xt "58000,48000,80250,55000"
5687pts [
5688"80250,48000"
5689"70000,48000"
5690"70000,55000"
5691"58000,55000"
5692]
5693)
5694start &29
5695end &109
5696sat 32
5697eat 2
5698sty 1
5699st 0
5700sf 1
5701si 0
5702tg (WTG
5703uid 542,0
5704ps "ConnStartEndStrategy"
5705stg "STSignalDisplayStrategy"
5706f (Text
5707uid 543,0
5708va (VaSet
5709)
5710xt "71000,47000,76900,48000"
5711st "adc_data_array"
5712blo "71000,47800"
5713tm "WireNameMgr"
5714)
5715)
5716on &114
5717)
5718*189 (Wire
5719uid 546,0
5720shape (OrthoPolyLine
5721uid 547,0
5722va (VaSet
5723vasetType 3
5724)
5725xt "58000,43000,80250,54000"
5726pts [
5727"80250,43000"
5728"69000,43000"
5729"69000,54000"
5730"58000,54000"
5731]
5732)
5733start &16
5734end &109
5735sat 32
5736eat 1
5737st 0
5738sf 1
5739si 0
5740tg (WTG
5741uid 550,0
5742ps "ConnStartEndStrategy"
5743stg "STSignalDisplayStrategy"
5744f (Text
5745uid 551,0
5746va (VaSet
5747)
5748xt "71000,42000,74200,43000"
5749st "adc_oeb"
5750blo "71000,42800"
5751tm "WireNameMgr"
5752)
5753)
5754on &115
5755)
5756*190 (Wire
5757uid 554,0
5758shape (OrthoPolyLine
5759uid 555,0
5760va (VaSet
5761vasetType 3
5762)
5763xt "40750,54000,50000,54000"
5764pts [
5765"50000,54000"
5766"40750,54000"
5767]
5768)
5769start &109
5770end &105
5771sat 2
5772eat 32
5773st 0
5774sf 1
5775tg (WTG
5776uid 558,0
5777ps "ConnStartEndStrategy"
5778stg "STSignalDisplayStrategy"
5779f (Text
5780uid 559,0
5781va (VaSet
5782)
5783xt "42000,53000,45200,54000"
5784st "adc_oeb"
5785blo "42000,53800"
5786tm "WireNameMgr"
5787)
5788)
5789on &115
5790)
5791*191 (Wire
5792uid 562,0
5793shape (OrthoPolyLine
5794uid 563,0
5795va (VaSet
5796vasetType 3
5797)
5798xt "40750,53000,50000,53000"
5799pts [
5800"40750,53000"
5801"50000,53000"
5802]
5803)
5804start &104
5805end &109
5806sat 32
5807eat 1
5808st 0
5809sf 1
5810tg (WTG
5811uid 566,0
5812ps "ConnStartEndStrategy"
5813stg "STSignalDisplayStrategy"
5814f (Text
5815uid 567,0
5816va (VaSet
5817)
5818xt "42000,52000,44900,53000"
5819st "adc_otr"
5820blo "42000,52800"
5821tm "WireNameMgr"
5822)
5823)
5824on &116
5825)
5826*192 (Wire
5827uid 570,0
5828shape (OrthoPolyLine
5829uid 571,0
5830va (VaSet
5831vasetType 3
5832lineWidth 2
5833)
5834xt "40750,55000,50000,55000"
5835pts [
5836"40750,55000"
5837"50000,55000"
5838]
5839)
5840start &103
5841end &109
5842sat 32
5843eat 1
5844sty 1
5845st 0
5846sf 1
5847tg (WTG
5848uid 574,0
5849ps "ConnStartEndStrategy"
5850stg "STSignalDisplayStrategy"
5851f (Text
5852uid 575,0
5853va (VaSet
5854)
5855xt "42000,54000,48400,55000"
5856st "adc_data : (11:0)"
5857blo "42000,54800"
5858tm "WireNameMgr"
5859)
5860)
5861on &117
5862)
5863*193 (Wire
5864uid 578,0
5865shape (OrthoPolyLine
5866uid 579,0
5867va (VaSet
5868vasetType 3
5869)
5870xt "24000,53000,29250,53000"
5871pts [
5872"29250,53000"
5873"24000,53000"
5874]
5875)
5876start &102
5877sat 32
5878eat 16
5879st 0
5880sf 1
5881tg (WTG
5882uid 582,0
5883ps "ConnStartEndStrategy"
5884stg "STSignalDisplayStrategy"
5885f (Text
5886uid 583,0
5887va (VaSet
5888)
5889xt "25000,52000,29000,53000"
5890st "ADC_CLK"
5891blo "25000,52800"
5892tm "WireNameMgr"
5893)
5894)
5895on &154
5896)
5897*194 (Wire
5898uid 769,0
5899shape (OrthoPolyLine
5900uid 770,0
5901va (VaSet
5902vasetType 3
5903)
5904xt "109750,24000,116000,24000"
5905pts [
5906"109750,24000"
5907"116000,24000"
5908]
5909)
5910start &13
5911sat 32
5912eat 16
5913st 0
5914sf 1
5915si 0
5916tg (WTG
5917uid 773,0
5918ps "ConnStartEndStrategy"
5919stg "STSignalDisplayStrategy"
5920f (Text
5921uid 774,0
5922va (VaSet
5923)
5924xt "111000,23000,114600,24000"
5925st "wiz_reset"
5926blo "111000,23800"
5927tm "WireNameMgr"
5928)
5929)
5930on &118
5931)
5932*195 (Wire
5933uid 777,0
5934shape (OrthoPolyLine
5935uid 778,0
5936va (VaSet
5937vasetType 3
5938lineWidth 2
5939)
5940xt "109750,70000,116000,70000"
5941pts [
5942"109750,70000"
5943"116000,70000"
5944]
5945)
5946start &14
5947sat 32
5948eat 16
5949sty 1
5950st 0
5951sf 1
5952si 0
5953tg (WTG
5954uid 781,0
5955ps "ConnStartEndStrategy"
5956stg "STSignalDisplayStrategy"
5957f (Text
5958uid 782,0
5959va (VaSet
5960)
5961xt "111000,69000,115000,70000"
5962st "led : (7:0)"
5963blo "111000,69800"
5964tm "WireNameMgr"
5965)
5966)
5967on &119
5968)
5969*196 (Wire
5970uid 785,0
5971shape (OrthoPolyLine
5972uid 786,0
5973va (VaSet
5974vasetType 3
5975)
5976xt "109750,28000,122250,28000"
5977pts [
5978"109750,28000"
5979"122250,28000"
5980]
5981)
5982start &21
5983end &162
5984sat 32
5985eat 32
5986st 0
5987sf 1
5988si 0
5989tg (WTG
5990uid 789,0
5991ps "ConnStartEndStrategy"
5992stg "STSignalDisplayStrategy"
5993f (Text
5994uid 790,0
5995va (VaSet
5996)
5997xt "111000,27000,113700,28000"
5998st "wiz_cs"
5999blo "111000,27800"
6000tm "WireNameMgr"
6001)
6002)
6003on &120
6004)
6005*197 (Wire
6006uid 793,0
6007shape (OrthoPolyLine
6008uid 794,0
6009va (VaSet
6010vasetType 3
6011)
6012xt "109750,27000,122250,27000"
6013pts [
6014"122250,27000"
6015"109750,27000"
6016]
6017)
6018start &161
6019end &24
6020sat 32
6021eat 32
6022st 0
6023sf 1
6024si 0
6025tg (WTG
6026uid 797,0
6027ps "ConnStartEndStrategy"
6028stg "STSignalDisplayStrategy"
6029f (Text
6030uid 798,0
6031va (VaSet
6032)
6033xt "111000,26000,113700,27000"
6034st "wiz_int"
6035blo "111000,26800"
6036tm "WireNameMgr"
6037)
6038)
6039on &121
6040)
6041*198 (Wire
6042uid 801,0
6043shape (OrthoPolyLine
6044uid 802,0
6045va (VaSet
6046vasetType 3
6047)
6048xt "109750,40000,116000,40000"
6049pts [
6050"109750,40000"
6051"116000,40000"
6052]
6053)
6054start &40
6055sat 32
6056eat 16
6057st 0
6058sf 1
6059si 0
6060tg (WTG
6061uid 805,0
6062ps "ConnStartEndStrategy"
6063stg "STSignalDisplayStrategy"
6064f (Text
6065uid 806,0
6066va (VaSet
6067)
6068xt "111000,39000,113800,40000"
6069st "dac_cs"
6070blo "111000,39800"
6071tm "WireNameMgr"
6072)
6073)
6074on &122
6075)
6076*199 (Wire
6077uid 809,0
6078shape (OrthoPolyLine
6079uid 810,0
6080va (VaSet
6081vasetType 3
6082)
6083xt "109750,53000,116000,53000"
6084pts [
6085"109750,53000"
6086"116000,53000"
6087]
6088)
6089start &42
6090sat 32
6091eat 16
6092st 0
6093sf 1
6094si 0
6095tg (WTG
6096uid 813,0
6097ps "ConnStartEndStrategy"
6098stg "STSignalDisplayStrategy"
6099f (Text
6100uid 814,0
6101va (VaSet
6102)
6103xt "111000,52000,113000,53000"
6104st "mosi"
6105blo "111000,52800"
6106tm "WireNameMgr"
6107)
6108)
6109on &123
6110)
6111*200 (Wire
6112uid 817,0
6113shape (OrthoPolyLine
6114uid 818,0
6115va (VaSet
6116vasetType 3
6117)
6118xt "70000,66000,80250,66000"
6119pts [
6120"80250,66000"
6121"70000,66000"
6122]
6123)
6124start &43
6125sat 32
6126eat 16
6127st 0
6128sf 1
6129si 0
6130tg (WTG
6131uid 821,0
6132ps "ConnStartEndStrategy"
6133stg "STSignalDisplayStrategy"
6134f (Text
6135uid 822,0
6136va (VaSet
6137)
6138xt "71000,65000,74000,66000"
6139st "denable"
6140blo "71000,65800"
6141tm "WireNameMgr"
6142)
6143)
6144on &124
6145)
6146*201 (Wire
6147uid 825,0
6148shape (OrthoPolyLine
6149uid 826,0
6150va (VaSet
6151vasetType 3
6152)
6153xt "70000,23000,80250,23000"
6154pts [
6155"80250,23000"
6156"70000,23000"
6157]
6158)
6159start &25
6160sat 32
6161eat 16
6162st 0
6163sf 1
6164si 0
6165tg (WTG
6166uid 829,0
6167ps "ConnStartEndStrategy"
6168stg "STSignalDisplayStrategy"
6169f (Text
6170uid 830,0
6171va (VaSet
6172)
6173xt "71000,22000,75500,23000"
6174st "CLK_25_PS"
6175blo "71000,22800"
6176tm "WireNameMgr"
6177)
6178)
6179on &125
6180)
6181*202 (Wire
6182uid 833,0
6183shape (OrthoPolyLine
6184uid 834,0
6185va (VaSet
6186vasetType 3
6187)
6188xt "70000,22000,80250,22000"
6189pts [
6190"80250,22000"
6191"70000,22000"
6192]
6193)
6194start &26
6195sat 32
6196eat 16
6197st 0
6198sf 1
6199si 0
6200tg (WTG
6201uid 837,0
6202ps "ConnStartEndStrategy"
6203stg "STSignalDisplayStrategy"
6204f (Text
6205uid 838,0
6206va (VaSet
6207)
6208xt "71000,21000,74100,22000"
6209st "CLK_50"
6210blo "71000,21800"
6211tm "WireNameMgr"
6212)
6213)
6214on &126
6215)
6216*203 (Wire
6217uid 841,0
6218shape (OrthoPolyLine
6219uid 842,0
6220va (VaSet
6221vasetType 3
6222lineWidth 2
6223)
6224xt "70000,62000,80250,62000"
6225pts [
6226"80250,62000"
6227"70000,62000"
6228]
6229)
6230start &30
6231sat 32
6232eat 16
6233sty 1
6234st 0
6235sf 1
6236si 0
6237tg (WTG
6238uid 845,0
6239ps "ConnStartEndStrategy"
6240stg "STSignalDisplayStrategy"
6241f (Text
6242uid 846,0
6243va (VaSet
6244)
6245xt "71000,61000,79500,62000"
6246st "drs_channel_id : (3:0)"
6247blo "71000,61800"
6248tm "WireNameMgr"
6249)
6250)
6251on &127
6252)
6253*204 (Wire
6254uid 849,0
6255shape (OrthoPolyLine
6256uid 850,0
6257va (VaSet
6258vasetType 3
6259)
6260xt "70000,67000,80250,67000"
6261pts [
6262"80250,67000"
6263"70000,67000"
6264]
6265)
6266start &31
6267ss 0
6268sat 32
6269eat 16
6270st 0
6271sf 1
6272si 0
6273tg (WTG
6274uid 853,0
6275ps "ConnStartEndStrategy"
6276stg "STSignalDisplayStrategy"
6277f (Text
6278uid 854,0
6279va (VaSet
6280)
6281xt "71000,66000,75300,67000"
6282st "drs_dwrite"
6283blo "71000,66800"
6284tm "WireNameMgr"
6285)
6286)
6287on &128
6288)
6289*205 (Wire
6290uid 857,0
6291shape (OrthoPolyLine
6292uid 858,0
6293va (VaSet
6294vasetType 3
6295)
6296xt "70000,64000,80250,64000"
6297pts [
6298"80250,64000"
6299"70000,64000"
6300]
6301)
6302start &36
6303sat 32
6304eat 16
6305st 0
6306sf 1
6307si 0
6308tg (WTG
6309uid 861,0
6310ps "ConnStartEndStrategy"
6311stg "STSignalDisplayStrategy"
6312f (Text
6313uid 862,0
6314va (VaSet
6315)
6316xt "71000,63000,75200,64000"
6317st "RSRLOAD"
6318blo "71000,63800"
6319tm "WireNameMgr"
6320)
6321)
6322on &129
6323)
6324*206 (Wire
6325uid 865,0
6326shape (OrthoPolyLine
6327uid 866,0
6328va (VaSet
6329vasetType 3
6330)
6331xt "70000,65000,80250,65000"
6332pts [
6333"80250,65000"
6334"70000,65000"
6335]
6336)
6337start &37
6338sat 32
6339eat 16
6340st 0
6341sf 1
6342si 0
6343tg (WTG
6344uid 869,0
6345ps "ConnStartEndStrategy"
6346stg "STSignalDisplayStrategy"
6347f (Text
6348uid 870,0
6349va (VaSet
6350)
6351xt "71000,64000,74000,65000"
6352st "SRCLK"
6353blo "71000,64800"
6354tm "WireNameMgr"
6355)
6356)
6357on &130
6358)
6359*207 (Wire
6360uid 873,0
6361shape (OrthoPolyLine
6362uid 874,0
6363va (VaSet
6364vasetType 3
6365)
6366xt "70000,58000,80250,58000"
6367pts [
6368"70000,58000"
6369"80250,58000"
6370]
6371)
6372end &32
6373sat 16
6374eat 32
6375st 0
6376sf 1
6377si 0
6378tg (WTG
6379uid 877,0
6380ps "ConnStartEndStrategy"
6381stg "STSignalDisplayStrategy"
6382f (Text
6383uid 878,0
6384va (VaSet
6385)
6386xt "71000,57000,76400,58000"
6387st "SROUT_in_0"
6388blo "71000,57800"
6389tm "WireNameMgr"
6390)
6391)
6392on &131
6393)
6394*208 (Wire
6395uid 881,0
6396shape (OrthoPolyLine
6397uid 882,0
6398va (VaSet
6399vasetType 3
6400)
6401xt "70000,59000,80250,59000"
6402pts [
6403"70000,59000"
6404"80250,59000"
6405]
6406)
6407end &33
6408sat 16
6409eat 32
6410st 0
6411sf 1
6412si 0
6413tg (WTG
6414uid 885,0
6415ps "ConnStartEndStrategy"
6416stg "STSignalDisplayStrategy"
6417f (Text
6418uid 886,0
6419va (VaSet
6420)
6421xt "71000,58000,76400,59000"
6422st "SROUT_in_1"
6423blo "71000,58800"
6424tm "WireNameMgr"
6425)
6426)
6427on &132
6428)
6429*209 (Wire
6430uid 889,0
6431shape (OrthoPolyLine
6432uid 890,0
6433va (VaSet
6434vasetType 3
6435)
6436xt "70000,60000,80250,60000"
6437pts [
6438"70000,60000"
6439"80250,60000"
6440]
6441)
6442end &34
6443sat 16
6444eat 32
6445st 0
6446sf 1
6447si 0
6448tg (WTG
6449uid 893,0
6450ps "ConnStartEndStrategy"
6451stg "STSignalDisplayStrategy"
6452f (Text
6453uid 894,0
6454va (VaSet
6455)
6456xt "71000,59000,76400,60000"
6457st "SROUT_in_2"
6458blo "71000,59800"
6459tm "WireNameMgr"
6460)
6461)
6462on &133
6463)
6464*210 (Wire
6465uid 897,0
6466shape (OrthoPolyLine
6467uid 898,0
6468va (VaSet
6469vasetType 3
6470)
6471xt "70000,61000,80250,61000"
6472pts [
6473"70000,61000"
6474"80250,61000"
6475]
6476)
6477end &35
6478sat 16
6479eat 32
6480st 0
6481sf 1
6482si 0
6483tg (WTG
6484uid 901,0
6485ps "ConnStartEndStrategy"
6486stg "STSignalDisplayStrategy"
6487f (Text
6488uid 902,0
6489va (VaSet
6490)
6491xt "71000,60000,76400,61000"
6492st "SROUT_in_3"
6493blo "71000,60800"
6494tm "WireNameMgr"
6495)
6496)
6497on &134
6498)
6499*211 (Wire
6500uid 1437,0
6501shape (OrthoPolyLine
6502uid 1438,0
6503va (VaSet
6504vasetType 3
6505)
6506xt "73000,72000,80250,72000"
6507pts [
6508"80250,72000"
6509"73000,72000"
6510]
6511)
6512start &53
6513sat 32
6514eat 16
6515st 0
6516sf 1
6517si 0
6518tg (WTG
6519uid 1441,0
6520ps "ConnStartEndStrategy"
6521stg "STSignalDisplayStrategy"
6522f (Text
6523uid 1442,0
6524va (VaSet
6525)
6526xt "76000,72000,79700,73000"
6527st "SRIN_out"
6528blo "76000,72800"
6529tm "WireNameMgr"
6530)
6531)
6532on &135
6533)
6534*212 (Wire
6535uid 1445,0
6536shape (OrthoPolyLine
6537uid 1446,0
6538va (VaSet
6539vasetType 3
6540)
6541xt "109750,80000,115000,80000"
6542pts [
6543"109750,80000"
6544"115000,80000"
6545]
6546)
6547start &46
6548sat 32
6549eat 16
6550st 0
6551sf 1
6552si 0
6553tg (WTG
6554uid 1449,0
6555ps "ConnStartEndStrategy"
6556stg "STSignalDisplayStrategy"
6557f (Text
6558uid 1450,0
6559va (VaSet
6560)
6561xt "111000,79000,113500,80000"
6562st "amber"
6563blo "111000,79800"
6564tm "WireNameMgr"
6565)
6566)
6567on &136
6568)
6569*213 (Wire
6570uid 1453,0
6571shape (OrthoPolyLine
6572uid 1454,0
6573va (VaSet
6574vasetType 3
6575)
6576xt "109750,79000,114000,79000"
6577pts [
6578"109750,79000"
6579"114000,79000"
6580]
6581)
6582start &52
6583sat 32
6584eat 16
6585st 0
6586sf 1
6587si 0
6588tg (WTG
6589uid 1457,0
6590ps "ConnStartEndStrategy"
6591stg "STSignalDisplayStrategy"
6592f (Text
6593uid 1458,0
6594va (VaSet
6595)
6596xt "111000,78000,112500,79000"
6597st "red"
6598blo "111000,78800"
6599tm "WireNameMgr"
6600)
6601)
6602on &137
6603)
6604*214 (Wire
6605uid 1461,0
6606shape (OrthoPolyLine
6607uid 1462,0
6608va (VaSet
6609vasetType 3
6610)
6611xt "109750,78000,114000,78000"
6612pts [
6613"109750,78000"
6614"114000,78000"
6615]
6616)
6617start &50
6618sat 32
6619eat 16
6620st 0
6621sf 1
6622si 0
6623tg (WTG
6624uid 1465,0
6625ps "ConnStartEndStrategy"
6626stg "STSignalDisplayStrategy"
6627f (Text
6628uid 1466,0
6629va (VaSet
6630)
6631xt "111000,77000,113400,78000"
6632st "green"
6633blo "111000,77800"
6634tm "WireNameMgr"
6635)
6636)
6637on &138
6638)
6639*215 (Wire
6640uid 1469,0
6641shape (OrthoPolyLine
6642uid 1470,0
6643va (VaSet
6644vasetType 3
6645lineWidth 2
6646)
6647xt "109750,77000,121000,77000"
6648pts [
6649"109750,77000"
6650"121000,77000"
6651]
6652)
6653start &47
6654sat 32
6655eat 16
6656sty 1
6657st 0
6658sf 1
6659si 0
6660tg (WTG
6661uid 1473,0
6662ps "ConnStartEndStrategy"
6663stg "STSignalDisplayStrategy"
6664f (Text
6665uid 1474,0
6666va (VaSet
6667)
6668xt "111000,76000,119600,77000"
6669st "counter_result : (11:0)"
6670blo "111000,76800"
6671tm "WireNameMgr"
6672)
6673)
6674on &139
6675)
6676*216 (Wire
6677uid 1477,0
6678shape (OrthoPolyLine
6679uid 1478,0
6680va (VaSet
6681vasetType 3
6682)
6683xt "109750,75000,120000,75000"
6684pts [
6685"109750,75000"
6686"120000,75000"
6687]
6688)
6689start &45
6690sat 32
6691eat 16
6692st 0
6693sf 1
6694si 0
6695tg (WTG
6696uid 1481,0
6697ps "ConnStartEndStrategy"
6698stg "STSignalDisplayStrategy"
6699f (Text
6700uid 1482,0
6701va (VaSet
6702)
6703xt "111000,74000,119200,75000"
6704st "alarm_refclk_too_low"
6705blo "111000,74800"
6706tm "WireNameMgr"
6707)
6708)
6709on &140
6710)
6711*217 (Wire
6712uid 1485,0
6713shape (OrthoPolyLine
6714uid 1486,0
6715va (VaSet
6716vasetType 3
6717)
6718xt "109750,74000,121000,74000"
6719pts [
6720"109750,74000"
6721"121000,74000"
6722]
6723)
6724start &44
6725sat 32
6726eat 16
6727st 0
6728sf 1
6729si 0
6730tg (WTG
6731uid 1489,0
6732ps "ConnStartEndStrategy"
6733stg "STSignalDisplayStrategy"
6734f (Text
6735uid 1490,0
6736va (VaSet
6737)
6738xt "111000,73000,119600,74000"
6739st "alarm_refclk_too_high"
6740blo "111000,73800"
6741tm "WireNameMgr"
6742)
6743)
6744on &141
6745)
6746*218 (Wire
6747uid 1503,0
6748shape (OrthoPolyLine
6749uid 1504,0
6750va (VaSet
6751vasetType 3
6752lineWidth 2
6753)
6754xt "73000,75000,80250,75000"
6755pts [
6756"73000,75000"
6757"80250,75000"
6758]
6759)
6760end &48
6761sat 16
6762eat 32
6763sty 1
6764st 0
6765sf 1
6766si 0
6767tg (WTG
6768uid 1507,0
6769ps "ConnStartEndStrategy"
6770stg "STSignalDisplayStrategy"
6771f (Text
6772uid 1508,0
6773va (VaSet
6774)
6775xt "74000,74000,79500,75000"
6776st "D_T_in : (1:0)"
6777blo "74000,74800"
6778tm "WireNameMgr"
6779)
6780)
6781on &146
6782)
6783*219 (Wire
6784uid 1529,0
6785shape (OrthoPolyLine
6786uid 1530,0
6787va (VaSet
6788vasetType 3
6789)
6790xt "66750,76000,80250,79000"
6791pts [
6792"66750,79000"
6793"70000,79000"
6794"70000,76000"
6795"80250,76000"
6796]
6797)
6798start &148
6799end &49
6800sat 32
6801eat 32
6802st 0
6803sf 1
6804si 0
6805tg (WTG
6806uid 1531,0
6807ps "ConnStartEndStrategy"
6808stg "STSignalDisplayStrategy"
6809f (Text
6810uid 1532,0
6811va (VaSet
6812)
6813xt "68750,78000,72650,79000"
6814st "REF_CLK"
6815blo "68750,78800"
6816tm "WireNameMgr"
6817)
6818)
6819on &155
6820)
6821*220 (Wire
6822uid 1533,0
6823shape (OrthoPolyLine
6824uid 1534,0
6825va (VaSet
6826vasetType 3
6827)
6828xt "35000,70000,45000,70000"
6829pts [
6830"35000,70000"
6831"45000,70000"
6832]
6833)
6834start &142
6835sat 2
6836eat 16
6837st 0
6838sf 1
6839si 0
6840tg (WTG
6841uid 1539,0
6842ps "ConnStartEndStrategy"
6843stg "STSignalDisplayStrategy"
6844f (Text
6845uid 1540,0
6846va (VaSet
6847)
6848xt "37000,69000,42500,70000"
6849st "D_T_in : (1:0)"
6850blo "37000,69800"
6851tm "WireNameMgr"
6852)
6853)
6854on &146
6855)
6856*221 (Wire
6857uid 1561,0
6858shape (OrthoPolyLine
6859uid 1562,0
6860va (VaSet
6861vasetType 3
6862lineWidth 2
6863)
6864xt "72000,77000,80250,77000"
6865pts [
6866"72000,77000"
6867"80250,77000"
6868]
6869)
6870end &51
6871sat 16
6872eat 32
6873sty 1
6874st 0
6875sf 1
6876si 0
6877tg (WTG
6878uid 1565,0
6879ps "ConnStartEndStrategy"
6880stg "STSignalDisplayStrategy"
6881f (Text
6882uid 1566,0
6883va (VaSet
6884)
6885xt "73000,76000,79100,77000"
6886st "plllock_in : (3:0)"
6887blo "73000,76800"
6888tm "WireNameMgr"
6889)
6890)
6891on &153
6892)
6893*222 (Wire
6894uid 1567,0
6895shape (OrthoPolyLine
6896uid 1568,0
6897va (VaSet
6898vasetType 3
6899)
6900xt "35000,71000,45000,71000"
6901pts [
6902"35000,71000"
6903"45000,71000"
6904]
6905)
6906start &142
6907sat 2
6908eat 16
6909st 0
6910sf 1
6911si 0
6912tg (WTG
6913uid 1573,0
6914ps "ConnStartEndStrategy"
6915stg "STSignalDisplayStrategy"
6916f (Text
6917uid 1574,0
6918va (VaSet
6919)
6920xt "37000,70000,43100,71000"
6921st "plllock_in : (3:0)"
6922blo "37000,70800"
6923tm "WireNameMgr"
6924)
6925)
6926on &153
6927)
6928*223 (Wire
6929uid 1684,0
6930shape (OrthoPolyLine
6931uid 1685,0
6932va (VaSet
6933vasetType 3
6934)
6935xt "70000,24000,80250,24000"
6936pts [
6937"80250,24000"
6938"70000,24000"
6939]
6940)
6941start &54
6942sat 32
6943eat 16
6944st 0
6945sf 1
6946si 0
6947tg (WTG
6948uid 1688,0
6949ps "ConnStartEndStrategy"
6950stg "STSignalDisplayStrategy"
6951f (Text
6952uid 1689,0
6953va (VaSet
6954)
6955xt "71000,23000,75000,24000"
6956st "ADC_CLK"
6957blo "71000,23800"
6958tm "WireNameMgr"
6959)
6960)
6961on &154
6962)
6963*224 (Wire
6964uid 2707,0
6965shape (OrthoPolyLine
6966uid 2708,0
6967va (VaSet
6968vasetType 3
6969)
6970xt "109750,81000,122000,81000"
6971pts [
6972"109750,81000"
6973"122000,81000"
6974]
6975)
6976start &55
6977sat 32
6978eat 16
6979st 0
6980sf 1
6981si 0
6982tg (WTG
6983uid 2711,0
6984ps "ConnStartEndStrategy"
6985stg "STSignalDisplayStrategy"
6986f (Text
6987uid 2712,0
6988va (VaSet
6989)
6990xt "111000,80000,121400,81000"
6991st "debug_data_ram_empty"
6992blo "111000,80800"
6993tm "WireNameMgr"
6994)
6995)
6996on &166
6997)
6998*225 (Wire
6999uid 2715,0
7000shape (OrthoPolyLine
7001uid 2716,0
7002va (VaSet
7003vasetType 3
7004)
7005xt "109750,82000,120000,82000"
7006pts [
7007"109750,82000"
7008"120000,82000"
7009]
7010)
7011start &56
7012sat 32
7013eat 16
7014st 0
7015sf 1
7016si 0
7017tg (WTG
7018uid 2719,0
7019ps "ConnStartEndStrategy"
7020stg "STSignalDisplayStrategy"
7021f (Text
7022uid 2720,0
7023va (VaSet
7024)
7025xt "111000,81000,118500,82000"
7026st "debug_data_valid"
7027blo "111000,81800"
7028tm "WireNameMgr"
7029)
7030)
7031on &167
7032)
7033*226 (Wire
7034uid 2723,0
7035shape (OrthoPolyLine
7036uid 2724,0
7037va (VaSet
7038vasetType 3
7039lineWidth 2
7040)
7041xt "109750,83000,119000,83000"
7042pts [
7043"109750,83000"
7044"119000,83000"
7045]
7046)
7047start &57
7048sat 32
7049eat 16
7050sty 1
7051st 0
7052sf 1
7053si 0
7054tg (WTG
7055uid 2727,0
7056ps "ConnStartEndStrategy"
7057stg "STSignalDisplayStrategy"
7058f (Text
7059uid 2728,0
7060va (VaSet
7061)
7062xt "111000,82000,117900,83000"
7063st "DG_state : (7:0)"
7064blo "111000,82800"
7065tm "WireNameMgr"
7066)
7067)
7068on &168
7069)
7070*227 (Wire
7071uid 2731,0
7072shape (OrthoPolyLine
7073uid 2732,0
7074va (VaSet
7075vasetType 3
7076)
7077xt "109750,84000,120000,84000"
7078pts [
7079"109750,84000"
7080"120000,84000"
7081]
7082)
7083start &59
7084sat 32
7085eat 16
7086st 0
7087sf 1
7088si 0
7089tg (WTG
7090uid 2735,0
7091ps "ConnStartEndStrategy"
7092stg "STSignalDisplayStrategy"
7093f (Text
7094uid 2736,0
7095va (VaSet
7096)
7097xt "111000,83000,119400,84000"
7098st "FTM_RS485_rx_en"
7099blo "111000,83800"
7100tm "WireNameMgr"
7101)
7102)
7103on &169
7104)
7105*228 (Wire
7106uid 2739,0
7107shape (OrthoPolyLine
7108uid 2740,0
7109va (VaSet
7110vasetType 3
7111)
7112xt "109750,85000,120000,85000"
7113pts [
7114"109750,85000"
7115"120000,85000"
7116]
7117)
7118start &60
7119sat 32
7120eat 16
7121st 0
7122sf 1
7123si 0
7124tg (WTG
7125uid 2743,0
7126ps "ConnStartEndStrategy"
7127stg "STSignalDisplayStrategy"
7128f (Text
7129uid 2744,0
7130va (VaSet
7131)
7132xt "111000,84000,119100,85000"
7133st "FTM_RS485_tx_d"
7134blo "111000,84800"
7135tm "WireNameMgr"
7136)
7137)
7138on &170
7139)
7140*229 (Wire
7141uid 2747,0
7142shape (OrthoPolyLine
7143uid 2748,0
7144va (VaSet
7145vasetType 3
7146)
7147xt "109750,86000,120000,86000"
7148pts [
7149"109750,86000"
7150"120000,86000"
7151]
7152)
7153start &61
7154sat 32
7155eat 16
7156st 0
7157sf 1
7158si 0
7159tg (WTG
7160uid 2751,0
7161ps "ConnStartEndStrategy"
7162stg "STSignalDisplayStrategy"
7163f (Text
7164uid 2752,0
7165va (VaSet
7166)
7167xt "111000,85000,119400,86000"
7168st "FTM_RS485_tx_en"
7169blo "111000,85800"
7170tm "WireNameMgr"
7171)
7172)
7173on &171
7174)
7175*230 (Wire
7176uid 2755,0
7177shape (OrthoPolyLine
7178uid 2756,0
7179va (VaSet
7180vasetType 3
7181lineWidth 2
7182)
7183xt "109750,87000,123000,87000"
7184pts [
7185"109750,87000"
7186"123000,87000"
7187]
7188)
7189start &62
7190sat 32
7191eat 16
7192sty 1
7193st 0
7194sf 1
7195si 0
7196tg (WTG
7197uid 2759,0
7198ps "ConnStartEndStrategy"
7199stg "STSignalDisplayStrategy"
7200f (Text
7201uid 2760,0
7202va (VaSet
7203)
7204xt "111000,86000,122400,87000"
7205st "mem_manager_state : (3:0)"
7206blo "111000,86800"
7207tm "WireNameMgr"
7208)
7209)
7210on &172
7211)
7212*231 (Wire
7213uid 2763,0
7214shape (OrthoPolyLine
7215uid 2764,0
7216va (VaSet
7217vasetType 3
7218)
7219xt "109750,88000,118000,88000"
7220pts [
7221"109750,88000"
7222"118000,88000"
7223]
7224)
7225start &63
7226sat 32
7227eat 16
7228st 0
7229sf 1
7230si 0
7231tg (WTG
7232uid 2767,0
7233ps "ConnStartEndStrategy"
7234stg "STSignalDisplayStrategy"
7235f (Text
7236uid 2768,0
7237va (VaSet
7238)
7239xt "111000,87000,116600,88000"
7240st "trigger_veto"
7241blo "111000,87800"
7242tm "WireNameMgr"
7243)
7244)
7245on &173
7246)
7247*232 (Wire
7248uid 2771,0
7249shape (OrthoPolyLine
7250uid 2772,0
7251va (VaSet
7252vasetType 3
7253lineWidth 2
7254)
7255xt "109750,89000,120000,89000"
7256pts [
7257"109750,89000"
7258"120000,89000"
7259]
7260)
7261start &64
7262sat 32
7263eat 16
7264sty 1
7265st 0
7266sf 1
7267si 0
7268tg (WTG
7269uid 2775,0
7270ps "ConnStartEndStrategy"
7271stg "STSignalDisplayStrategy"
7272f (Text
7273uid 2776,0
7274va (VaSet
7275)
7276xt "111000,88000,119400,89000"
7277st "w5300_state : (7:0)"
7278blo "111000,88800"
7279tm "WireNameMgr"
7280)
7281)
7282on &174
7283)
7284*233 (Wire
7285uid 2779,0
7286shape (OrthoPolyLine
7287uid 2780,0
7288va (VaSet
7289vasetType 3
7290)
7291xt "74000,78000,80250,82000"
7292pts [
7293"74000,82000"
7294"80250,78000"
7295]
7296)
7297end &58
7298sat 16
7299eat 32
7300st 0
7301sf 1
7302si 0
7303tg (WTG
7304uid 2783,0
7305ps "ConnStartEndStrategy"
7306stg "STSignalDisplayStrategy"
7307f (Text
7308uid 2784,0
7309va (VaSet
7310)
7311xt "73000,80000,81100,81000"
7312st "FTM_RS485_rx_d"
7313blo "73000,80800"
7314tm "WireNameMgr"
7315)
7316)
7317on &175
7318)
7319]
7320bg "65535,65535,65535"
7321grid (Grid
7322origin "0,0"
7323isVisible 1
7324isActive 1
7325xSpacing 1000
7326xySpacing 1000
7327xShown 1
7328yShown 1
7329color "26368,26368,26368"
7330)
7331packageList *234 (PackageList
7332uid 41,0
7333stg "VerticalLayoutStrategy"
7334textVec [
7335*235 (Text
7336uid 42,0
7337va (VaSet
7338font "arial,8,1"
7339)
7340xt "-87000,0,-81600,1000"
7341st "Package List"
7342blo "-87000,800"
7343)
7344*236 (MLText
7345uid 43,0
7346va (VaSet
7347)
7348xt "-87000,1000,-70900,11000"
7349st "LIBRARY ieee;
7350USE ieee.std_logic_1164.all;
7351USE ieee.std_logic_arith.all;
7352USE ieee.std_logic_unsigned.all;
7353
7354LIBRARY FACT_FAD_lib;
7355USE FACT_FAD_lib.fad_definitions.all;
7356USE ieee.std_logic_textio.all;
7357LIBRARY std;
7358USE std.textio.all;"
7359tm "PackageList"
7360)
7361]
7362)
7363compDirBlock (MlTextGroup
7364uid 44,0
7365stg "VerticalLayoutStrategy"
7366textVec [
7367*237 (Text
7368uid 45,0
7369va (VaSet
7370isHidden 1
7371font "Arial,8,1"
7372)
7373xt "20000,0,28100,1000"
7374st "Compiler Directives"
7375blo "20000,800"
7376)
7377*238 (Text
7378uid 46,0
7379va (VaSet
7380isHidden 1
7381font "Arial,8,1"
7382)
7383xt "20000,1000,29600,2000"
7384st "Pre-module directives:"
7385blo "20000,1800"
7386)
7387*239 (MLText
7388uid 47,0
7389va (VaSet
7390isHidden 1
7391)
7392xt "20000,2000,28200,4000"
7393st "`resetall
7394`timescale 1ns/10ps"
7395tm "BdCompilerDirectivesTextMgr"
7396)
7397*240 (Text
7398uid 48,0
7399va (VaSet
7400isHidden 1
7401font "Arial,8,1"
7402)
7403xt "20000,4000,30100,5000"
7404st "Post-module directives:"
7405blo "20000,4800"
7406)
7407*241 (MLText
7408uid 49,0
7409va (VaSet
7410isHidden 1
7411)
7412xt "20000,0,20000,0"
7413tm "BdCompilerDirectivesTextMgr"
7414)
7415*242 (Text
7416uid 50,0
7417va (VaSet
7418isHidden 1
7419font "Arial,8,1"
7420)
7421xt "20000,5000,29900,6000"
7422st "End-module directives:"
7423blo "20000,5800"
7424)
7425*243 (MLText
7426uid 51,0
7427va (VaSet
7428isHidden 1
7429)
7430xt "20000,6000,20000,6000"
7431tm "BdCompilerDirectivesTextMgr"
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8373)
8374)
8375thePort (LogicalPort
8376m 3
8377decl (Decl
8378n "Port"
8379t ""
8380o 0
8381)
8382)
8383)
8384defaultDeclText (MLText
8385va (VaSet
8386font "Courier New,8,0"
8387)
8388)
8389archDeclarativeBlock (BdArchDeclBlock
8390uid 1,0
8391stg "BdArchDeclBlockLS"
8392declLabel (Text
8393uid 2,0
8394va (VaSet
8395font "Arial,8,1"
8396)
8397xt "-92000,21600,-86600,22600"
8398st "Declarations"
8399blo "-92000,22400"
8400)
8401portLabel (Text
8402uid 3,0
8403va (VaSet
8404font "Arial,8,1"
8405)
8406xt "-92000,22600,-89300,23600"
8407st "Ports:"
8408blo "-92000,23400"
8409)
8410preUserLabel (Text
8411uid 4,0
8412va (VaSet
8413isHidden 1
8414font "Arial,8,1"
8415)
8416xt "-92000,21600,-88200,22600"
8417st "Pre User:"
8418blo "-92000,22400"
8419)
8420preUserText (MLText
8421uid 5,0
8422va (VaSet
8423isHidden 1
8424font "Courier New,8,0"
8425)
8426xt "-92000,21600,-92000,21600"
8427tm "BdDeclarativeTextMgr"
8428)
8429diagSignalLabel (Text
8430uid 6,0
8431va (VaSet
8432font "Arial,8,1"
8433)
8434xt "-92000,23600,-84900,24600"
8435st "Diagram Signals:"
8436blo "-92000,24400"
8437)
8438postUserLabel (Text
8439uid 7,0
8440va (VaSet
8441isHidden 1
8442font "Arial,8,1"
8443)
8444xt "-92000,21600,-87300,22600"
8445st "Post User:"
8446blo "-92000,22400"
8447)
8448postUserText (MLText
8449uid 8,0
8450va (VaSet
8451isHidden 1
8452font "Courier New,8,0"
8453)
8454xt "-92000,21600,-92000,21600"
8455tm "BdDeclarativeTextMgr"
8456)
8457)
8458commonDM (CommonDM
8459ldm (LogicalDM
8460suid 62,0
8461usingSuid 1
8462emptyRow *265 (LEmptyRow
8463)
8464uid 54,0
8465optionalChildren [
8466*266 (RefLabelRowHdr
8467)
8468*267 (TitleRowHdr
8469)
8470*268 (FilterRowHdr
8471)
8472*269 (RefLabelColHdr
8473tm "RefLabelColHdrMgr"
8474)
8475*270 (RowExpandColHdr
8476tm "RowExpandColHdrMgr"
8477)
8478*271 (GroupColHdr
8479tm "GroupColHdrMgr"
8480)
8481*272 (NameColHdr
8482tm "BlockDiagramNameColHdrMgr"
8483)
8484*273 (ModeColHdr
8485tm "BlockDiagramModeColHdrMgr"
8486)
8487*274 (TypeColHdr
8488tm "BlockDiagramTypeColHdrMgr"
8489)
8490*275 (BoundsColHdr
8491tm "BlockDiagramBoundsColHdrMgr"
8492)
8493*276 (InitColHdr
8494tm "BlockDiagramInitColHdrMgr"
8495)
8496*277 (EolColHdr
8497tm "BlockDiagramEolColHdrMgr"
8498)
8499*278 (LeafLogPort
8500port (LogicalPort
8501m 4
8502decl (Decl
8503n "clk"
8504t "STD_LOGIC"
8505preAdd 0
8506posAdd 0
8507o 1
8508suid 1,0
8509)
8510)
8511uid 340,0
8512)
8513*279 (LeafLogPort
8514port (LogicalPort
8515m 4
8516decl (Decl
8517n "wiz_addr"
8518t "std_logic_vector"
8519b "(9 DOWNTO 0)"
8520o 2
8521suid 2,0
8522)
8523)
8524uid 342,0
8525)
8526*280 (LeafLogPort
8527port (LogicalPort
8528m 4
8529decl (Decl
8530n "wiz_data"
8531t "std_logic_vector"
8532b "(15 DOWNTO 0)"
8533o 3
8534suid 3,0
8535)
8536)
8537uid 344,0
8538)
8539*281 (LeafLogPort
8540port (LogicalPort
8541m 4
8542decl (Decl
8543n "wiz_rd"
8544t "std_logic"
8545o 4
8546suid 4,0
8547i "'1'"
8548)
8549)
8550uid 346,0
8551)
8552*282 (LeafLogPort
8553port (LogicalPort
8554m 4
8555decl (Decl
8556n "wiz_wr"
8557t "std_logic"
8558o 5
8559suid 5,0
8560i "'1'"
8561)
8562)
8563uid 348,0
8564)
8565*283 (LeafLogPort
8566port (LogicalPort
8567m 4
8568decl (Decl
8569n "sensor_cs"
8570t "std_logic_vector"
8571b "(3 DOWNTO 0)"
8572o 6
8573suid 6,0
8574)
8575)
8576uid 404,0
8577)
8578*284 (LeafLogPort
8579port (LogicalPort
8580m 4
8581decl (Decl
8582n "sclk"
8583t "std_logic"
8584o 7
8585suid 7,0
8586)
8587)
8588uid 406,0
8589)
8590*285 (LeafLogPort
8591port (LogicalPort
8592m 4
8593decl (Decl
8594n "sio"
8595t "std_logic"
8596preAdd 0
8597posAdd 0
8598o 8
8599suid 8,0
8600)
8601)
8602uid 408,0
8603)
8604*286 (LeafLogPort
8605port (LogicalPort
8606m 4
8607decl (Decl
8608n "trigger"
8609t "std_logic"
8610preAdd 0
8611posAdd 0
8612o 9
8613suid 9,0
8614)
8615)
8616uid 456,0
8617)
8618*287 (LeafLogPort
8619port (LogicalPort
8620m 4
8621decl (Decl
8622n "board_id"
8623t "std_logic_vector"
8624b "(3 downto 0)"
8625preAdd 0
8626posAdd 0
8627o 10
8628suid 10,0
8629)
8630)
8631uid 458,0
8632)
8633*288 (LeafLogPort
8634port (LogicalPort
8635m 4
8636decl (Decl
8637n "crate_id"
8638t "std_logic_vector"
8639b "(1 downto 0)"
8640o 11
8641suid 11,0
8642)
8643)
8644uid 460,0
8645)
8646*289 (LeafLogPort
8647port (LogicalPort
8648m 4
8649decl (Decl
8650n "adc_otr_array"
8651t "std_logic_vector"
8652b "(3 DOWNTO 0)"
8653o 12
8654suid 12,0
8655)
8656)
8657uid 584,0
8658)
8659*290 (LeafLogPort
8660port (LogicalPort
8661m 4
8662decl (Decl
8663n "adc_data_array"
8664t "adc_data_array_type"
8665o 13
8666suid 13,0
8667)
8668)
8669uid 586,0
8670)
8671*291 (LeafLogPort
8672port (LogicalPort
8673m 4
8674decl (Decl
8675n "adc_oeb"
8676t "std_logic"
8677preAdd 0
8678posAdd 0
8679o 14
8680suid 14,0
8681)
8682)
8683uid 588,0
8684)
8685*292 (LeafLogPort
8686port (LogicalPort
8687m 4
8688decl (Decl
8689n "adc_otr"
8690t "STD_LOGIC"
8691preAdd 0
8692posAdd 0
8693o 16
8694suid 16,0
8695)
8696)
8697uid 590,0
8698)
8699*293 (LeafLogPort
8700port (LogicalPort
8701m 4
8702decl (Decl
8703n "adc_data"
8704t "std_logic_vector"
8705b "(11 DOWNTO 0)"
8706preAdd 0
8707posAdd 0
8708o 17
8709suid 17,0
8710)
8711)
8712uid 592,0
8713)
8714*294 (LeafLogPort
8715port (LogicalPort
8716m 4
8717decl (Decl
8718n "wiz_reset"
8719t "std_logic"
8720o 21
8721suid 23,0
8722i "'1'"
8723)
8724)
8725uid 903,0
8726)
8727*295 (LeafLogPort
8728port (LogicalPort
8729m 4
8730decl (Decl
8731n "led"
8732t "std_logic_vector"
8733b "(7 DOWNTO 0)"
8734posAdd 0
8735o 22
8736suid 24,0
8737i "(OTHERS => '0')"
8738)
8739)
8740uid 905,0
8741)
8742*296 (LeafLogPort
8743port (LogicalPort
8744m 4
8745decl (Decl
8746n "wiz_cs"
8747t "std_logic"
8748o 23
8749suid 25,0
8750i "'1'"
8751)
8752)
8753uid 907,0
8754)
8755*297 (LeafLogPort
8756port (LogicalPort
8757m 4
8758decl (Decl
8759n "wiz_int"
8760t "std_logic"
8761o 24
8762suid 26,0
8763)
8764)
8765uid 909,0
8766)
8767*298 (LeafLogPort
8768port (LogicalPort
8769m 4
8770decl (Decl
8771n "dac_cs"
8772t "std_logic"
8773o 25
8774suid 27,0
8775)
8776)
8777uid 911,0
8778)
8779*299 (LeafLogPort
8780port (LogicalPort
8781m 4
8782decl (Decl
8783n "mosi"
8784t "std_logic"
8785o 26
8786suid 28,0
8787i "'0'"
8788)
8789)
8790uid 913,0
8791)
8792*300 (LeafLogPort
8793port (LogicalPort
8794m 4
8795decl (Decl
8796n "denable"
8797t "std_logic"
8798eolc "-- default domino wave off"
8799posAdd 0
8800o 27
8801suid 29,0
8802i "'0'"
8803)
8804)
8805uid 915,0
8806)
8807*301 (LeafLogPort
8808port (LogicalPort
8809m 4
8810decl (Decl
8811n "CLK_25_PS"
8812t "std_logic"
8813o 28
8814suid 30,0
8815)
8816)
8817uid 917,0
8818)
8819*302 (LeafLogPort
8820port (LogicalPort
8821m 4
8822decl (Decl
8823n "CLK_50"
8824t "std_logic"
8825o 29
8826suid 31,0
8827)
8828)
8829uid 919,0
8830)
8831*303 (LeafLogPort
8832port (LogicalPort
8833m 4
8834decl (Decl
8835n "drs_channel_id"
8836t "std_logic_vector"
8837b "(3 downto 0)"
8838o 30
8839suid 32,0
8840i "(others => '0')"
8841)
8842)
8843uid 921,0
8844)
8845*304 (LeafLogPort
8846port (LogicalPort
8847m 4
8848decl (Decl
8849n "drs_dwrite"
8850t "std_logic"
8851o 31
8852suid 33,0
8853i "'1'"
8854)
8855)
8856uid 923,0
8857)
8858*305 (LeafLogPort
8859port (LogicalPort
8860m 4
8861decl (Decl
8862n "RSRLOAD"
8863t "std_logic"
8864o 32
8865suid 34,0
8866i "'0'"
8867)
8868)
8869uid 925,0
8870)
8871*306 (LeafLogPort
8872port (LogicalPort
8873m 4
8874decl (Decl
8875n "SRCLK"
8876t "std_logic"
8877o 33
8878suid 35,0
8879i "'0'"
8880)
8881)
8882uid 927,0
8883)
8884*307 (LeafLogPort
8885port (LogicalPort
8886m 4
8887decl (Decl
8888n "SROUT_in_0"
8889t "std_logic"
8890o 30
8891suid 36,0
8892)
8893)
8894uid 929,0
8895)
8896*308 (LeafLogPort
8897port (LogicalPort
8898m 4
8899decl (Decl
8900n "SROUT_in_1"
8901t "std_logic"
8902o 31
8903suid 37,0
8904)
8905)
8906uid 931,0
8907)
8908*309 (LeafLogPort
8909port (LogicalPort
8910m 4
8911decl (Decl
8912n "SROUT_in_2"
8913t "std_logic"
8914o 32
8915suid 38,0
8916)
8917)
8918uid 933,0
8919)
8920*310 (LeafLogPort
8921port (LogicalPort
8922m 4
8923decl (Decl
8924n "SROUT_in_3"
8925t "std_logic"
8926o 33
8927suid 39,0
8928)
8929)
8930uid 935,0
8931)
8932*311 (LeafLogPort
8933port (LogicalPort
8934m 4
8935decl (Decl
8936n "SRIN_out"
8937t "std_logic"
8938o 34
8939suid 40,0
8940i "'0'"
8941)
8942)
8943uid 1541,0
8944)
8945*312 (LeafLogPort
8946port (LogicalPort
8947m 4
8948decl (Decl
8949n "amber"
8950t "std_logic"
8951o 35
8952suid 41,0
8953)
8954)
8955uid 1543,0
8956)
8957*313 (LeafLogPort
8958port (LogicalPort
8959m 4
8960decl (Decl
8961n "red"
8962t "std_logic"
8963o 36
8964suid 42,0
8965)
8966)
8967uid 1545,0
8968)
8969*314 (LeafLogPort
8970port (LogicalPort
8971m 4
8972decl (Decl
8973n "green"
8974t "std_logic"
8975o 37
8976suid 43,0
8977)
8978)
8979uid 1547,0
8980)
8981*315 (LeafLogPort
8982port (LogicalPort
8983m 4
8984decl (Decl
8985n "counter_result"
8986t "std_logic_vector"
8987b "(11 DOWNTO 0)"
8988o 38
8989suid 44,0
8990)
8991)
8992uid 1549,0
8993)
8994*316 (LeafLogPort
8995port (LogicalPort
8996m 4
8997decl (Decl
8998n "alarm_refclk_too_low"
8999t "std_logic"
9000posAdd 0
9001o 39
9002suid 45,0
9003)
9004)
9005uid 1551,0
9006)
9007*317 (LeafLogPort
9008port (LogicalPort
9009m 4
9010decl (Decl
9011n "alarm_refclk_too_high"
9012t "std_logic"
9013o 40
9014suid 46,0
9015)
9016)
9017uid 1553,0
9018)
9019*318 (LeafLogPort
9020port (LogicalPort
9021m 4
9022decl (Decl
9023n "D_T_in"
9024t "std_logic_vector"
9025b "(1 DOWNTO 0)"
9026o 41
9027suid 47,0
9028)
9029)
9030uid 1555,0
9031)
9032*319 (LeafLogPort
9033port (LogicalPort
9034m 4
9035decl (Decl
9036n "plllock_in"
9037t "std_logic_vector"
9038b "(3 DOWNTO 0)"
9039eolc "-- high level, if dominowave is running and DRS PLL locked"
9040o 43
9041suid 49,0
9042)
9043)
9044uid 1575,0
9045)
9046*320 (LeafLogPort
9047port (LogicalPort
9048lang 2
9049m 4
9050decl (Decl
9051n "ADC_CLK"
9052t "std_logic"
9053o 44
9054suid 50,0
9055)
9056)
9057uid 1690,0
9058)
9059*321 (LeafLogPort
9060port (LogicalPort
9061m 4
9062decl (Decl
9063n "REF_CLK"
9064t "STD_LOGIC"
9065o 42
9066suid 51,0
9067i "'0'"
9068)
9069)
9070uid 2003,0
9071)
9072*322 (LeafLogPort
9073port (LogicalPort
9074m 4
9075decl (Decl
9076n "debug_data_ram_empty"
9077t "std_logic"
9078o 45
9079suid 53,0
9080)
9081)
9082uid 2785,0
9083)
9084*323 (LeafLogPort
9085port (LogicalPort
9086m 4
9087decl (Decl
9088n "debug_data_valid"
9089t "std_logic"
9090o 46
9091suid 54,0
9092)
9093)
9094uid 2787,0
9095)
9096*324 (LeafLogPort
9097port (LogicalPort
9098m 4
9099decl (Decl
9100n "DG_state"
9101t "std_logic_vector"
9102b "(7 downto 0)"
9103prec "-- for debugging"
9104preAdd 0
9105o 47
9106suid 55,0
9107)
9108)
9109uid 2789,0
9110)
9111*325 (LeafLogPort
9112port (LogicalPort
9113m 4
9114decl (Decl
9115n "FTM_RS485_rx_en"
9116t "std_logic"
9117o 48
9118suid 56,0
9119)
9120)
9121uid 2791,0
9122)
9123*326 (LeafLogPort
9124port (LogicalPort
9125m 4
9126decl (Decl
9127n "FTM_RS485_tx_d"
9128t "std_logic"
9129o 49
9130suid 57,0
9131)
9132)
9133uid 2793,0
9134)
9135*327 (LeafLogPort
9136port (LogicalPort
9137m 4
9138decl (Decl
9139n "FTM_RS485_tx_en"
9140t "std_logic"
9141o 50
9142suid 58,0
9143)
9144)
9145uid 2795,0
9146)
9147*328 (LeafLogPort
9148port (LogicalPort
9149lang 2
9150m 4
9151decl (Decl
9152n "mem_manager_state"
9153t "std_logic_vector"
9154b "(3 DOWNTO 0)"
9155eolc "-- state is encoded here ... useful for debugging."
9156posAdd 0
9157o 51
9158suid 59,0
9159)
9160)
9161uid 2797,0
9162)
9163*329 (LeafLogPort
9164port (LogicalPort
9165m 4
9166decl (Decl
9167n "trigger_veto"
9168t "std_logic"
9169o 52
9170suid 60,0
9171i "'1'"
9172)
9173)
9174uid 2799,0
9175)
9176*330 (LeafLogPort
9177port (LogicalPort
9178m 4
9179decl (Decl
9180n "w5300_state"
9181t "std_logic_vector"
9182b "(7 DOWNTO 0)"
9183eolc "-- state is encoded here ... useful for debugging."
9184posAdd 0
9185o 53
9186suid 61,0
9187)
9188)
9189uid 2801,0
9190)
9191*331 (LeafLogPort
9192port (LogicalPort
9193m 4
9194decl (Decl
9195n "FTM_RS485_rx_d"
9196t "std_logic"
9197o 54
9198suid 62,0
9199)
9200)
9201uid 2803,0
9202)
9203]
9204)
9205pdm (PhysicalDM
9206displayShortBounds 1
9207editShortBounds 1
9208uid 67,0
9209optionalChildren [
9210*332 (Sheet
9211sheetRow (SheetRow
9212headerVa (MVa
9213cellColor "49152,49152,49152"
9214fontColor "0,0,0"
9215font "Tahoma,10,0"
9216)
9217cellVa (MVa
9218cellColor "65535,65535,65535"
9219fontColor "0,0,0"
9220font "Tahoma,10,0"
9221)
9222groupVa (MVa
9223cellColor "39936,56832,65280"
9224fontColor "0,0,0"
9225font "Tahoma,10,0"
9226)
9227emptyMRCItem *333 (MRCItem
9228litem &265
9229pos 54
9230dimension 20
9231)
9232uid 69,0
9233optionalChildren [
9234*334 (MRCItem
9235litem &266
9236pos 0
9237dimension 20
9238uid 70,0
9239)
9240*335 (MRCItem
9241litem &267
9242pos 1
9243dimension 23
9244uid 71,0
9245)
9246*336 (MRCItem
9247litem &268
9248pos 2
9249hidden 1
9250dimension 20
9251uid 72,0
9252)
9253*337 (MRCItem
9254litem &278
9255pos 0
9256dimension 20
9257uid 341,0
9258)
9259*338 (MRCItem
9260litem &279
9261pos 1
9262dimension 20
9263uid 343,0
9264)
9265*339 (MRCItem
9266litem &280
9267pos 2
9268dimension 20
9269uid 345,0
9270)
9271*340 (MRCItem
9272litem &281
9273pos 3
9274dimension 20
9275uid 347,0
9276)
9277*341 (MRCItem
9278litem &282
9279pos 4
9280dimension 20
9281uid 349,0
9282)
9283*342 (MRCItem
9284litem &283
9285pos 5
9286dimension 20
9287uid 405,0
9288)
9289*343 (MRCItem
9290litem &284
9291pos 6
9292dimension 20
9293uid 407,0
9294)
9295*344 (MRCItem
9296litem &285
9297pos 7
9298dimension 20
9299uid 409,0
9300)
9301*345 (MRCItem
9302litem &286
9303pos 8
9304dimension 20
9305uid 457,0
9306)
9307*346 (MRCItem
9308litem &287
9309pos 9
9310dimension 20
9311uid 459,0
9312)
9313*347 (MRCItem
9314litem &288
9315pos 10
9316dimension 20
9317uid 461,0
9318)
9319*348 (MRCItem
9320litem &289
9321pos 11
9322dimension 20
9323uid 585,0
9324)
9325*349 (MRCItem
9326litem &290
9327pos 12
9328dimension 20
9329uid 587,0
9330)
9331*350 (MRCItem
9332litem &291
9333pos 13
9334dimension 20
9335uid 589,0
9336)
9337*351 (MRCItem
9338litem &292
9339pos 14
9340dimension 20
9341uid 591,0
9342)
9343*352 (MRCItem
9344litem &293
9345pos 15
9346dimension 20
9347uid 593,0
9348)
9349*353 (MRCItem
9350litem &294
9351pos 16
9352dimension 20
9353uid 904,0
9354)
9355*354 (MRCItem
9356litem &295
9357pos 17
9358dimension 20
9359uid 906,0
9360)
9361*355 (MRCItem
9362litem &296
9363pos 18
9364dimension 20
9365uid 908,0
9366)
9367*356 (MRCItem
9368litem &297
9369pos 19
9370dimension 20
9371uid 910,0
9372)
9373*357 (MRCItem
9374litem &298
9375pos 20
9376dimension 20
9377uid 912,0
9378)
9379*358 (MRCItem
9380litem &299
9381pos 21
9382dimension 20
9383uid 914,0
9384)
9385*359 (MRCItem
9386litem &300
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9389uid 916,0
9390)
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9395uid 918,0
9396)
9397*361 (MRCItem
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9400dimension 20
9401uid 920,0
9402)
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9406dimension 20
9407uid 922,0
9408)
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9411pos 26
9412dimension 20
9413uid 924,0
9414)
9415*364 (MRCItem
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9417pos 27
9418dimension 20
9419uid 926,0
9420)
9421*365 (MRCItem
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9423pos 28
9424dimension 20
9425uid 928,0
9426)
9427*366 (MRCItem
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9429pos 29
9430dimension 20
9431uid 930,0
9432)
9433*367 (MRCItem
9434litem &308
9435pos 30
9436dimension 20
9437uid 932,0
9438)
9439*368 (MRCItem
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9442dimension 20
9443uid 934,0
9444)
9445*369 (MRCItem
9446litem &310
9447pos 32
9448dimension 20
9449uid 936,0
9450)
9451*370 (MRCItem
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9453pos 33
9454dimension 20
9455uid 1542,0
9456)
9457*371 (MRCItem
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9459pos 34
9460dimension 20
9461uid 1544,0
9462)
9463*372 (MRCItem
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9465pos 35
9466dimension 20
9467uid 1546,0
9468)
9469*373 (MRCItem
9470litem &314
9471pos 36
9472dimension 20
9473uid 1548,0
9474)
9475*374 (MRCItem
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9477pos 37
9478dimension 20
9479uid 1550,0
9480)
9481*375 (MRCItem
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9483pos 38
9484dimension 20
9485uid 1552,0
9486)
9487*376 (MRCItem
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9489pos 39
9490dimension 20
9491uid 1554,0
9492)
9493*377 (MRCItem
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9495pos 40
9496dimension 20
9497uid 1556,0
9498)
9499*378 (MRCItem
9500litem &319
9501pos 41
9502dimension 20
9503uid 1576,0
9504)
9505*379 (MRCItem
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9507pos 42
9508dimension 20
9509uid 1691,0
9510)
9511*380 (MRCItem
9512litem &321
9513pos 43
9514dimension 20
9515uid 2004,0
9516)
9517*381 (MRCItem
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9519pos 44
9520dimension 20
9521uid 2786,0
9522)
9523*382 (MRCItem
9524litem &323
9525pos 45
9526dimension 20
9527uid 2788,0
9528)
9529*383 (MRCItem
9530litem &324
9531pos 46
9532dimension 20
9533uid 2790,0
9534)
9535*384 (MRCItem
9536litem &325
9537pos 47
9538dimension 20
9539uid 2792,0
9540)
9541*385 (MRCItem
9542litem &326
9543pos 48
9544dimension 20
9545uid 2794,0
9546)
9547*386 (MRCItem
9548litem &327
9549pos 49
9550dimension 20
9551uid 2796,0
9552)
9553*387 (MRCItem
9554litem &328
9555pos 50
9556dimension 20
9557uid 2798,0
9558)
9559*388 (MRCItem
9560litem &329
9561pos 51
9562dimension 20
9563uid 2800,0
9564)
9565*389 (MRCItem
9566litem &330
9567pos 52
9568dimension 20
9569uid 2802,0
9570)
9571*390 (MRCItem
9572litem &331
9573pos 53
9574dimension 20
9575uid 2804,0
9576)
9577]
9578)
9579sheetCol (SheetCol
9580propVa (MVa
9581cellColor "0,49152,49152"
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9583font "Tahoma,10,0"
9584textAngle 90
9585)
9586uid 73,0
9587optionalChildren [
9588*391 (MRCItem
9589litem &269
9590pos 0
9591dimension 20
9592uid 74,0
9593)
9594*392 (MRCItem
9595litem &271
9596pos 1
9597dimension 50
9598uid 75,0
9599)
9600*393 (MRCItem
9601litem &272
9602pos 2
9603dimension 100
9604uid 76,0
9605)
9606*394 (MRCItem
9607litem &273
9608pos 3
9609dimension 50
9610uid 77,0
9611)
9612*395 (MRCItem
9613litem &274
9614pos 4
9615dimension 100
9616uid 78,0
9617)
9618*396 (MRCItem
9619litem &275
9620pos 5
9621dimension 100
9622uid 79,0
9623)
9624*397 (MRCItem
9625litem &276
9626pos 6
9627dimension 50
9628uid 80,0
9629)
9630*398 (MRCItem
9631litem &277
9632pos 7
9633dimension 80
9634uid 81,0
9635)
9636]
9637)
9638fixedCol 4
9639fixedRow 2
9640name "Ports"
9641uid 68,0
9642vaOverrides [
9643]
9644)
9645]
9646)
9647uid 53,0
9648)
9649genericsCommonDM (CommonDM
9650ldm (LogicalDM
9651emptyRow *399 (LEmptyRow
9652)
9653uid 83,0
9654optionalChildren [
9655*400 (RefLabelRowHdr
9656)
9657*401 (TitleRowHdr
9658)
9659*402 (FilterRowHdr
9660)
9661*403 (RefLabelColHdr
9662tm "RefLabelColHdrMgr"
9663)
9664*404 (RowExpandColHdr
9665tm "RowExpandColHdrMgr"
9666)
9667*405 (GroupColHdr
9668tm "GroupColHdrMgr"
9669)
9670*406 (NameColHdr
9671tm "GenericNameColHdrMgr"
9672)
9673*407 (TypeColHdr
9674tm "GenericTypeColHdrMgr"
9675)
9676*408 (InitColHdr
9677tm "GenericValueColHdrMgr"
9678)
9679*409 (PragmaColHdr
9680tm "GenericPragmaColHdrMgr"
9681)
9682*410 (EolColHdr
9683tm "GenericEolColHdrMgr"
9684)
9685]
9686)
9687pdm (PhysicalDM
9688displayShortBounds 1
9689editShortBounds 1
9690uid 95,0
9691optionalChildren [
9692*411 (Sheet
9693sheetRow (SheetRow
9694headerVa (MVa
9695cellColor "49152,49152,49152"
9696fontColor "0,0,0"
9697font "Tahoma,10,0"
9698)
9699cellVa (MVa
9700cellColor "65535,65535,65535"
9701fontColor "0,0,0"
9702font "Tahoma,10,0"
9703)
9704groupVa (MVa
9705cellColor "39936,56832,65280"
9706fontColor "0,0,0"
9707font "Tahoma,10,0"
9708)
9709emptyMRCItem *412 (MRCItem
9710litem &399
9711pos 0
9712dimension 20
9713)
9714uid 97,0
9715optionalChildren [
9716*413 (MRCItem
9717litem &400
9718pos 0
9719dimension 20
9720uid 98,0
9721)
9722*414 (MRCItem
9723litem &401
9724pos 1
9725dimension 23
9726uid 99,0
9727)
9728*415 (MRCItem
9729litem &402
9730pos 2
9731hidden 1
9732dimension 20
9733uid 100,0
9734)
9735]
9736)
9737sheetCol (SheetCol
9738propVa (MVa
9739cellColor "0,49152,49152"
9740fontColor "0,0,0"
9741font "Tahoma,10,0"
9742textAngle 90
9743)
9744uid 101,0
9745optionalChildren [
9746*416 (MRCItem
9747litem &403
9748pos 0
9749dimension 20
9750uid 102,0
9751)
9752*417 (MRCItem
9753litem &405
9754pos 1
9755dimension 50
9756uid 103,0
9757)
9758*418 (MRCItem
9759litem &406
9760pos 2
9761dimension 100
9762uid 104,0
9763)
9764*419 (MRCItem
9765litem &407
9766pos 3
9767dimension 100
9768uid 105,0
9769)
9770*420 (MRCItem
9771litem &408
9772pos 4
9773dimension 50
9774uid 106,0
9775)
9776*421 (MRCItem
9777litem &409
9778pos 5
9779dimension 50
9780uid 107,0
9781)
9782*422 (MRCItem
9783litem &410
9784pos 6
9785dimension 80
9786uid 108,0
9787)
9788]
9789)
9790fixedCol 3
9791fixedRow 2
9792name "Ports"
9793uid 96,0
9794vaOverrides [
9795]
9796)
9797]
9798)
9799uid 82,0
9800type 1
9801)
9802activeModelName "BlockDiag"
9803)
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