source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak @ 10914

Last change on this file since 10914 was 10914, checked in by neise, 9 years ago
File size: 152.7 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
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9(DmPackageRef
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11unitName "std_logic_arith"
12)
13(DmPackageRef
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17(DmPackageRef
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111(Instance
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979b "(9 DOWNTO 0)"
980o 47
981suid 26,0
982)
983)
984)
985*20 (CptPort
986uid 137,0
987ps "OnEdgeStrategy"
988shape (Diamond
989uid 138,0
990ro 90
991va (VaSet
992vasetType 1
993fg "0,65535,0"
994)
995xt "109000,21625,109750,22375"
996)
997tg (CPTG
998uid 139,0
999ps "CptPortTextPlaceStrategy"
1000stg "RightVerticalLayoutStrategy"
1001f (Text
1002uid 140,0
1003va (VaSet
1004)
1005xt "100800,21500,108000,22500"
1006st "wiz_data : (15:0)"
1007ju 2
1008blo "108000,22300"
1009)
1010)
1011thePort (LogicalPort
1012m 2
1013decl (Decl
1014n "wiz_data"
1015t "std_logic_vector"
1016b "(15 DOWNTO 0)"
1017o 53
1018suid 27,0
1019)
1020)
1021)
1022*21 (CptPort
1023uid 141,0
1024ps "OnEdgeStrategy"
1025shape (Triangle
1026uid 142,0
1027ro 90
1028va (VaSet
1029vasetType 1
1030fg "0,65535,0"
1031)
1032xt "109000,27625,109750,28375"
1033)
1034tg (CPTG
1035uid 143,0
1036ps "CptPortTextPlaceStrategy"
1037stg "RightVerticalLayoutStrategy"
1038f (Text
1039uid 144,0
1040va (VaSet
1041)
1042xt "105000,27500,108000,28500"
1043st "wiz_cs"
1044ju 2
1045blo "108000,28300"
1046)
1047)
1048thePort (LogicalPort
1049m 1
1050decl (Decl
1051n "wiz_cs"
1052t "std_logic"
1053o 48
1054suid 28,0
1055i "'1'"
1056)
1057)
1058)
1059*22 (CptPort
1060uid 145,0
1061ps "OnEdgeStrategy"
1062shape (Triangle
1063uid 146,0
1064ro 90
1065va (VaSet
1066vasetType 1
1067fg "0,65535,0"
1068)
1069xt "109000,25625,109750,26375"
1070)
1071tg (CPTG
1072uid 147,0
1073ps "CptPortTextPlaceStrategy"
1074stg "RightVerticalLayoutStrategy"
1075f (Text
1076uid 148,0
1077va (VaSet
1078)
1079xt "104800,25500,108000,26500"
1080st "wiz_wr"
1081ju 2
1082blo "108000,26300"
1083)
1084)
1085thePort (LogicalPort
1086m 1
1087decl (Decl
1088n "wiz_wr"
1089t "std_logic"
1090o 51
1091suid 29,0
1092i "'1'"
1093)
1094)
1095)
1096*23 (CptPort
1097uid 149,0
1098ps "OnEdgeStrategy"
1099shape (Triangle
1100uid 150,0
1101ro 90
1102va (VaSet
1103vasetType 1
1104fg "0,65535,0"
1105)
1106xt "109000,24625,109750,25375"
1107)
1108tg (CPTG
1109uid 151,0
1110ps "CptPortTextPlaceStrategy"
1111stg "RightVerticalLayoutStrategy"
1112f (Text
1113uid 152,0
1114va (VaSet
1115)
1116xt "104900,24500,108000,25500"
1117st "wiz_rd"
1118ju 2
1119blo "108000,25300"
1120)
1121)
1122thePort (LogicalPort
1123m 1
1124decl (Decl
1125n "wiz_rd"
1126t "std_logic"
1127o 49
1128suid 30,0
1129i "'1'"
1130)
1131)
1132)
1133*24 (CptPort
1134uid 153,0
1135ps "OnEdgeStrategy"
1136shape (Triangle
1137uid 154,0
1138ro 270
1139va (VaSet
1140vasetType 1
1141fg "0,65535,0"
1142)
1143xt "109000,26625,109750,27375"
1144)
1145tg (CPTG
1146uid 155,0
1147ps "CptPortTextPlaceStrategy"
1148stg "RightVerticalLayoutStrategy"
1149f (Text
1150uid 156,0
1151va (VaSet
1152)
1153xt "104800,26500,108000,27500"
1154st "wiz_int"
1155ju 2
1156blo "108000,27300"
1157)
1158)
1159thePort (LogicalPort
1160decl (Decl
1161n "wiz_int"
1162t "std_logic"
1163o 15
1164suid 31,0
1165)
1166)
1167)
1168*25 (CptPort
1169uid 157,0
1170ps "OnEdgeStrategy"
1171shape (Triangle
1172uid 158,0
1173ro 270
1174va (VaSet
1175vasetType 1
1176fg "0,65535,0"
1177)
1178xt "80250,22625,81000,23375"
1179)
1180tg (CPTG
1181uid 159,0
1182ps "CptPortTextPlaceStrategy"
1183stg "VerticalLayoutStrategy"
1184f (Text
1185uid 160,0
1186va (VaSet
1187)
1188xt "82000,22500,86800,23500"
1189st "CLK_25_PS"
1190blo "82000,23300"
1191)
1192)
1193thePort (LogicalPort
1194m 1
1195decl (Decl
1196n "CLK_25_PS"
1197t "std_logic"
1198o 17
1199suid 35,0
1200)
1201)
1202)
1203*26 (CptPort
1204uid 161,0
1205ps "OnEdgeStrategy"
1206shape (Triangle
1207uid 162,0
1208ro 270
1209va (VaSet
1210vasetType 1
1211fg "0,65535,0"
1212)
1213xt "80250,21625,81000,22375"
1214)
1215tg (CPTG
1216uid 163,0
1217ps "CptPortTextPlaceStrategy"
1218stg "VerticalLayoutStrategy"
1219f (Text
1220uid 164,0
1221va (VaSet
1222)
1223xt "82000,21500,85300,22500"
1224st "CLK_50"
1225blo "82000,22300"
1226)
1227)
1228thePort (LogicalPort
1229m 1
1230decl (Decl
1231n "CLK_50"
1232t "std_logic"
1233preAdd 0
1234posAdd 0
1235o 18
1236suid 37,0
1237)
1238)
1239)
1240*27 (CptPort
1241uid 165,0
1242ps "OnEdgeStrategy"
1243shape (Triangle
1244uid 166,0
1245ro 90
1246va (VaSet
1247vasetType 1
1248fg "0,65535,0"
1249)
1250xt "80250,20625,81000,21375"
1251)
1252tg (CPTG
1253uid 167,0
1254ps "CptPortTextPlaceStrategy"
1255stg "VerticalLayoutStrategy"
1256f (Text
1257uid 168,0
1258va (VaSet
1259)
1260xt "82000,20500,83900,21500"
1261st "CLK"
1262blo "82000,21300"
1263)
1264)
1265thePort (LogicalPort
1266decl (Decl
1267n "CLK"
1268t "std_logic"
1269o 1
1270suid 38,0
1271)
1272)
1273)
1274*28 (CptPort
1275uid 169,0
1276ps "OnEdgeStrategy"
1277shape (Triangle
1278uid 170,0
1279ro 90
1280va (VaSet
1281vasetType 1
1282fg "0,65535,0"
1283)
1284xt "80250,41625,81000,42375"
1285)
1286tg (CPTG
1287uid 171,0
1288ps "CptPortTextPlaceStrategy"
1289stg "VerticalLayoutStrategy"
1290f (Text
1291uid 172,0
1292va (VaSet
1293)
1294xt "82000,41500,91300,42500"
1295st "adc_otr_array : (3:0)"
1296blo "82000,42300"
1297)
1298)
1299thePort (LogicalPort
1300decl (Decl
1301n "adc_otr_array"
1302t "std_logic_vector"
1303b "(3 DOWNTO 0)"
1304o 9
1305suid 40,0
1306)
1307)
1308)
1309*29 (CptPort
1310uid 173,0
1311ps "OnEdgeStrategy"
1312shape (Triangle
1313uid 174,0
1314ro 90
1315va (VaSet
1316vasetType 1
1317fg "0,65535,0"
1318)
1319xt "80250,47625,81000,48375"
1320)
1321tg (CPTG
1322uid 175,0
1323ps "CptPortTextPlaceStrategy"
1324stg "VerticalLayoutStrategy"
1325f (Text
1326uid 176,0
1327va (VaSet
1328)
1329xt "82000,47500,88900,48500"
1330st "adc_data_array"
1331blo "82000,48300"
1332)
1333)
1334thePort (LogicalPort
1335decl (Decl
1336n "adc_data_array"
1337t "adc_data_array_type"
1338o 8
1339suid 41,0
1340)
1341)
1342)
1343*30 (CptPort
1344uid 177,0
1345ps "OnEdgeStrategy"
1346shape (Triangle
1347uid 178,0
1348ro 270
1349va (VaSet
1350vasetType 1
1351fg "0,65535,0"
1352)
1353xt "80250,61625,81000,62375"
1354)
1355tg (CPTG
1356uid 179,0
1357ps "CptPortTextPlaceStrategy"
1358stg "VerticalLayoutStrategy"
1359f (Text
1360uid 180,0
1361va (VaSet
1362)
1363xt "82000,61500,91500,62500"
1364st "drs_channel_id : (3:0)"
1365blo "82000,62300"
1366)
1367)
1368thePort (LogicalPort
1369m 1
1370decl (Decl
1371n "drs_channel_id"
1372t "std_logic_vector"
1373b "(3 downto 0)"
1374o 35
1375suid 48,0
1376i "(others => '0')"
1377)
1378)
1379)
1380*31 (CptPort
1381uid 181,0
1382ps "OnEdgeStrategy"
1383shape (Triangle
1384uid 182,0
1385ro 270
1386va (VaSet
1387vasetType 1
1388fg "0,65535,0"
1389)
1390xt "80250,66625,81000,67375"
1391)
1392tg (CPTG
1393uid 183,0
1394ps "CptPortTextPlaceStrategy"
1395stg "VerticalLayoutStrategy"
1396f (Text
1397uid 184,0
1398va (VaSet
1399)
1400xt "82000,66500,87200,67500"
1401st "drs_dwrite"
1402blo "82000,67300"
1403)
1404)
1405thePort (LogicalPort
1406m 1
1407decl (Decl
1408n "drs_dwrite"
1409t "std_logic"
1410o 36
1411suid 49,0
1412i "'1'"
1413)
1414)
1415)
1416*32 (CptPort
1417uid 185,0
1418ps "OnEdgeStrategy"
1419shape (Triangle
1420uid 186,0
1421ro 90
1422va (VaSet
1423vasetType 1
1424fg "0,65535,0"
1425)
1426xt "80250,57625,81000,58375"
1427)
1428tg (CPTG
1429uid 187,0
1430ps "CptPortTextPlaceStrategy"
1431stg "VerticalLayoutStrategy"
1432f (Text
1433uid 188,0
1434va (VaSet
1435)
1436xt "82000,57500,87800,58500"
1437st "SROUT_in_0"
1438blo "82000,58300"
1439)
1440)
1441thePort (LogicalPort
1442decl (Decl
1443n "SROUT_in_0"
1444t "std_logic"
1445o 4
1446suid 52,0
1447)
1448)
1449)
1450*33 (CptPort
1451uid 189,0
1452ps "OnEdgeStrategy"
1453shape (Triangle
1454uid 190,0
1455ro 90
1456va (VaSet
1457vasetType 1
1458fg "0,65535,0"
1459)
1460xt "80250,58625,81000,59375"
1461)
1462tg (CPTG
1463uid 191,0
1464ps "CptPortTextPlaceStrategy"
1465stg "VerticalLayoutStrategy"
1466f (Text
1467uid 192,0
1468va (VaSet
1469)
1470xt "82000,58500,87700,59500"
1471st "SROUT_in_1"
1472blo "82000,59300"
1473)
1474)
1475thePort (LogicalPort
1476decl (Decl
1477n "SROUT_in_1"
1478t "std_logic"
1479o 5
1480suid 53,0
1481)
1482)
1483)
1484*34 (CptPort
1485uid 193,0
1486ps "OnEdgeStrategy"
1487shape (Triangle
1488uid 194,0
1489ro 90
1490va (VaSet
1491vasetType 1
1492fg "0,65535,0"
1493)
1494xt "80250,59625,81000,60375"
1495)
1496tg (CPTG
1497uid 195,0
1498ps "CptPortTextPlaceStrategy"
1499stg "VerticalLayoutStrategy"
1500f (Text
1501uid 196,0
1502va (VaSet
1503)
1504xt "82000,59500,87800,60500"
1505st "SROUT_in_2"
1506blo "82000,60300"
1507)
1508)
1509thePort (LogicalPort
1510decl (Decl
1511n "SROUT_in_2"
1512t "std_logic"
1513o 6
1514suid 54,0
1515)
1516)
1517)
1518*35 (CptPort
1519uid 197,0
1520ps "OnEdgeStrategy"
1521shape (Triangle
1522uid 198,0
1523ro 90
1524va (VaSet
1525vasetType 1
1526fg "0,65535,0"
1527)
1528xt "80250,60625,81000,61375"
1529)
1530tg (CPTG
1531uid 199,0
1532ps "CptPortTextPlaceStrategy"
1533stg "VerticalLayoutStrategy"
1534f (Text
1535uid 200,0
1536va (VaSet
1537)
1538xt "82000,60500,87800,61500"
1539st "SROUT_in_3"
1540blo "82000,61300"
1541)
1542)
1543thePort (LogicalPort
1544decl (Decl
1545n "SROUT_in_3"
1546t "std_logic"
1547o 7
1548suid 55,0
1549)
1550)
1551)
1552*36 (CptPort
1553uid 201,0
1554ps "OnEdgeStrategy"
1555shape (Triangle
1556uid 202,0
1557ro 270
1558va (VaSet
1559vasetType 1
1560fg "0,65535,0"
1561)
1562xt "80250,63625,81000,64375"
1563)
1564tg (CPTG
1565uid 203,0
1566ps "CptPortTextPlaceStrategy"
1567stg "VerticalLayoutStrategy"
1568f (Text
1569uid 204,0
1570va (VaSet
1571)
1572xt "82000,63500,86200,64500"
1573st "RSRLOAD"
1574blo "82000,64300"
1575)
1576)
1577thePort (LogicalPort
1578m 1
1579decl (Decl
1580n "RSRLOAD"
1581t "std_logic"
1582o 23
1583suid 56,0
1584i "'0'"
1585)
1586)
1587)
1588*37 (CptPort
1589uid 205,0
1590ps "OnEdgeStrategy"
1591shape (Triangle
1592uid 206,0
1593ro 270
1594va (VaSet
1595vasetType 1
1596fg "0,65535,0"
1597)
1598xt "80250,64625,81000,65375"
1599)
1600tg (CPTG
1601uid 207,0
1602ps "CptPortTextPlaceStrategy"
1603stg "VerticalLayoutStrategy"
1604f (Text
1605uid 208,0
1606va (VaSet
1607)
1608xt "82000,64500,84900,65500"
1609st "SRCLK"
1610blo "82000,65300"
1611)
1612)
1613thePort (LogicalPort
1614m 1
1615decl (Decl
1616n "SRCLK"
1617t "std_logic"
1618o 24
1619suid 57,0
1620i "'0'"
1621)
1622)
1623)
1624*38 (CptPort
1625uid 209,0
1626ps "OnEdgeStrategy"
1627shape (Triangle
1628uid 210,0
1629ro 90
1630va (VaSet
1631vasetType 1
1632fg "0,65535,0"
1633)
1634xt "109000,50625,109750,51375"
1635)
1636tg (CPTG
1637uid 211,0
1638ps "CptPortTextPlaceStrategy"
1639stg "RightVerticalLayoutStrategy"
1640f (Text
1641uid 212,0
1642va (VaSet
1643)
1644xt "106100,50500,108000,51500"
1645st "sclk"
1646ju 2
1647blo "108000,51300"
1648)
1649)
1650thePort (LogicalPort
1651m 1
1652decl (Decl
1653n "sclk"
1654t "std_logic"
1655o 42
1656suid 62,0
1657)
1658)
1659)
1660*39 (CptPort
1661uid 213,0
1662ps "OnEdgeStrategy"
1663shape (Diamond
1664uid 214,0
1665ro 90
1666va (VaSet
1667vasetType 1
1668fg "0,65535,0"
1669)
1670xt "109000,51625,109750,52375"
1671)
1672tg (CPTG
1673uid 215,0
1674ps "CptPortTextPlaceStrategy"
1675stg "RightVerticalLayoutStrategy"
1676f (Text
1677uid 216,0
1678va (VaSet
1679)
1680xt "106600,51500,108000,52500"
1681st "sio"
1682ju 2
1683blo "108000,52300"
1684)
1685)
1686thePort (LogicalPort
1687m 2
1688decl (Decl
1689n "sio"
1690t "std_logic"
1691preAdd 0
1692posAdd 0
1693o 52
1694suid 63,0
1695)
1696)
1697)
1698*40 (CptPort
1699uid 217,0
1700ps "OnEdgeStrategy"
1701shape (Triangle
1702uid 218,0
1703ro 90
1704va (VaSet
1705vasetType 1
1706fg "0,65535,0"
1707)
1708xt "109000,39625,109750,40375"
1709)
1710tg (CPTG
1711uid 219,0
1712ps "CptPortTextPlaceStrategy"
1713stg "RightVerticalLayoutStrategy"
1714f (Text
1715uid 220,0
1716va (VaSet
1717)
1718xt "105000,39500,108000,40500"
1719st "dac_cs"
1720ju 2
1721blo "108000,40300"
1722)
1723)
1724thePort (LogicalPort
1725m 1
1726decl (Decl
1727n "dac_cs"
1728t "std_logic"
1729o 31
1730suid 64,0
1731)
1732)
1733)
1734*41 (CptPort
1735uid 221,0
1736ps "OnEdgeStrategy"
1737shape (Triangle
1738uid 222,0
1739ro 90
1740va (VaSet
1741vasetType 1
1742fg "0,65535,0"
1743)
1744xt "109000,41625,109750,42375"
1745)
1746tg (CPTG
1747uid 223,0
1748ps "CptPortTextPlaceStrategy"
1749stg "RightVerticalLayoutStrategy"
1750f (Text
1751uid 224,0
1752va (VaSet
1753)
1754xt "101000,41500,108000,42500"
1755st "sensor_cs : (3:0)"
1756ju 2
1757blo "108000,42300"
1758)
1759)
1760thePort (LogicalPort
1761m 1
1762decl (Decl
1763n "sensor_cs"
1764t "std_logic_vector"
1765b "(3 DOWNTO 0)"
1766o 43
1767suid 65,0
1768)
1769)
1770)
1771*42 (CptPort
1772uid 225,0
1773ps "OnEdgeStrategy"
1774shape (Triangle
1775uid 226,0
1776ro 90
1777va (VaSet
1778vasetType 1
1779fg "0,65535,0"
1780)
1781xt "109000,52625,109750,53375"
1782)
1783tg (CPTG
1784uid 227,0
1785ps "CptPortTextPlaceStrategy"
1786stg "RightVerticalLayoutStrategy"
1787f (Text
1788uid 228,0
1789va (VaSet
1790)
1791xt "106000,52500,108000,53500"
1792st "mosi"
1793ju 2
1794blo "108000,53300"
1795)
1796)
1797thePort (LogicalPort
1798m 1
1799decl (Decl
1800n "mosi"
1801t "std_logic"
1802o 40
1803suid 66,0
1804i "'0'"
1805)
1806)
1807)
1808*43 (CptPort
1809uid 229,0
1810ps "OnEdgeStrategy"
1811shape (Triangle
1812uid 230,0
1813ro 270
1814va (VaSet
1815vasetType 1
1816fg "0,65535,0"
1817)
1818xt "80250,65625,81000,66375"
1819)
1820tg (CPTG
1821uid 231,0
1822ps "CptPortTextPlaceStrategy"
1823stg "VerticalLayoutStrategy"
1824f (Text
1825uid 232,0
1826va (VaSet
1827)
1828xt "82000,65500,85200,66500"
1829st "denable"
1830blo "82000,66300"
1831)
1832)
1833thePort (LogicalPort
1834m 1
1835decl (Decl
1836n "denable"
1837t "std_logic"
1838eolc "-- default domino wave off"
1839posAdd 0
1840o 34
1841suid 67,0
1842i "'0'"
1843)
1844)
1845)
1846*44 (CptPort
1847uid 1395,0
1848ps "OnEdgeStrategy"
1849shape (Triangle
1850uid 1396,0
1851ro 90
1852va (VaSet
1853vasetType 1
1854fg "0,65535,0"
1855)
1856xt "109000,73625,109750,74375"
1857)
1858tg (CPTG
1859uid 1397,0
1860ps "CptPortTextPlaceStrategy"
1861stg "RightVerticalLayoutStrategy"
1862f (Text
1863uid 1398,0
1864va (VaSet
1865)
1866xt "98000,73500,108000,74500"
1867st "alarm_refclk_too_high"
1868ju 2
1869blo "108000,74300"
1870)
1871)
1872thePort (LogicalPort
1873m 1
1874decl (Decl
1875n "alarm_refclk_too_high"
1876t "std_logic"
1877o 27
1878suid 95,0
1879)
1880)
1881)
1882*45 (CptPort
1883uid 1399,0
1884ps "OnEdgeStrategy"
1885shape (Triangle
1886uid 1400,0
1887ro 90
1888va (VaSet
1889vasetType 1
1890fg "0,65535,0"
1891)
1892xt "109000,74625,109750,75375"
1893)
1894tg (CPTG
1895uid 1401,0
1896ps "CptPortTextPlaceStrategy"
1897stg "RightVerticalLayoutStrategy"
1898f (Text
1899uid 1402,0
1900va (VaSet
1901)
1902xt "98400,74500,108000,75500"
1903st "alarm_refclk_too_low"
1904ju 2
1905blo "108000,75300"
1906)
1907)
1908thePort (LogicalPort
1909m 1
1910decl (Decl
1911n "alarm_refclk_too_low"
1912t "std_logic"
1913posAdd 0
1914o 28
1915suid 96,0
1916)
1917)
1918)
1919*46 (CptPort
1920uid 1403,0
1921ps "OnEdgeStrategy"
1922shape (Triangle
1923uid 1404,0
1924ro 90
1925va (VaSet
1926vasetType 1
1927fg "0,65535,0"
1928)
1929xt "109000,79625,109750,80375"
1930)
1931tg (CPTG
1932uid 1405,0
1933ps "CptPortTextPlaceStrategy"
1934stg "RightVerticalLayoutStrategy"
1935f (Text
1936uid 1406,0
1937va (VaSet
1938)
1939xt "105300,79500,108000,80500"
1940st "amber"
1941ju 2
1942blo "108000,80300"
1943)
1944)
1945thePort (LogicalPort
1946m 1
1947decl (Decl
1948n "amber"
1949t "std_logic"
1950o 29
1951suid 87,0
1952)
1953)
1954)
1955*47 (CptPort
1956uid 1407,0
1957ps "OnEdgeStrategy"
1958shape (Triangle
1959uid 1408,0
1960ro 90
1961va (VaSet
1962vasetType 1
1963fg "0,65535,0"
1964)
1965xt "109000,76625,109750,77375"
1966)
1967tg (CPTG
1968uid 1409,0
1969ps "CptPortTextPlaceStrategy"
1970stg "RightVerticalLayoutStrategy"
1971f (Text
1972uid 1410,0
1973va (VaSet
1974)
1975xt "98400,76500,108000,77500"
1976st "counter_result : (11:0)"
1977ju 2
1978blo "108000,77300"
1979)
1980)
1981thePort (LogicalPort
1982m 1
1983decl (Decl
1984n "counter_result"
1985t "std_logic_vector"
1986b "(11 DOWNTO 0)"
1987o 30
1988suid 94,0
1989)
1990)
1991)
1992*48 (CptPort
1993uid 1411,0
1994ps "OnEdgeStrategy"
1995shape (Triangle
1996uid 1412,0
1997ro 90
1998va (VaSet
1999vasetType 1
2000fg "0,65535,0"
2001)
2002xt "80250,74625,81000,75375"
2003)
2004tg (CPTG
2005uid 1413,0
2006ps "CptPortTextPlaceStrategy"
2007stg "VerticalLayoutStrategy"
2008f (Text
2009uid 1414,0
2010va (VaSet
2011)
2012xt "82000,74500,87500,75500"
2013st "D_T_in : (1:0)"
2014blo "82000,75300"
2015)
2016)
2017thePort (LogicalPort
2018decl (Decl
2019n "D_T_in"
2020t "std_logic_vector"
2021b "(1 DOWNTO 0)"
2022o 2
2023suid 91,0
2024)
2025)
2026)
2027*49 (CptPort
2028uid 1415,0
2029ps "OnEdgeStrategy"
2030shape (Triangle
2031uid 1416,0
2032ro 90
2033va (VaSet
2034vasetType 1
2035fg "0,65535,0"
2036)
2037xt "80250,75625,81000,76375"
2038)
2039tg (CPTG
2040uid 1417,0
2041ps "CptPortTextPlaceStrategy"
2042stg "VerticalLayoutStrategy"
2043f (Text
2044uid 1418,0
2045va (VaSet
2046)
2047xt "82000,75500,88100,76500"
2048st "drs_refclk_in"
2049blo "82000,76300"
2050)
2051)
2052thePort (LogicalPort
2053decl (Decl
2054n "drs_refclk_in"
2055t "std_logic"
2056eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
2057o 12
2058suid 92,0
2059)
2060)
2061)
2062*50 (CptPort
2063uid 1419,0
2064ps "OnEdgeStrategy"
2065shape (Triangle
2066uid 1420,0
2067ro 90
2068va (VaSet
2069vasetType 1
2070fg "0,65535,0"
2071)
2072xt "109000,77625,109750,78375"
2073)
2074tg (CPTG
2075uid 1421,0
2076ps "CptPortTextPlaceStrategy"
2077stg "RightVerticalLayoutStrategy"
2078f (Text
2079uid 1422,0
2080va (VaSet
2081)
2082xt "105600,77500,108000,78500"
2083st "green"
2084ju 2
2085blo "108000,78300"
2086)
2087)
2088thePort (LogicalPort
2089m 1
2090decl (Decl
2091n "green"
2092t "std_logic"
2093o 37
2094suid 86,0
2095)
2096)
2097)
2098*51 (CptPort
2099uid 1423,0
2100ps "OnEdgeStrategy"
2101shape (Triangle
2102uid 1424,0
2103ro 90
2104va (VaSet
2105vasetType 1
2106fg "0,65535,0"
2107)
2108xt "80250,76625,81000,77375"
2109)
2110tg (CPTG
2111uid 1425,0
2112ps "CptPortTextPlaceStrategy"
2113stg "VerticalLayoutStrategy"
2114f (Text
2115uid 1426,0
2116va (VaSet
2117)
2118xt "82000,76500,88700,77500"
2119st "plllock_in : (3:0)"
2120blo "82000,77300"
2121)
2122)
2123thePort (LogicalPort
2124decl (Decl
2125n "plllock_in"
2126t "std_logic_vector"
2127b "(3 DOWNTO 0)"
2128eolc "-- high level, if dominowave is running and DRS PLL locked"
2129o 13
2130suid 93,0
2131)
2132)
2133)
2134*52 (CptPort
2135uid 1427,0
2136ps "OnEdgeStrategy"
2137shape (Triangle
2138uid 1428,0
2139ro 90
2140va (VaSet
2141vasetType 1
2142fg "0,65535,0"
2143)
2144xt "109000,78625,109750,79375"
2145)
2146tg (CPTG
2147uid 1429,0
2148ps "CptPortTextPlaceStrategy"
2149stg "RightVerticalLayoutStrategy"
2150f (Text
2151uid 1430,0
2152va (VaSet
2153)
2154xt "106300,78500,108000,79500"
2155st "red"
2156ju 2
2157blo "108000,79300"
2158)
2159)
2160thePort (LogicalPort
2161m 1
2162decl (Decl
2163n "red"
2164t "std_logic"
2165o 41
2166suid 88,0
2167)
2168)
2169)
2170*53 (CptPort
2171uid 1431,0
2172ps "OnEdgeStrategy"
2173shape (Triangle
2174uid 1432,0
2175ro 270
2176va (VaSet
2177vasetType 1
2178fg "0,65535,0"
2179)
2180xt "80250,71625,81000,72375"
2181)
2182tg (CPTG
2183uid 1433,0
2184ps "CptPortTextPlaceStrategy"
2185stg "VerticalLayoutStrategy"
2186f (Text
2187uid 1434,0
2188va (VaSet
2189)
2190xt "82000,71500,86200,72500"
2191st "SRIN_out"
2192blo "82000,72300"
2193)
2194)
2195thePort (LogicalPort
2196m 1
2197decl (Decl
2198n "SRIN_out"
2199t "std_logic"
2200o 25
2201suid 85,0
2202i "'0'"
2203)
2204)
2205)
2206*54 (CptPort
2207uid 1678,0
2208ps "OnEdgeStrategy"
2209shape (Triangle
2210uid 1679,0
2211ro 270
2212va (VaSet
2213vasetType 1
2214fg "0,65535,0"
2215)
2216xt "80250,23625,81000,24375"
2217)
2218tg (CPTG
2219uid 1680,0
2220ps "CptPortTextPlaceStrategy"
2221stg "VerticalLayoutStrategy"
2222f (Text
2223uid 1681,0
2224va (VaSet
2225)
2226xt "82000,23500,86000,24500"
2227st "ADC_CLK"
2228blo "82000,24300"
2229)
2230)
2231thePort (LogicalPort
2232lang 2
2233m 1
2234decl (Decl
2235n "ADC_CLK"
2236t "std_logic"
2237o 16
2238suid 97,0
2239)
2240)
2241)
2242*55 (CptPort
2243uid 2651,0
2244ps "OnEdgeStrategy"
2245shape (Triangle
2246uid 2652,0
2247ro 90
2248va (VaSet
2249vasetType 1
2250fg "0,65535,0"
2251)
2252xt "109000,80625,109750,81375"
2253)
2254tg (CPTG
2255uid 2653,0
2256ps "CptPortTextPlaceStrategy"
2257stg "RightVerticalLayoutStrategy"
2258f (Text
2259uid 2654,0
2260va (VaSet
2261)
2262xt "97600,80500,108000,81500"
2263st "debug_data_ram_empty"
2264ju 2
2265blo "108000,81300"
2266)
2267)
2268thePort (LogicalPort
2269m 1
2270decl (Decl
2271n "debug_data_ram_empty"
2272t "std_logic"
2273o 32
2274suid 104,0
2275)
2276)
2277)
2278*56 (CptPort
2279uid 2655,0
2280ps "OnEdgeStrategy"
2281shape (Triangle
2282uid 2656,0
2283ro 90
2284va (VaSet
2285vasetType 1
2286fg "0,65535,0"
2287)
2288xt "109000,81625,109750,82375"
2289)
2290tg (CPTG
2291uid 2657,0
2292ps "CptPortTextPlaceStrategy"
2293stg "RightVerticalLayoutStrategy"
2294f (Text
2295uid 2658,0
2296va (VaSet
2297)
2298xt "100500,81500,108000,82500"
2299st "debug_data_valid"
2300ju 2
2301blo "108000,82300"
2302)
2303)
2304thePort (LogicalPort
2305m 1
2306decl (Decl
2307n "debug_data_valid"
2308t "std_logic"
2309o 33
2310suid 105,0
2311)
2312)
2313)
2314*57 (CptPort
2315uid 2659,0
2316ps "OnEdgeStrategy"
2317shape (Triangle
2318uid 2660,0
2319ro 90
2320va (VaSet
2321vasetType 1
2322fg "0,65535,0"
2323)
2324xt "109000,82625,109750,83375"
2325)
2326tg (CPTG
2327uid 2661,0
2328ps "CptPortTextPlaceStrategy"
2329stg "RightVerticalLayoutStrategy"
2330f (Text
2331uid 2662,0
2332va (VaSet
2333)
2334xt "101100,82500,108000,83500"
2335st "DG_state : (7:0)"
2336ju 2
2337blo "108000,83300"
2338)
2339)
2340thePort (LogicalPort
2341m 1
2342decl (Decl
2343n "DG_state"
2344t "std_logic_vector"
2345b "(7 downto 0)"
2346prec "-- for debugging"
2347preAdd 0
2348o 19
2349suid 108,0
2350)
2351)
2352)
2353*58 (CptPort
2354uid 2663,0
2355ps "OnEdgeStrategy"
2356shape (Triangle
2357uid 2664,0
2358ro 90
2359va (VaSet
2360vasetType 1
2361fg "0,65535,0"
2362)
2363xt "80250,77625,81000,78375"
2364)
2365tg (CPTG
2366uid 2665,0
2367ps "CptPortTextPlaceStrategy"
2368stg "VerticalLayoutStrategy"
2369f (Text
2370uid 2666,0
2371va (VaSet
2372)
2373xt "82000,77500,90100,78500"
2374st "FTM_RS485_rx_d"
2375blo "82000,78300"
2376)
2377)
2378thePort (LogicalPort
2379decl (Decl
2380n "FTM_RS485_rx_d"
2381t "std_logic"
2382o 3
2383suid 99,0
2384)
2385)
2386)
2387*59 (CptPort
2388uid 2667,0
2389ps "OnEdgeStrategy"
2390shape (Triangle
2391uid 2668,0
2392ro 90
2393va (VaSet
2394vasetType 1
2395fg "0,65535,0"
2396)
2397xt "109000,83625,109750,84375"
2398)
2399tg (CPTG
2400uid 2669,0
2401ps "CptPortTextPlaceStrategy"
2402stg "RightVerticalLayoutStrategy"
2403f (Text
2404uid 2670,0
2405va (VaSet
2406)
2407xt "99600,83500,108000,84500"
2408st "FTM_RS485_rx_en"
2409ju 2
2410blo "108000,84300"
2411)
2412)
2413thePort (LogicalPort
2414m 1
2415decl (Decl
2416n "FTM_RS485_rx_en"
2417t "std_logic"
2418o 20
2419suid 101,0
2420)
2421)
2422)
2423*60 (CptPort
2424uid 2671,0
2425ps "OnEdgeStrategy"
2426shape (Triangle
2427uid 2672,0
2428ro 90
2429va (VaSet
2430vasetType 1
2431fg "0,65535,0"
2432)
2433xt "109000,84625,109750,85375"
2434)
2435tg (CPTG
2436uid 2673,0
2437ps "CptPortTextPlaceStrategy"
2438stg "RightVerticalLayoutStrategy"
2439f (Text
2440uid 2674,0
2441va (VaSet
2442)
2443xt "99900,84500,108000,85500"
2444st "FTM_RS485_tx_d"
2445ju 2
2446blo "108000,85300"
2447)
2448)
2449thePort (LogicalPort
2450m 1
2451decl (Decl
2452n "FTM_RS485_tx_d"
2453t "std_logic"
2454o 21
2455suid 100,0
2456)
2457)
2458)
2459*61 (CptPort
2460uid 2675,0
2461ps "OnEdgeStrategy"
2462shape (Triangle
2463uid 2676,0
2464ro 90
2465va (VaSet
2466vasetType 1
2467fg "0,65535,0"
2468)
2469xt "109000,85625,109750,86375"
2470)
2471tg (CPTG
2472uid 2677,0
2473ps "CptPortTextPlaceStrategy"
2474stg "RightVerticalLayoutStrategy"
2475f (Text
2476uid 2678,0
2477va (VaSet
2478)
2479xt "99600,85500,108000,86500"
2480st "FTM_RS485_tx_en"
2481ju 2
2482blo "108000,86300"
2483)
2484)
2485thePort (LogicalPort
2486m 1
2487decl (Decl
2488n "FTM_RS485_tx_en"
2489t "std_logic"
2490o 22
2491suid 102,0
2492)
2493)
2494)
2495*62 (CptPort
2496uid 2679,0
2497ps "OnEdgeStrategy"
2498shape (Triangle
2499uid 2680,0
2500ro 90
2501va (VaSet
2502vasetType 1
2503fg "0,65535,0"
2504)
2505xt "109000,86625,109750,87375"
2506)
2507tg (CPTG
2508uid 2681,0
2509ps "CptPortTextPlaceStrategy"
2510stg "RightVerticalLayoutStrategy"
2511f (Text
2512uid 2682,0
2513va (VaSet
2514)
2515xt "96600,86500,108000,87500"
2516st "mem_manager_state : (3:0)"
2517ju 2
2518blo "108000,87300"
2519)
2520)
2521thePort (LogicalPort
2522lang 2
2523m 1
2524decl (Decl
2525n "mem_manager_state"
2526t "std_logic_vector"
2527b "(3 DOWNTO 0)"
2528eolc "-- state is encoded here ... useful for debugging."
2529posAdd 0
2530o 39
2531suid 106,0
2532)
2533)
2534)
2535*63 (CptPort
2536uid 2683,0
2537ps "OnEdgeStrategy"
2538shape (Triangle
2539uid 2684,0
2540ro 90
2541va (VaSet
2542vasetType 1
2543fg "0,65535,0"
2544)
2545xt "109000,87625,109750,88375"
2546)
2547tg (CPTG
2548uid 2685,0
2549ps "CptPortTextPlaceStrategy"
2550stg "RightVerticalLayoutStrategy"
2551f (Text
2552uid 2686,0
2553va (VaSet
2554)
2555xt "102400,87500,108000,88500"
2556st "trigger_veto"
2557ju 2
2558blo "108000,88300"
2559)
2560)
2561thePort (LogicalPort
2562m 1
2563decl (Decl
2564n "trigger_veto"
2565t "std_logic"
2566o 45
2567suid 98,0
2568i "'1'"
2569)
2570)
2571)
2572*64 (CptPort
2573uid 2687,0
2574ps "OnEdgeStrategy"
2575shape (Triangle
2576uid 2688,0
2577ro 90
2578va (VaSet
2579vasetType 1
2580fg "0,65535,0"
2581)
2582xt "109000,88625,109750,89375"
2583)
2584tg (CPTG
2585uid 2689,0
2586ps "CptPortTextPlaceStrategy"
2587stg "RightVerticalLayoutStrategy"
2588f (Text
2589uid 2690,0
2590va (VaSet
2591)
2592xt "99600,88500,108000,89500"
2593st "w5300_state : (7:0)"
2594ju 2
2595blo "108000,89300"
2596)
2597)
2598thePort (LogicalPort
2599m 1
2600decl (Decl
2601n "w5300_state"
2602t "std_logic_vector"
2603b "(7 DOWNTO 0)"
2604eolc "-- state is encoded here ... useful for debugging."
2605posAdd 0
2606o 46
2607suid 103,0
2608)
2609)
2610)
2611*65 (CptPort
2612uid 2924,0
2613ps "OnEdgeStrategy"
2614shape (Triangle
2615uid 2925,0
2616ro 90
2617va (VaSet
2618vasetType 1
2619fg "0,65535,0"
2620)
2621xt "109000,89625,109750,90375"
2622)
2623tg (CPTG
2624uid 2926,0
2625ps "CptPortTextPlaceStrategy"
2626stg "RightVerticalLayoutStrategy"
2627f (Text
2628uid 2927,0
2629va (VaSet
2630)
2631xt "96100,89500,108000,90500"
2632st "socket_tx_free_out : (16:0)"
2633ju 2
2634blo "108000,90300"
2635)
2636)
2637thePort (LogicalPort
2638m 1
2639decl (Decl
2640n "socket_tx_free_out"
2641t "std_logic_vector"
2642b "(16 DOWNTO 0)"
2643eolc "-- 17bit value .. that's true"
2644posAdd 0
2645o 44
2646suid 109,0
2647)
2648)
2649)
2650]
2651shape (Rectangle
2652uid 234,0
2653va (VaSet
2654vasetType 1
2655fg "0,65535,0"
2656lineColor "0,32896,0"
2657lineWidth 2
2658)
2659xt "81000,19000,109000,91000"
2660)
2661oxt "15000,-8000,43000,46000"
2662ttg (MlTextGroup
2663uid 235,0
2664ps "CenterOffsetStrategy"
2665stg "VerticalLayoutStrategy"
2666textVec [
2667*66 (Text
2668uid 236,0
2669va (VaSet
2670font "Arial,8,1"
2671)
2672xt "83200,81000,89400,82000"
2673st "FACT_FAD_lib"
2674blo "83200,81800"
2675tm "BdLibraryNameMgr"
2676)
2677*67 (Text
2678uid 237,0
2679va (VaSet
2680font "Arial,8,1"
2681)
2682xt "83200,82000,87400,83000"
2683st "FAD_main"
2684blo "83200,82800"
2685tm "CptNameMgr"
2686)
2687*68 (Text
2688uid 238,0
2689va (VaSet
2690font "Arial,8,1"
2691)
2692xt "83200,83000,90000,84000"
2693st "I_mainTB_FPGA"
2694blo "83200,83800"
2695tm "InstanceNameMgr"
2696)
2697]
2698)
2699ga (GenericAssociation
2700uid 239,0
2701ps "EdgeToEdgeStrategy"
2702matrix (Matrix
2703uid 240,0
2704text (MLText
2705uid 241,0
2706va (VaSet
2707font "Courier New,8,0"
2708)
2709xt "81000,18200,101000,19000"
2710st "RAMADDRWIDTH64b = 15    ( integer )  "
2711)
2712header ""
2713)
2714elements [
2715(GiElement
2716name "RAMADDRWIDTH64b"
2717type "integer"
2718value "15"
2719)
2720]
2721)
2722viewicon (ZoomableIcon
2723uid 242,0
2724sl 0
2725va (VaSet
2726vasetType 1
2727fg "49152,49152,49152"
2728)
2729xt "81250,89250,82750,90750"
2730iconName "BlockDiagram.png"
2731iconMaskName "BlockDiagram.msk"
2732ftype 1
2733)
2734viewiconposition 0
2735portVis (PortSigDisplay
2736)
2737archFileType "UNKNOWN"
2738)
2739*69 (SaComponent
2740uid 274,0
2741optionalChildren [
2742*70 (CptPort
2743uid 266,0
2744ps "OnEdgeStrategy"
2745shape (Triangle
2746uid 267,0
2747ro 90
2748va (VaSet
2749vasetType 1
2750fg "0,65535,0"
2751)
2752xt "58000,20625,58750,21375"
2753)
2754tg (CPTG
2755uid 268,0
2756ps "CptPortTextPlaceStrategy"
2757stg "RightVerticalLayoutStrategy"
2758f (Text
2759uid 269,0
2760va (VaSet
2761)
2762xt "55700,20500,57000,21500"
2763st "clk"
2764ju 2
2765blo "57000,21300"
2766)
2767)
2768thePort (LogicalPort
2769m 1
2770decl (Decl
2771n "clk"
2772t "STD_LOGIC"
2773o 1
2774i "'0'"
2775)
2776)
2777)
2778*71 (CptPort
2779uid 270,0
2780ps "OnEdgeStrategy"
2781shape (Triangle
2782uid 271,0
2783ro 90
2784va (VaSet
2785vasetType 1
2786fg "0,65535,0"
2787)
2788xt "58000,21625,58750,22375"
2789)
2790tg (CPTG
2791uid 272,0
2792ps "CptPortTextPlaceStrategy"
2793stg "RightVerticalLayoutStrategy"
2794f (Text
2795uid 273,0
2796va (VaSet
2797)
2798xt "55700,21500,57000,22500"
2799st "rst"
2800ju 2
2801blo "57000,22300"
2802)
2803)
2804thePort (LogicalPort
2805m 1
2806decl (Decl
2807n "rst"
2808t "STD_LOGIC"
2809o 2
2810i "'0'"
2811)
2812)
2813)
2814]
2815shape (Rectangle
2816uid 275,0
2817va (VaSet
2818vasetType 1
2819fg "0,49152,49152"
2820lineColor "0,0,50000"
2821lineWidth 2
2822)
2823xt "50000,19000,58000,24000"
2824)
2825oxt "0,0,8000,10000"
2826ttg (MlTextGroup
2827uid 276,0
2828ps "CenterOffsetStrategy"
2829stg "VerticalLayoutStrategy"
2830textVec [
2831*72 (Text
2832uid 277,0
2833va (VaSet
2834font "Arial,8,1"
2835)
2836xt "50150,24000,57850,25000"
2837st "FACT_FAD_TB_lib"
2838blo "50150,24800"
2839tm "BdLibraryNameMgr"
2840)
2841*73 (Text
2842uid 278,0
2843va (VaSet
2844font "Arial,8,1"
2845)
2846xt "50150,25000,56850,26000"
2847st "clock_generator"
2848blo "50150,25800"
2849tm "CptNameMgr"
2850)
2851*74 (Text
2852uid 279,0
2853va (VaSet
2854font "Arial,8,1"
2855)
2856xt "50150,26000,56750,27000"
2857st "I_mainTB_clock"
2858blo "50150,26800"
2859tm "InstanceNameMgr"
2860)
2861]
2862)
2863ga (GenericAssociation
2864uid 280,0
2865ps "EdgeToEdgeStrategy"
2866matrix (Matrix
2867uid 281,0
2868text (MLText
2869uid 282,0
2870va (VaSet
2871font "Courier New,8,0"
2872)
2873xt "50000,17400,68500,19000"
2874st "clock_period = 20 ns    ( time ) 
2875reset_time   = 50 ns    ( time )  "
2876)
2877header ""
2878)
2879elements [
2880(GiElement
2881name "clock_period"
2882type "time"
2883value "20 ns"
2884)
2885(GiElement
2886name "reset_time"
2887type "time"
2888value "50 ns"
2889)
2890]
2891)
2892viewicon (ZoomableIcon
2893uid 283,0
2894sl 0
2895va (VaSet
2896vasetType 1
2897fg "49152,49152,49152"
2898)
2899xt "50250,22250,51750,23750"
2900iconName "VhdlFileViewIcon.png"
2901iconMaskName "VhdlFileViewIcon.msk"
2902ftype 10
2903)
2904ordering 1
2905viewiconposition 0
2906portVis (PortSigDisplay
2907)
2908archFileType "UNKNOWN"
2909)
2910*75 (Net
2911uid 284,0
2912decl (Decl
2913n "clk"
2914t "STD_LOGIC"
2915preAdd 0
2916posAdd 0
2917o 1
2918suid 1,0
2919)
2920declText (MLText
2921uid 285,0
2922va (VaSet
2923font "Courier New,8,0"
2924)
2925xt "-90000,46200,-68000,47000"
2926st "SIGNAL clk                   : STD_LOGIC"
2927)
2928)
2929*76 (Net
2930uid 316,0
2931decl (Decl
2932n "wiz_addr"
2933t "std_logic_vector"
2934b "(9 DOWNTO 0)"
2935o 2
2936suid 2,0
2937)
2938declText (MLText
2939uid 317,0
2940va (VaSet
2941font "Courier New,8,0"
2942)
2943xt "-90000,63800,-58500,64600"
2944st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)"
2945)
2946)
2947*77 (Net
2948uid 322,0
2949decl (Decl
2950n "wiz_data"
2951t "std_logic_vector"
2952b "(15 DOWNTO 0)"
2953o 3
2954suid 3,0
2955)
2956declText (MLText
2957uid 323,0
2958va (VaSet
2959font "Courier New,8,0"
2960)
2961xt "-90000,65400,-58000,66200"
2962st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)"
2963)
2964)
2965*78 (Net
2966uid 328,0
2967decl (Decl
2968n "wiz_rd"
2969t "std_logic"
2970o 4
2971suid 4,0
2972i "'1'"
2973)
2974declText (MLText
2975uid 329,0
2976va (VaSet
2977font "Courier New,8,0"
2978)
2979xt "-90000,67000,-55000,67800"
2980st "SIGNAL wiz_rd                : std_logic                    := '1'"
2981)
2982)
2983*79 (Net
2984uid 334,0
2985decl (Decl
2986n "wiz_wr"
2987t "std_logic"
2988o 5
2989suid 5,0
2990i "'1'"
2991)
2992declText (MLText
2993uid 335,0
2994va (VaSet
2995font "Courier New,8,0"
2996)
2997xt "-90000,68600,-55000,69400"
2998st "SIGNAL wiz_wr                : std_logic                    := '1'"
2999)
3000)
3001*80 (SaComponent
3002uid 362,0
3003optionalChildren [
3004*81 (CptPort
3005uid 350,0
3006ps "OnEdgeStrategy"
3007shape (Triangle
3008uid 351,0
3009ro 90
3010va (VaSet
3011vasetType 1
3012fg "0,65535,0"
3013)
3014xt "122250,50625,123000,51375"
3015)
3016tg (CPTG
3017uid 352,0
3018ps "CptPortTextPlaceStrategy"
3019stg "VerticalLayoutStrategy"
3020f (Text
3021uid 353,0
3022va (VaSet
3023)
3024xt "124000,50500,125700,51500"
3025st "sclk"
3026blo "124000,51300"
3027)
3028)
3029thePort (LogicalPort
3030decl (Decl
3031n "sclk"
3032t "std_logic"
3033preAdd 0
3034posAdd 0
3035o 1
3036suid 1,0
3037)
3038)
3039)
3040*82 (CptPort
3041uid 354,0
3042ps "OnEdgeStrategy"
3043shape (Diamond
3044uid 355,0
3045ro 270
3046va (VaSet
3047vasetType 1
3048fg "0,65535,0"
3049)
3050xt "122250,51625,123000,52375"
3051)
3052tg (CPTG
3053uid 356,0
3054ps "CptPortTextPlaceStrategy"
3055stg "VerticalLayoutStrategy"
3056f (Text
3057uid 357,0
3058va (VaSet
3059)
3060xt "124000,51500,125400,52500"
3061st "sio"
3062blo "124000,52300"
3063)
3064)
3065thePort (LogicalPort
3066m 2
3067decl (Decl
3068n "sio"
3069t "std_logic"
3070preAdd 0
3071posAdd 0
3072o 2
3073suid 2,0
3074)
3075)
3076)
3077*83 (CptPort
3078uid 358,0
3079ps "OnEdgeStrategy"
3080shape (Triangle
3081uid 359,0
3082ro 90
3083va (VaSet
3084vasetType 1
3085fg "0,65535,0"
3086)
3087xt "122250,47625,123000,48375"
3088)
3089tg (CPTG
3090uid 360,0
3091ps "CptPortTextPlaceStrategy"
3092stg "VerticalLayoutStrategy"
3093f (Text
3094uid 361,0
3095va (VaSet
3096)
3097xt "124000,47500,130500,48500"
3098st "sensor_cs : (3:0)"
3099blo "124000,48300"
3100)
3101)
3102thePort (LogicalPort
3103decl (Decl
3104n "sensor_cs"
3105t "std_logic_vector"
3106b "(3 downto 0)"
3107preAdd 0
3108posAdd 0
3109o 3
3110suid 3,0
3111)
3112)
3113)
3114]
3115shape (Rectangle
3116uid 363,0
3117va (VaSet
3118vasetType 1
3119fg "0,49152,49152"
3120lineColor "0,0,50000"
3121lineWidth 2
3122)
3123xt "123000,46000,133000,56000"
3124)
3125oxt "30000,3000,40000,13000"
3126ttg (MlTextGroup
3127uid 364,0
3128ps "CenterOffsetStrategy"
3129stg "VerticalLayoutStrategy"
3130textVec [
3131*84 (Text
3132uid 365,0
3133va (VaSet
3134font "Arial,8,1"
3135)
3136xt "123200,56000,130900,57000"
3137st "FACT_FAD_TB_lib"
3138blo "123200,56800"
3139tm "BdLibraryNameMgr"
3140)
3141*85 (Text
3142uid 366,0
3143va (VaSet
3144font "Arial,8,1"
3145)
3146xt "123200,57000,130800,58000"
3147st "max6662_emulator"
3148blo "123200,57800"
3149tm "CptNameMgr"
3150)
3151*86 (Text
3152uid 367,0
3153va (VaSet
3154font "Arial,8,1"
3155)
3156xt "123200,58000,131000,59000"
3157st "I_mainTB_max6662"
3158blo "123200,58800"
3159tm "InstanceNameMgr"
3160)
3161]
3162)
3163ga (GenericAssociation
3164uid 368,0
3165ps "EdgeToEdgeStrategy"
3166matrix (Matrix
3167uid 369,0
3168text (MLText
3169uid 370,0
3170va (VaSet
3171font "Courier New,8,0"
3172)
3173xt "123000,45200,143000,46000"
3174st "DRS_TEMPERATURE = 51    ( integer )  "
3175)
3176header ""
3177)
3178elements [
3179(GiElement
3180name "DRS_TEMPERATURE"
3181type "integer"
3182value "51"
3183)
3184]
3185)
3186viewicon (ZoomableIcon
3187uid 371,0
3188sl 0
3189va (VaSet
3190vasetType 1
3191fg "49152,49152,49152"
3192)
3193xt "123250,54250,124750,55750"
3194iconName "VhdlFileViewIcon.png"
3195iconMaskName "VhdlFileViewIcon.msk"
3196ftype 10
3197)
3198ordering 1
3199viewiconposition 0
3200portVis (PortSigDisplay
3201sIVOD 1
3202)
3203archFileType "UNKNOWN"
3204)
3205*87 (Net
3206uid 372,0
3207decl (Decl
3208n "sensor_cs"
3209t "std_logic_vector"
3210b "(3 DOWNTO 0)"
3211o 6
3212suid 6,0
3213)
3214declText (MLText
3215uid 373,0
3216va (VaSet
3217font "Courier New,8,0"
3218)
3219xt "-90000,59000,-58500,59800"
3220st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
3221)
3222)
3223*88 (Net
3224uid 378,0
3225decl (Decl
3226n "sclk"
3227t "std_logic"
3228o 7
3229suid 7,0
3230)
3231declText (MLText
3232uid 379,0
3233va (VaSet
3234font "Courier New,8,0"
3235)
3236xt "-90000,58200,-68000,59000"
3237st "SIGNAL sclk                  : std_logic"
3238)
3239)
3240*89 (Net
3241uid 384,0
3242decl (Decl
3243n "sio"
3244t "std_logic"
3245preAdd 0
3246posAdd 0
3247o 8
3248suid 8,0
3249)
3250declText (MLText
3251uid 385,0
3252va (VaSet
3253font "Courier New,8,0"
3254)
3255xt "-90000,59800,-68000,60600"
3256st "SIGNAL sio                   : std_logic"
3257)
3258)
3259*90 (SaComponent
3260uid 414,0
3261optionalChildren [
3262*91 (CptPort
3263uid 410,0
3264ps "OnEdgeStrategy"
3265shape (Triangle
3266uid 411,0
3267ro 90
3268va (VaSet
3269vasetType 1
3270fg "0,65535,0"
3271)
3272xt "58000,31625,58750,32375"
3273)
3274tg (CPTG
3275uid 412,0
3276ps "CptPortTextPlaceStrategy"
3277stg "RightVerticalLayoutStrategy"
3278f (Text
3279uid 413,0
3280va (VaSet
3281)
3282xt "54200,31500,57000,32500"
3283st "trigger"
3284ju 2
3285blo "57000,32300"
3286)
3287)
3288thePort (LogicalPort
3289m 1
3290decl (Decl
3291n "trigger"
3292t "std_logic"
3293preAdd 0
3294posAdd 0
3295o 1
3296suid 1,0
3297)
3298)
3299)
3300]
3301shape (Rectangle
3302uid 415,0
3303va (VaSet
3304vasetType 1
3305fg "0,49152,49152"
3306lineColor "0,0,50000"
3307lineWidth 2
3308)
3309xt "50000,30000,58000,36000"
3310)
3311oxt "19000,4000,29000,14000"
3312ttg (MlTextGroup
3313uid 416,0
3314ps "CenterOffsetStrategy"
3315stg "VerticalLayoutStrategy"
3316textVec [
3317*92 (Text
3318uid 417,0
3319va (VaSet
3320font "Arial,8,1"
3321)
3322xt "50200,36000,57900,37000"
3323st "FACT_FAD_TB_lib"
3324blo "50200,36800"
3325tm "BdLibraryNameMgr"
3326)
3327*93 (Text
3328uid 418,0
3329va (VaSet
3330font "Arial,8,1"
3331)
3332xt "50200,37000,57500,38000"
3333st "trigger_generator"
3334blo "50200,37800"
3335tm "CptNameMgr"
3336)
3337*94 (Text
3338uid 419,0
3339va (VaSet
3340font "Arial,8,1"
3341)
3342xt "50200,38000,57400,39000"
3343st "I_mainTB_trigger"
3344blo "50200,38800"
3345tm "InstanceNameMgr"
3346)
3347]
3348)
3349ga (GenericAssociation
3350uid 420,0
3351ps "EdgeToEdgeStrategy"
3352matrix (Matrix
3353uid 421,0
3354text (MLText
3355uid 422,0
3356va (VaSet
3357font "Courier New,8,0"
3358)
3359xt "50000,28400,68500,30000"
3360st "TRIGGER_RATE = 1 ms     ( time ) 
3361PULSE_WIDTH  = 20 ns    ( time )  "
3362)
3363header ""
3364)
3365elements [
3366(GiElement
3367name "TRIGGER_RATE"
3368type "time"
3369value "1 ms"
3370)
3371(GiElement
3372name "PULSE_WIDTH"
3373type "time"
3374value "20 ns"
3375)
3376]
3377)
3378viewicon (ZoomableIcon
3379uid 423,0
3380sl 0
3381va (VaSet
3382vasetType 1
3383fg "49152,49152,49152"
3384)
3385xt "50250,34250,51750,35750"
3386iconName "VhdlFileViewIcon.png"
3387iconMaskName "VhdlFileViewIcon.msk"
3388ftype 10
3389)
3390ordering 1
3391viewiconposition 0
3392portVis (PortSigDisplay
3393sIVOD 1
3394)
3395archFileType "UNKNOWN"
3396)
3397*95 (Net
3398uid 424,0
3399decl (Decl
3400n "trigger"
3401t "std_logic"
3402preAdd 0
3403posAdd 0
3404o 9
3405suid 9,0
3406)
3407declText (MLText
3408uid 425,0
3409va (VaSet
3410font "Courier New,8,0"
3411)
3412xt "-90000,61400,-68000,62200"
3413st "SIGNAL trigger               : std_logic"
3414)
3415)
3416*96 (HdlText
3417uid 430,0
3418optionalChildren [
3419*97 (EmbeddedText
3420uid 436,0
3421commentText (CommentText
3422uid 437,0
3423ps "CenterOffsetStrategy"
3424shape (Rectangle
3425uid 438,0
3426va (VaSet
3427vasetType 1
3428fg "65535,65535,65535"
3429lineColor "0,0,32768"
3430lineWidth 2
3431)
3432xt "50000,45000,60000,49000"
3433)
3434oxt "0,0,18000,5000"
3435text (MLText
3436uid 439,0
3437va (VaSet
3438)
3439xt "50200,45200,60200,48200"
3440st "
3441-- eb_ID 1: hard-wired IDs
3442board_id <= \"0101\";
3443crate_id <= \"01\";
3444
3445"
3446tm "HdlTextMgr"
3447wrapOption 3
3448visibleHeight 4000
3449visibleWidth 10000
3450)
3451)
3452)
3453]
3454shape (Rectangle
3455uid 431,0
3456va (VaSet
3457vasetType 1
3458fg "65535,65535,37120"
3459lineColor "0,0,32768"
3460lineWidth 2
3461)
3462xt "50000,40000,58000,45000"
3463)
3464oxt "0,0,8000,10000"
3465ttg (MlTextGroup
3466uid 432,0
3467ps "CenterOffsetStrategy"
3468stg "VerticalLayoutStrategy"
3469textVec [
3470*98 (Text
3471uid 433,0
3472va (VaSet
3473font "Arial,8,1"
3474)
3475xt "51150,41000,57350,42000"
3476st "eb_mainTB_ID"
3477blo "51150,41800"
3478tm "HdlTextNameMgr"
3479)
3480*99 (Text
3481uid 434,0
3482va (VaSet
3483font "Arial,8,1"
3484)
3485xt "51150,42000,51950,43000"
3486st "1"
3487blo "51150,42800"
3488tm "HdlTextNumberMgr"
3489)
3490]
3491)
3492viewicon (ZoomableIcon
3493uid 435,0
3494sl 0
3495va (VaSet
3496vasetType 1
3497fg "49152,49152,49152"
3498)
3499xt "50250,43250,51750,44750"
3500iconName "TextFile.png"
3501iconMaskName "TextFile.msk"
3502ftype 21
3503)
3504viewiconposition 0
3505)
3506*100 (Net
3507uid 440,0
3508decl (Decl
3509n "board_id"
3510t "std_logic_vector"
3511b "(3 downto 0)"
3512preAdd 0
3513posAdd 0
3514o 10
3515suid 10,0
3516)
3517declText (MLText
3518uid 441,0
3519va (VaSet
3520font "Courier New,8,0"
3521)
3522xt "-90000,45400,-58500,46200"
3523st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
3524)
3525)
3526*101 (Net
3527uid 448,0
3528decl (Decl
3529n "crate_id"
3530t "std_logic_vector"
3531b "(1 downto 0)"
3532o 11
3533suid 11,0
3534)
3535declText (MLText
3536uid 449,0
3537va (VaSet
3538font "Courier New,8,0"
3539)
3540xt "-90000,47800,-58500,48600"
3541st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
3542)
3543)
3544*102 (SaComponent
3545uid 508,0
3546optionalChildren [
3547*103 (CptPort
3548uid 489,0
3549ps "OnEdgeStrategy"
3550shape (Triangle
3551uid 490,0
3552ro 90
3553va (VaSet
3554vasetType 1
3555fg "0,65535,0"
3556)
3557xt "29250,52625,30000,53375"
3558)
3559tg (CPTG
3560uid 491,0
3561ps "CptPortTextPlaceStrategy"
3562stg "VerticalLayoutStrategy"
3563f (Text
3564uid 492,0
3565va (VaSet
3566)
3567xt "31000,52500,32300,53500"
3568st "clk"
3569blo "31000,53300"
3570)
3571)
3572thePort (LogicalPort
3573decl (Decl
3574n "clk"
3575t "STD_LOGIC"
3576preAdd 0
3577posAdd 0
3578o 1
3579suid 1,0
3580)
3581)
3582)
3583*104 (CptPort
3584uid 493,0
3585ps "OnEdgeStrategy"
3586shape (Triangle
3587uid 494,0
3588ro 90
3589va (VaSet
3590vasetType 1
3591fg "0,65535,0"
3592)
3593xt "40000,54625,40750,55375"
3594)
3595tg (CPTG
3596uid 495,0
3597ps "CptPortTextPlaceStrategy"
3598stg "RightVerticalLayoutStrategy"
3599f (Text
3600uid 496,0
3601va (VaSet
3602)
3603xt "34200,54500,39000,55500"
3604st "data : (11:0)"
3605ju 2
3606blo "39000,55300"
3607)
3608)
3609thePort (LogicalPort
3610m 1
3611decl (Decl
3612n "data"
3613t "STD_LOGIC_VECTOR"
3614b "(11 DOWNTO 0)"
3615preAdd 0
3616posAdd 0
3617o 2
3618suid 2,0
3619)
3620)
3621)
3622*105 (CptPort
3623uid 497,0
3624ps "OnEdgeStrategy"
3625shape (Triangle
3626uid 498,0
3627ro 90
3628va (VaSet
3629vasetType 1
3630fg "0,65535,0"
3631)
3632xt "40000,52625,40750,53375"
3633)
3634tg (CPTG
3635uid 499,0
3636ps "CptPortTextPlaceStrategy"
3637stg "RightVerticalLayoutStrategy"
3638f (Text
3639uid 500,0
3640va (VaSet
3641)
3642xt "37700,52500,39000,53500"
3643st "otr"
3644ju 2
3645blo "39000,53300"
3646)
3647)
3648thePort (LogicalPort
3649m 1
3650decl (Decl
3651n "otr"
3652t "STD_LOGIC"
3653preAdd 0
3654posAdd 0
3655o 3
3656suid 3,0
3657)
3658)
3659)
3660*106 (CptPort
3661uid 501,0
3662ps "OnEdgeStrategy"
3663shape (Triangle
3664uid 502,0
3665ro 270
3666va (VaSet
3667vasetType 1
3668fg "0,65535,0"
3669)
3670xt "40000,53625,40750,54375"
3671)
3672tg (CPTG
3673uid 503,0
3674ps "CptPortTextPlaceStrategy"
3675stg "RightVerticalLayoutStrategy"
3676f (Text
3677uid 504,0
3678va (VaSet
3679)
3680xt "37400,53500,39000,54500"
3681st "oeb"
3682ju 2
3683blo "39000,54300"
3684)
3685)
3686thePort (LogicalPort
3687decl (Decl
3688n "oeb"
3689t "STD_LOGIC"
3690preAdd 0
3691posAdd 0
3692o 4
3693suid 4,0
3694)
3695)
3696)
3697]
3698shape (Rectangle
3699uid 509,0
3700va (VaSet
3701vasetType 1
3702fg "0,49152,49152"
3703lineColor "0,0,50000"
3704lineWidth 2
3705)
3706xt "30000,51000,40000,58000"
3707)
3708oxt "29000,7000,39000,17000"
3709ttg (MlTextGroup
3710uid 510,0
3711ps "CenterOffsetStrategy"
3712stg "VerticalLayoutStrategy"
3713textVec [
3714*107 (Text
3715uid 511,0
3716va (VaSet
3717font "Arial,8,1"
3718)
3719xt "30200,58000,37900,59000"
3720st "FACT_FAD_TB_lib"
3721blo "30200,58800"
3722tm "BdLibraryNameMgr"
3723)
3724*108 (Text
3725uid 512,0
3726va (VaSet
3727font "Arial,8,1"
3728)
3729xt "30200,59000,36000,60000"
3730st "adc_emulator"
3731blo "30200,59800"
3732tm "CptNameMgr"
3733)
3734*109 (Text
3735uid 513,0
3736va (VaSet
3737font "Arial,8,1"
3738)
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3813-- eb_adc 2: ADC routing
3814adc_data_array(0) <= adc_data;
3815adc_data_array(1) <= adc_data;
3816adc_data_array(2) <= adc_data;
3817adc_data_array(3) <= adc_data;
3818adc_otr_array(0) <= adc_otr;
3819adc_otr_array(1) <= adc_otr;
3820adc_otr_array(2) <= adc_otr;
3821adc_otr_array(3) <= adc_otr;
3822
3823"
3824tm "HdlTextMgr"
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3885uid 528,0
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3902*115 (Net
3903uid 536,0
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3905n "adc_data_array"
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3922n "adc_oeb"
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3936)
3937)
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3939uid 560,0
3940decl (Decl
3941n "adc_otr"
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3944posAdd 0
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3955)
3956)
3957*118 (Net
3958uid 568,0
3959decl (Decl
3960n "adc_data"
3961t "std_logic_vector"
3962b "(11 DOWNTO 0)"
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3975)
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3993)
3994)
3995*120 (Net
3996uid 775,0
3997decl (Decl
3998n "led"
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4002o 22
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4013)
4014)
4015*121 (Net
4016uid 783,0
4017decl (Decl
4018n "wiz_cs"
4019t "std_logic"
4020o 23
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4031)
4032)
4033*122 (Net
4034uid 791,0
4035decl (Decl
4036n "wiz_int"
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4048)
4049)
4050*123 (Net
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4052decl (Decl
4053n "dac_cs"
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4065)
4066)
4067*124 (Net
4068uid 807,0
4069decl (Decl
4070n "mosi"
4071t "std_logic"
4072o 26
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4082st "SIGNAL mosi                  : std_logic                    := '0'"
4083)
4084)
4085*125 (Net
4086uid 815,0
4087decl (Decl
4088n "denable"
4089t "std_logic"
4090eolc "-- default domino wave off"
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4092o 27
4093suid 29,0
4094i "'0'"
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4102st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off"
4103)
4104)
4105*126 (Net
4106uid 823,0
4107decl (Decl
4108n "CLK_25_PS"
4109t "std_logic"
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4120)
4121)
4122*127 (Net
4123uid 831,0
4124decl (Decl
4125n "CLK_50"
4126t "std_logic"
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4139*128 (Net
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4141decl (Decl
4142n "drs_channel_id"
4143t "std_logic_vector"
4144b "(3 downto 0)"
4145o 30
4146suid 32,0
4147i "(others => '0')"
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4156)
4157)
4158*129 (Net
4159uid 847,0
4160decl (Decl
4161n "drs_dwrite"
4162t "std_logic"
4163o 31
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4173st "SIGNAL drs_dwrite            : std_logic                    := '1'"
4174)
4175)
4176*130 (Net
4177uid 855,0
4178decl (Decl
4179n "RSRLOAD"
4180t "std_logic"
4181o 32
4182suid 34,0
4183i "'0'"
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4191st "SIGNAL RSRLOAD               : std_logic                    := '0'"
4192)
4193)
4194*131 (Net
4195uid 863,0
4196decl (Decl
4197n "SRCLK"
4198t "std_logic"
4199o 33
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4209st "SIGNAL SRCLK                 : std_logic                    := '0'"
4210)
4211)
4212*132 (Net
4213uid 871,0
4214decl (Decl
4215n "SROUT_in_0"
4216t "std_logic"
4217o 30
4218suid 36,0
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4227)
4228)
4229*133 (Net
4230uid 879,0
4231decl (Decl
4232n "SROUT_in_1"
4233t "std_logic"
4234o 31
4235suid 37,0
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4243st "SIGNAL SROUT_in_1            : std_logic"
4244)
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4246*134 (Net
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4248decl (Decl
4249n "SROUT_in_2"
4250t "std_logic"
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4260st "SIGNAL SROUT_in_2            : std_logic"
4261)
4262)
4263*135 (Net
4264uid 895,0
4265decl (Decl
4266n "SROUT_in_3"
4267t "std_logic"
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4278)
4279)
4280*136 (Net
4281uid 1435,0
4282decl (Decl
4283n "SRIN_out"
4284t "std_logic"
4285o 34
4286suid 40,0
4287i "'0'"
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4292font "Courier New,8,0"
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4295st "SIGNAL SRIN_out              : std_logic                    := '0'"
4296)
4297)
4298*137 (Net
4299uid 1443,0
4300decl (Decl
4301n "amber"
4302t "std_logic"
4303o 35
4304suid 41,0
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4308va (VaSet
4309font "Courier New,8,0"
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4311xt "-90000,44600,-68000,45400"
4312st "SIGNAL amber                 : std_logic"
4313)
4314)
4315*138 (Net
4316uid 1451,0
4317decl (Decl
4318n "red"
4319t "std_logic"
4320o 36
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4325va (VaSet
4326font "Courier New,8,0"
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4328xt "-90000,57400,-68000,58200"
4329st "SIGNAL red                   : std_logic"
4330)
4331)
4332*139 (Net
4333uid 1459,0
4334decl (Decl
4335n "green"
4336t "std_logic"
4337o 37
4338suid 43,0
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4342va (VaSet
4343font "Courier New,8,0"
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4346st "SIGNAL green                 : std_logic"
4347)
4348)
4349*140 (Net
4350uid 1467,0
4351decl (Decl
4352n "counter_result"
4353t "std_logic_vector"
4354b "(11 DOWNTO 0)"
4355o 38
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4364st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
4365)
4366)
4367*141 (Net
4368uid 1475,0
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4370n "alarm_refclk_too_low"
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4386uid 1483,0
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4388n "alarm_refclk_too_high"
4389t "std_logic"
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4391suid 46,0
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4418xt "27000,72000,41000,77000"
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4420oxt "0,0,18000,5000"
4421text (MLText
4422uid 1500,0
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4425xt "27200,72200,39400,77200"
4426st "
4427
4428D_T_in(1 downto 0) <= \"00\";
4429plllock_in(3 downto 0) <= \"1111\";
4430SROUT_in_0 <= '1';
4431SROUT_in_1 <= '0';
4432SROUT_in_2 <= '1';
4433SROUT_in_3 <= '0';
4434
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4436tm "HdlTextMgr"
4437wrapOption 3
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4465xt "28150,69000,35250,70000"
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4467blo "28150,69800"
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4477blo "28150,70800"
4478tm "HdlTextNumberMgr"
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4484sl 0
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4499n "D_T_in"
4500t "std_logic_vector"
4501b "(1 DOWNTO 0)"
4502o 41
4503suid 47,0
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4507va (VaSet
4508font "Courier New,8,0"
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4510xt "-90000,28600,-58500,29400"
4511st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
4512)
4513)
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4516optionalChildren [
4517*149 (CptPort
4518uid 1519,0
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4520shape (Triangle
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4522ro 90
4523va (VaSet
4524vasetType 1
4525fg "0,65535,0"
4526)
4527xt "66000,78625,66750,79375"
4528)
4529tg (CPTG
4530uid 1521,0
4531ps "CptPortTextPlaceStrategy"
4532stg "RightVerticalLayoutStrategy"
4533f (Text
4534uid 1522,0
4535va (VaSet
4536)
4537xt "63700,78500,65000,79500"
4538st "clk"
4539ju 2
4540blo "65000,79300"
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4542)
4543thePort (LogicalPort
4544m 1
4545decl (Decl
4546n "clk"
4547t "STD_LOGIC"
4548o 1
4549i "'0'"
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4552)
4553*150 (CptPort
4554uid 1523,0
4555ps "OnEdgeStrategy"
4556shape (Triangle
4557uid 1524,0
4558ro 90
4559va (VaSet
4560vasetType 1
4561fg "0,65535,0"
4562)
4563xt "66000,79625,66750,80375"
4564)
4565tg (CPTG
4566uid 1525,0
4567ps "CptPortTextPlaceStrategy"
4568stg "RightVerticalLayoutStrategy"
4569f (Text
4570uid 1526,0
4571va (VaSet
4572)
4573xt "63700,79500,65000,80500"
4574st "rst"
4575ju 2
4576blo "65000,80300"
4577)
4578)
4579thePort (LogicalPort
4580m 1
4581decl (Decl
4582n "rst"
4583t "STD_LOGIC"
4584o 2
4585i "'0'"
4586)
4587)
4588)
4589]
4590shape (Rectangle
4591uid 1510,0
4592va (VaSet
4593vasetType 1
4594fg "0,49152,49152"
4595lineColor "0,0,50000"
4596lineWidth 2
4597)
4598xt "55000,77000,66000,82000"
4599)
4600oxt "0,0,8000,10000"
4601ttg (MlTextGroup
4602uid 1511,0
4603ps "CenterOffsetStrategy"
4604stg "VerticalLayoutStrategy"
4605textVec [
4606*151 (Text
4607uid 1512,0
4608va (VaSet
4609font "Arial,8,1"
4610)
4611xt "56150,78000,63850,79000"
4612st "FACT_FAD_TB_lib"
4613blo "56150,78800"
4614tm "BdLibraryNameMgr"
4615)
4616*152 (Text
4617uid 1513,0
4618va (VaSet
4619font "Arial,8,1"
4620)
4621xt "56150,79000,62850,80000"
4622st "clock_generator"
4623blo "56150,79800"
4624tm "CptNameMgr"
4625)
4626*153 (Text
4627uid 1514,0
4628va (VaSet
4629font "Arial,8,1"
4630)
4631xt "56150,80000,63150,81000"
4632st "I_mainTB_clock1"
4633blo "56150,80800"
4634tm "InstanceNameMgr"
4635)
4636]
4637)
4638ga (GenericAssociation
4639uid 1515,0
4640ps "EdgeToEdgeStrategy"
4641matrix (Matrix
4642uid 1516,0
4643text (MLText
4644uid 1517,0
4645va (VaSet
4646font "Courier New,8,0"
4647)
4648xt "55000,82400,73000,84000"
4649st "clock_period = 1 us    ( time ) 
4650reset_time   = 1 us    ( time )  "
4651)
4652header ""
4653)
4654elements [
4655(GiElement
4656name "clock_period"
4657type "time"
4658value "1 us"
4659)
4660(GiElement
4661name "reset_time"
4662type "time"
4663value "1 us"
4664)
4665]
4666)
4667viewicon (ZoomableIcon
4668uid 1518,0
4669sl 0
4670va (VaSet
4671vasetType 1
4672fg "49152,49152,49152"
4673)
4674xt "55250,80250,56750,81750"
4675iconName "VhdlFileViewIcon.png"
4676iconMaskName "VhdlFileViewIcon.msk"
4677ftype 10
4678)
4679ordering 1
4680viewiconposition 0
4681portVis (PortSigDisplay
4682)
4683archFileType "UNKNOWN"
4684)
4685*154 (Net
4686uid 1559,0
4687decl (Decl
4688n "plllock_in"
4689t "std_logic_vector"
4690b "(3 DOWNTO 0)"
4691eolc "-- high level, if dominowave is running and DRS PLL locked"
4692o 43
4693suid 49,0
4694)
4695declText (MLText
4696uid 1560,0
4697va (VaSet
4698font "Courier New,8,0"
4699)
4700xt "-90000,56600,-29000,57400"
4701st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
4702)
4703)
4704*155 (Net
4705uid 1682,0
4706lang 2
4707decl (Decl
4708n "ADC_CLK"
4709t "std_logic"
4710o 44
4711suid 50,0
4712)
4713declText (MLText
4714uid 1683,0
4715va (VaSet
4716font "Courier New,8,0"
4717)
4718xt "-90000,24600,-68000,25400"
4719st "SIGNAL ADC_CLK               : std_logic"
4720)
4721)
4722*156 (Net
4723uid 2001,0
4724decl (Decl
4725n "REF_CLK"
4726t "STD_LOGIC"
4727o 42
4728suid 51,0
4729i "'0'"
4730)
4731declText (MLText
4732uid 2002,0
4733va (VaSet
4734font "Courier New,8,0"
4735)
4736xt "-90000,32600,-55000,33400"
4737st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'"
4738)
4739)
4740*157 (SaComponent
4741uid 2336,0
4742optionalChildren [
4743*158 (CptPort
4744uid 2315,0
4745ps "OnEdgeStrategy"
4746shape (Triangle
4747uid 2316,0
4748ro 90
4749va (VaSet
4750vasetType 1
4751fg "0,65535,0"
4752)
4753xt "122250,20625,123000,21375"
4754)
4755tg (CPTG
4756uid 2317,0
4757ps "CptPortTextPlaceStrategy"
4758stg "VerticalLayoutStrategy"
4759f (Text
4760uid 2318,0
4761va (VaSet
4762)
4763xt "124000,20500,129100,21500"
4764st "addr : (9:0)"
4765blo "124000,21300"
4766)
4767)
4768thePort (LogicalPort
4769decl (Decl
4770n "addr"
4771t "std_logic_vector"
4772b "(9 DOWNTO 0)"
4773preAdd 0
4774posAdd 0
4775o 2
4776suid 1,0
4777)
4778)
4779)
4780*159 (CptPort
4781uid 2319,0
4782ps "OnEdgeStrategy"
4783shape (Diamond
4784uid 2320,0
4785ro 270
4786va (VaSet
4787vasetType 1
4788fg "0,65535,0"
4789)
4790xt "122250,21625,123000,22375"
4791)
4792tg (CPTG
4793uid 2321,0
4794ps "CptPortTextPlaceStrategy"
4795stg "VerticalLayoutStrategy"
4796f (Text
4797uid 2322,0
4798va (VaSet
4799)
4800xt "124000,21500,129400,22500"
4801st "data : (15:0)"
4802blo "124000,22300"
4803)
4804)
4805thePort (LogicalPort
4806m 2
4807decl (Decl
4808n "data"
4809t "std_logic_vector"
4810b "(15 DOWNTO 0)"
4811preAdd 0
4812posAdd 0
4813o 3
4814suid 2,0
4815)
4816)
4817)
4818*160 (CptPort
4819uid 2323,0
4820ps "OnEdgeStrategy"
4821shape (Triangle
4822uid 2324,0
4823ro 90
4824va (VaSet
4825vasetType 1
4826fg "0,65535,0"
4827)
4828xt "122250,24625,123000,25375"
4829)
4830tg (CPTG
4831uid 2325,0
4832ps "CptPortTextPlaceStrategy"
4833stg "VerticalLayoutStrategy"
4834f (Text
4835uid 2326,0
4836va (VaSet
4837)
4838xt "124000,24500,125300,25500"
4839st "rd"
4840blo "124000,25300"
4841)
4842)
4843thePort (LogicalPort
4844decl (Decl
4845n "rd"
4846t "std_logic"
4847preAdd 0
4848posAdd 0
4849o 4
4850suid 3,0
4851)
4852)
4853)
4854*161 (CptPort
4855uid 2327,0
4856ps "OnEdgeStrategy"
4857shape (Triangle
4858uid 2328,0
4859ro 90
4860va (VaSet
4861vasetType 1
4862fg "0,65535,0"
4863)
4864xt "122250,25625,123000,26375"
4865)
4866tg (CPTG
4867uid 2329,0
4868ps "CptPortTextPlaceStrategy"
4869stg "VerticalLayoutStrategy"
4870f (Text
4871uid 2330,0
4872va (VaSet
4873)
4874xt "124000,25500,125400,26500"
4875st "wr"
4876blo "124000,26300"
4877)
4878)
4879thePort (LogicalPort
4880decl (Decl
4881n "wr"
4882t "std_logic"
4883preAdd 0
4884posAdd 0
4885o 6
4886suid 4,0
4887)
4888)
4889)
4890*162 (CptPort
4891uid 2331,0
4892ps "OnEdgeStrategy"
4893shape (Triangle
4894uid 2332,0
4895ro 270
4896va (VaSet
4897vasetType 1
4898fg "0,65535,0"
4899)
4900xt "122250,26625,123000,27375"
4901)
4902tg (CPTG
4903uid 2333,0
4904ps "CptPortTextPlaceStrategy"
4905stg "VerticalLayoutStrategy"
4906f (Text
4907uid 2334,0
4908va (VaSet
4909)
4910xt "124000,26500,125400,27500"
4911st "int"
4912blo "124000,27300"
4913)
4914)
4915thePort (LogicalPort
4916m 1
4917decl (Decl
4918n "int"
4919t "std_logic"
4920o 1
4921suid 5,0
4922i "'1'"
4923)
4924)
4925)
4926*163 (CptPort
4927uid 2548,0
4928ps "OnEdgeStrategy"
4929shape (Triangle
4930uid 2549,0
4931ro 90
4932va (VaSet
4933vasetType 1
4934fg "0,65535,0"
4935)
4936xt "122250,27625,123000,28375"
4937)
4938tg (CPTG
4939uid 2550,0
4940ps "CptPortTextPlaceStrategy"
4941stg "VerticalLayoutStrategy"
4942f (Text
4943uid 2551,0
4944va (VaSet
4945)
4946xt "124000,27500,125200,28500"
4947st "cs"
4948blo "124000,28300"
4949)
4950)
4951thePort (LogicalPort
4952decl (Decl
4953n "cs"
4954t "std_logic"
4955o 5
4956suid 6,0
4957)
4958)
4959)
4960]
4961shape (Rectangle
4962uid 2337,0
4963va (VaSet
4964vasetType 1
4965fg "0,49152,49152"
4966lineColor "0,0,50000"
4967lineWidth 2
4968)
4969xt "123000,19000,133000,31000"
4970)
4971oxt "29000,0,39000,12000"
4972ttg (MlTextGroup
4973uid 2338,0
4974ps "CenterOffsetStrategy"
4975stg "VerticalLayoutStrategy"
4976textVec [
4977*164 (Text
4978uid 2339,0
4979va (VaSet
4980font "Arial,8,1"
4981)
4982xt "123200,31000,130900,32000"
4983st "FACT_FAD_TB_lib"
4984blo "123200,31800"
4985tm "BdLibraryNameMgr"
4986)
4987*165 (Text
4988uid 2340,0
4989va (VaSet
4990font "Arial,8,1"
4991)
4992xt "123200,32000,129800,33000"
4993st "w5300_emulator"
4994blo "123200,32800"
4995tm "CptNameMgr"
4996)
4997*166 (Text
4998uid 2341,0
4999va (VaSet
5000font "Arial,8,1"
5001)
5002xt "123200,33000,130000,34000"
5003st "I_mainTB_w5300"
5004blo "123200,33800"
5005tm "InstanceNameMgr"
5006)
5007]
5008)
5009ga (GenericAssociation
5010uid 2342,0
5011ps "EdgeToEdgeStrategy"
5012matrix (Matrix
5013uid 2343,0
5014text (MLText
5015uid 2344,0
5016va (VaSet
5017font "Courier New,8,0"
5018)
5019xt "123000,18000,123000,18000"
5020)
5021header ""
5022)
5023elements [
5024]
5025)
5026viewicon (ZoomableIcon
5027uid 2345,0
5028sl 0
5029va (VaSet
5030vasetType 1
5031fg "49152,49152,49152"
5032)
5033xt "123250,29250,124750,30750"
5034iconName "VhdlFileViewIcon.png"
5035iconMaskName "VhdlFileViewIcon.msk"
5036ftype 10
5037)
5038ordering 1
5039viewiconposition 0
5040portVis (PortSigDisplay
5041)
5042archFileType "UNKNOWN"
5043)
5044*167 (Net
5045uid 2705,0
5046decl (Decl
5047n "debug_data_ram_empty"
5048t "std_logic"
5049o 45
5050suid 53,0
5051)
5052declText (MLText
5053uid 2706,0
5054va (VaSet
5055font "Courier New,8,0"
5056)
5057xt "-90000,49400,-68000,50200"
5058st "SIGNAL debug_data_ram_empty  : std_logic"
5059)
5060)
5061*168 (Net
5062uid 2713,0
5063decl (Decl
5064n "debug_data_valid"
5065t "std_logic"
5066o 46
5067suid 54,0
5068)
5069declText (MLText
5070uid 2714,0
5071va (VaSet
5072font "Courier New,8,0"
5073)
5074xt "-90000,50200,-68000,51000"
5075st "SIGNAL debug_data_valid      : std_logic"
5076)
5077)
5078*169 (Net
5079uid 2721,0
5080decl (Decl
5081n "DG_state"
5082t "std_logic_vector"
5083b "(7 downto 0)"
5084prec "-- for debugging"
5085preAdd 0
5086o 47
5087suid 55,0
5088)
5089declText (MLText
5090uid 2722,0
5091va (VaSet
5092font "Courier New,8,0"
5093)
5094xt "-90000,27000,-58500,28600"
5095st "-- for debugging
5096SIGNAL DG_state              : std_logic_vector(7 downto 0)"
5097)
5098)
5099*170 (Net
5100uid 2729,0
5101decl (Decl
5102n "FTM_RS485_rx_en"
5103t "std_logic"
5104o 48
5105suid 56,0
5106)
5107declText (MLText
5108uid 2730,0
5109va (VaSet
5110font "Courier New,8,0"
5111)
5112xt "-90000,30200,-68000,31000"
5113st "SIGNAL FTM_RS485_rx_en       : std_logic"
5114)
5115)
5116*171 (Net
5117uid 2737,0
5118decl (Decl
5119n "FTM_RS485_tx_d"
5120t "std_logic"
5121o 49
5122suid 57,0
5123)
5124declText (MLText
5125uid 2738,0
5126va (VaSet
5127font "Courier New,8,0"
5128)
5129xt "-90000,31000,-68000,31800"
5130st "SIGNAL FTM_RS485_tx_d        : std_logic"
5131)
5132)
5133*172 (Net
5134uid 2745,0
5135decl (Decl
5136n "FTM_RS485_tx_en"
5137t "std_logic"
5138o 50
5139suid 58,0
5140)
5141declText (MLText
5142uid 2746,0
5143va (VaSet
5144font "Courier New,8,0"
5145)
5146xt "-90000,31800,-68000,32600"
5147st "SIGNAL FTM_RS485_tx_en       : std_logic"
5148)
5149)
5150*173 (Net
5151uid 2753,0
5152lang 2
5153decl (Decl
5154n "mem_manager_state"
5155t "std_logic_vector"
5156b "(3 DOWNTO 0)"
5157eolc "-- state is encoded here ... useful for debugging."
5158posAdd 0
5159o 51
5160suid 59,0
5161)
5162declText (MLText
5163uid 2754,0
5164va (VaSet
5165font "Courier New,8,0"
5166)
5167xt "-90000,55000,-33000,55800"
5168st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
5169)
5170)
5171*174 (Net
5172uid 2761,0
5173decl (Decl
5174n "trigger_veto"
5175t "std_logic"
5176o 52
5177suid 60,0
5178i "'1'"
5179)
5180declText (MLText
5181uid 2762,0
5182va (VaSet
5183font "Courier New,8,0"
5184)
5185xt "-90000,62200,-55000,63000"
5186st "SIGNAL trigger_veto          : std_logic                    := '1'"
5187)
5188)
5189*175 (Net
5190uid 2769,0
5191decl (Decl
5192n "w5300_state"
5193t "std_logic_vector"
5194b "(7 DOWNTO 0)"
5195eolc "-- state is encoded here ... useful for debugging."
5196posAdd 0
5197o 53
5198suid 61,0
5199)
5200declText (MLText
5201uid 2770,0
5202va (VaSet
5203font "Courier New,8,0"
5204)
5205xt "-90000,63000,-33000,63800"
5206st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
5207)
5208)
5209*176 (Net
5210uid 2777,0
5211decl (Decl
5212n "FTM_RS485_rx_d"
5213t "std_logic"
5214o 54
5215suid 62,0
5216)
5217declText (MLText
5218uid 2778,0
5219va (VaSet
5220font "Courier New,8,0"
5221)
5222xt "-90000,29400,-68000,30200"
5223st "SIGNAL FTM_RS485_rx_d        : std_logic"
5224)
5225)
5226*177 (Net
5227uid 2942,0
5228decl (Decl
5229n "socket_tx_free_out"
5230t "std_logic_vector"
5231b "(16 DOWNTO 0)"
5232eolc "-- 17bit value .. that's true"
5233posAdd 0
5234o 55
5235suid 64,0
5236)
5237declText (MLText
5238uid 2943,0
5239va (VaSet
5240font "Courier New,8,0"
5241)
5242xt "-90000,60600,-43000,61400"
5243st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
5244)
5245)
5246*178 (SaComponent
5247uid 3285,0
5248optionalChildren [
5249*179 (CptPort
5250uid 3073,0
5251ps "OnEdgeStrategy"
5252shape (Triangle
5253uid 3074,0
5254ro 90
5255va (VaSet
5256vasetType 1
5257fg "0,65535,0"
5258)
5259xt "168000,19625,168750,20375"
5260)
5261tg (CPTG
5262uid 3075,0
5263ps "CptPortTextPlaceStrategy"
5264stg "RightVerticalLayoutStrategy"
5265f (Text
5266uid 3076,0
5267va (VaSet
5268)
5269xt "163400,19500,167000,20500"
5270st "wiz_reset"
5271ju 2
5272blo "167000,20300"
5273)
5274)
5275thePort (LogicalPort
5276m 1
5277decl (Decl
5278n "wiz_reset"
5279t "std_logic"
5280o 50
5281suid 2,0
5282i "'1'"
5283)
5284)
5285)
5286*180 (CptPort
5287uid 3077,0
5288ps "OnEdgeStrategy"
5289shape (Triangle
5290uid 3078,0
5291ro 90
5292va (VaSet
5293vasetType 1
5294fg "0,65535,0"
5295)
5296xt "168000,65625,168750,66375"
5297)
5298tg (CPTG
5299uid 3079,0
5300ps "CptPortTextPlaceStrategy"
5301stg "RightVerticalLayoutStrategy"
5302f (Text
5303uid 3080,0
5304va (VaSet
5305)
5306xt "163000,65500,167000,66500"
5307st "led : (7:0)"
5308ju 2
5309blo "167000,66300"
5310)
5311)
5312thePort (LogicalPort
5313m 1
5314decl (Decl
5315n "led"
5316t "std_logic_vector"
5317b "(7 DOWNTO 0)"
5318posAdd 0
5319o 38
5320suid 7,0
5321i "(OTHERS => '0')"
5322)
5323)
5324)
5325*181 (CptPort
5326uid 3081,0
5327ps "OnEdgeStrategy"
5328shape (Triangle
5329uid 3082,0
5330ro 90
5331va (VaSet
5332vasetType 1
5333fg "0,65535,0"
5334)
5335xt "139250,27625,140000,28375"
5336)
5337tg (CPTG
5338uid 3083,0
5339ps "CptPortTextPlaceStrategy"
5340stg "VerticalLayoutStrategy"
5341f (Text
5342uid 3084,0
5343va (VaSet
5344)
5345xt "141000,27500,143800,28500"
5346st "trigger"
5347blo "141000,28300"
5348)
5349)
5350thePort (LogicalPort
5351decl (Decl
5352n "trigger"
5353t "std_logic"
5354preAdd 0
5355posAdd 0
5356o 14
5357suid 18,0
5358)
5359)
5360)
5361*182 (CptPort
5362uid 3085,0
5363ps "OnEdgeStrategy"
5364shape (Triangle
5365uid 3086,0
5366ro 270
5367va (VaSet
5368vasetType 1
5369fg "0,65535,0"
5370)
5371xt "139250,38625,140000,39375"
5372)
5373tg (CPTG
5374uid 3087,0
5375ps "CptPortTextPlaceStrategy"
5376stg "VerticalLayoutStrategy"
5377f (Text
5378uid 3088,0
5379va (VaSet
5380)
5381xt "141000,38500,144200,39500"
5382st "adc_oeb"
5383blo "141000,39300"
5384)
5385)
5386thePort (LogicalPort
5387m 1
5388decl (Decl
5389n "adc_oeb"
5390t "std_logic"
5391o 26
5392suid 21,0
5393i "'1'"
5394)
5395)
5396)
5397*183 (CptPort
5398uid 3089,0
5399ps "OnEdgeStrategy"
5400shape (Triangle
5401uid 3090,0
5402ro 90
5403va (VaSet
5404vasetType 1
5405fg "0,65535,0"
5406)
5407xt "139250,29625,140000,30375"
5408)
5409tg (CPTG
5410uid 3091,0
5411ps "CptPortTextPlaceStrategy"
5412stg "VerticalLayoutStrategy"
5413f (Text
5414uid 3092,0
5415va (VaSet
5416)
5417xt "141000,29500,146900,30500"
5418st "board_id : (3:0)"
5419blo "141000,30300"
5420)
5421)
5422thePort (LogicalPort
5423decl (Decl
5424n "board_id"
5425t "std_logic_vector"
5426b "(3 DOWNTO 0)"
5427o 10
5428suid 24,0
5429)
5430)
5431)
5432*184 (CptPort
5433uid 3093,0
5434ps "OnEdgeStrategy"
5435shape (Triangle
5436uid 3094,0
5437ro 90
5438va (VaSet
5439vasetType 1
5440fg "0,65535,0"
5441)
5442xt "139250,30625,140000,31375"
5443)
5444tg (CPTG
5445uid 3095,0
5446ps "CptPortTextPlaceStrategy"
5447stg "VerticalLayoutStrategy"
5448f (Text
5449uid 3096,0
5450va (VaSet
5451)
5452xt "141000,30500,146700,31500"
5453st "crate_id : (1:0)"
5454blo "141000,31300"
5455)
5456)
5457thePort (LogicalPort
5458decl (Decl
5459n "crate_id"
5460t "std_logic_vector"
5461b "(1 DOWNTO 0)"
5462o 11
5463suid 25,0
5464)
5465)
5466)
5467*185 (CptPort
5468uid 3097,0
5469ps "OnEdgeStrategy"
5470shape (Triangle
5471uid 3098,0
5472ro 90
5473va (VaSet
5474vasetType 1
5475fg "0,65535,0"
5476)
5477xt "168000,16625,168750,17375"
5478)
5479tg (CPTG
5480uid 3099,0
5481ps "CptPortTextPlaceStrategy"
5482stg "RightVerticalLayoutStrategy"
5483f (Text
5484uid 3100,0
5485va (VaSet
5486)
5487xt "161000,16500,167000,17500"
5488st "wiz_addr : (9:0)"
5489ju 2
5490blo "167000,17300"
5491)
5492)
5493thePort (LogicalPort
5494m 1
5495decl (Decl
5496n "wiz_addr"
5497t "std_logic_vector"
5498b "(9 DOWNTO 0)"
5499o 47
5500suid 26,0
5501)
5502)
5503)
5504*186 (CptPort
5505uid 3101,0
5506ps "OnEdgeStrategy"
5507shape (Diamond
5508uid 3102,0
5509ro 90
5510va (VaSet
5511vasetType 1
5512fg "0,65535,0"
5513)
5514xt "168000,17625,168750,18375"
5515)
5516tg (CPTG
5517uid 3103,0
5518ps "CptPortTextPlaceStrategy"
5519stg "RightVerticalLayoutStrategy"
5520f (Text
5521uid 3104,0
5522va (VaSet
5523)
5524xt "160700,17500,167000,18500"
5525st "wiz_data : (15:0)"
5526ju 2
5527blo "167000,18300"
5528)
5529)
5530thePort (LogicalPort
5531m 2
5532decl (Decl
5533n "wiz_data"
5534t "std_logic_vector"
5535b "(15 DOWNTO 0)"
5536o 53
5537suid 27,0
5538)
5539)
5540)
5541*187 (CptPort
5542uid 3105,0
5543ps "OnEdgeStrategy"
5544shape (Triangle
5545uid 3106,0
5546ro 90
5547va (VaSet
5548vasetType 1
5549fg "0,65535,0"
5550)
5551xt "168000,23625,168750,24375"
5552)
5553tg (CPTG
5554uid 3107,0
5555ps "CptPortTextPlaceStrategy"
5556stg "RightVerticalLayoutStrategy"
5557f (Text
5558uid 3108,0
5559va (VaSet
5560)
5561xt "164300,23500,167000,24500"
5562st "wiz_cs"
5563ju 2
5564blo "167000,24300"
5565)
5566)
5567thePort (LogicalPort
5568m 1
5569decl (Decl
5570n "wiz_cs"
5571t "std_logic"
5572o 48
5573suid 28,0
5574i "'1'"
5575)
5576)
5577)
5578*188 (CptPort
5579uid 3109,0
5580ps "OnEdgeStrategy"
5581shape (Triangle
5582uid 3110,0
5583ro 90
5584va (VaSet
5585vasetType 1
5586fg "0,65535,0"
5587)
5588xt "168000,21625,168750,22375"
5589)
5590tg (CPTG
5591uid 3111,0
5592ps "CptPortTextPlaceStrategy"
5593stg "RightVerticalLayoutStrategy"
5594f (Text
5595uid 3112,0
5596va (VaSet
5597)
5598xt "164300,21500,167000,22500"
5599st "wiz_wr"
5600ju 2
5601blo "167000,22300"
5602)
5603)
5604thePort (LogicalPort
5605m 1
5606decl (Decl
5607n "wiz_wr"
5608t "std_logic"
5609o 51
5610suid 29,0
5611i "'1'"
5612)
5613)
5614)
5615*189 (CptPort
5616uid 3113,0
5617ps "OnEdgeStrategy"
5618shape (Triangle
5619uid 3114,0
5620ro 90
5621va (VaSet
5622vasetType 1
5623fg "0,65535,0"
5624)
5625xt "168000,20625,168750,21375"
5626)
5627tg (CPTG
5628uid 3115,0
5629ps "CptPortTextPlaceStrategy"
5630stg "RightVerticalLayoutStrategy"
5631f (Text
5632uid 3116,0
5633va (VaSet
5634)
5635xt "164400,20500,167000,21500"
5636st "wiz_rd"
5637ju 2
5638blo "167000,21300"
5639)
5640)
5641thePort (LogicalPort
5642m 1
5643decl (Decl
5644n "wiz_rd"
5645t "std_logic"
5646o 49
5647suid 30,0
5648i "'1'"
5649)
5650)
5651)
5652*190 (CptPort
5653uid 3117,0
5654ps "OnEdgeStrategy"
5655shape (Triangle
5656uid 3118,0
5657ro 270
5658va (VaSet
5659vasetType 1
5660fg "0,65535,0"
5661)
5662xt "168000,22625,168750,23375"
5663)
5664tg (CPTG
5665uid 3119,0
5666ps "CptPortTextPlaceStrategy"
5667stg "RightVerticalLayoutStrategy"
5668f (Text
5669uid 3120,0
5670va (VaSet
5671)
5672xt "164300,22500,167000,23500"
5673st "wiz_int"
5674ju 2
5675blo "167000,23300"
5676)
5677)
5678thePort (LogicalPort
5679decl (Decl
5680n "wiz_int"
5681t "std_logic"
5682o 15
5683suid 31,0
5684)
5685)
5686)
5687*191 (CptPort
5688uid 3121,0
5689ps "OnEdgeStrategy"
5690shape (Triangle
5691uid 3122,0
5692ro 270
5693va (VaSet
5694vasetType 1
5695fg "0,65535,0"
5696)
5697xt "139250,18625,140000,19375"
5698)
5699tg (CPTG
5700uid 3123,0
5701ps "CptPortTextPlaceStrategy"
5702stg "VerticalLayoutStrategy"
5703f (Text
5704uid 3124,0
5705va (VaSet
5706)
5707xt "141000,18500,145500,19500"
5708st "CLK_25_PS"
5709blo "141000,19300"
5710)
5711)
5712thePort (LogicalPort
5713m 1
5714decl (Decl
5715n "CLK_25_PS"
5716t "std_logic"
5717o 17
5718suid 35,0
5719)
5720)
5721)
5722*192 (CptPort
5723uid 3125,0
5724ps "OnEdgeStrategy"
5725shape (Triangle
5726uid 3126,0
5727ro 270
5728va (VaSet
5729vasetType 1
5730fg "0,65535,0"
5731)
5732xt "139250,17625,140000,18375"
5733)
5734tg (CPTG
5735uid 3127,0
5736ps "CptPortTextPlaceStrategy"
5737stg "VerticalLayoutStrategy"
5738f (Text
5739uid 3128,0
5740va (VaSet
5741)
5742xt "141000,17500,144100,18500"
5743st "CLK_50"
5744blo "141000,18300"
5745)
5746)
5747thePort (LogicalPort
5748m 1
5749decl (Decl
5750n "CLK_50"
5751t "std_logic"
5752preAdd 0
5753posAdd 0
5754o 18
5755suid 37,0
5756)
5757)
5758)
5759*193 (CptPort
5760uid 3129,0
5761ps "OnEdgeStrategy"
5762shape (Triangle
5763uid 3130,0
5764ro 90
5765va (VaSet
5766vasetType 1
5767fg "0,65535,0"
5768)
5769xt "139250,16625,140000,17375"
5770)
5771tg (CPTG
5772uid 3131,0
5773ps "CptPortTextPlaceStrategy"
5774stg "VerticalLayoutStrategy"
5775f (Text
5776uid 3132,0
5777va (VaSet
5778)
5779xt "141000,16500,142900,17500"
5780st "CLK"
5781blo "141000,17300"
5782)
5783)
5784thePort (LogicalPort
5785decl (Decl
5786n "CLK"
5787t "std_logic"
5788o 1
5789suid 38,0
5790)
5791)
5792)
5793*194 (CptPort
5794uid 3133,0
5795ps "OnEdgeStrategy"
5796shape (Triangle
5797uid 3134,0
5798ro 90
5799va (VaSet
5800vasetType 1
5801fg "0,65535,0"
5802)
5803xt "139250,37625,140000,38375"
5804)
5805tg (CPTG
5806uid 3135,0
5807ps "CptPortTextPlaceStrategy"
5808stg "VerticalLayoutStrategy"
5809f (Text
5810uid 3136,0
5811va (VaSet
5812)
5813xt "141000,37500,149000,38500"
5814st "adc_otr_array : (3:0)"
5815blo "141000,38300"
5816)
5817)
5818thePort (LogicalPort
5819decl (Decl
5820n "adc_otr_array"
5821t "std_logic_vector"
5822b "(3 DOWNTO 0)"
5823o 9
5824suid 40,0
5825)
5826)
5827)
5828*195 (CptPort
5829uid 3137,0
5830ps "OnEdgeStrategy"
5831shape (Triangle
5832uid 3138,0
5833ro 90
5834va (VaSet
5835vasetType 1
5836fg "0,65535,0"
5837)
5838xt "139250,43625,140000,44375"
5839)
5840tg (CPTG
5841uid 3139,0
5842ps "CptPortTextPlaceStrategy"
5843stg "VerticalLayoutStrategy"
5844f (Text
5845uid 3140,0
5846va (VaSet
5847)
5848xt "141000,43500,146900,44500"
5849st "adc_data_array"
5850blo "141000,44300"
5851)
5852)
5853thePort (LogicalPort
5854decl (Decl
5855n "adc_data_array"
5856t "adc_data_array_type"
5857o 8
5858suid 41,0
5859)
5860)
5861)
5862*196 (CptPort
5863uid 3141,0
5864ps "OnEdgeStrategy"
5865shape (Triangle
5866uid 3142,0
5867ro 270
5868va (VaSet
5869vasetType 1
5870fg "0,65535,0"
5871)
5872xt "139250,57625,140000,58375"
5873)
5874tg (CPTG
5875uid 3143,0
5876ps "CptPortTextPlaceStrategy"
5877stg "VerticalLayoutStrategy"
5878f (Text
5879uid 3144,0
5880va (VaSet
5881)
5882xt "141000,57500,149500,58500"
5883st "drs_channel_id : (3:0)"
5884blo "141000,58300"
5885)
5886)
5887thePort (LogicalPort
5888m 1
5889decl (Decl
5890n "drs_channel_id"
5891t "std_logic_vector"
5892b "(3 downto 0)"
5893o 35
5894suid 48,0
5895i "(others => '0')"
5896)
5897)
5898)
5899*197 (CptPort
5900uid 3145,0
5901ps "OnEdgeStrategy"
5902shape (Triangle
5903uid 3146,0
5904ro 270
5905va (VaSet
5906vasetType 1
5907fg "0,65535,0"
5908)
5909xt "139250,62625,140000,63375"
5910)
5911tg (CPTG
5912uid 3147,0
5913ps "CptPortTextPlaceStrategy"
5914stg "VerticalLayoutStrategy"
5915f (Text
5916uid 3148,0
5917va (VaSet
5918)
5919xt "141000,62500,145300,63500"
5920st "drs_dwrite"
5921blo "141000,63300"
5922)
5923)
5924thePort (LogicalPort
5925m 1
5926decl (Decl
5927n "drs_dwrite"
5928t "std_logic"
5929o 36
5930suid 49,0
5931i "'1'"
5932)
5933)
5934)
5935*198 (CptPort
5936uid 3149,0
5937ps "OnEdgeStrategy"
5938shape (Triangle
5939uid 3150,0
5940ro 90
5941va (VaSet
5942vasetType 1
5943fg "0,65535,0"
5944)
5945xt "139250,53625,140000,54375"
5946)
5947tg (CPTG
5948uid 3151,0
5949ps "CptPortTextPlaceStrategy"
5950stg "VerticalLayoutStrategy"
5951f (Text
5952uid 3152,0
5953va (VaSet
5954)
5955xt "141000,53500,146400,54500"
5956st "SROUT_in_0"
5957blo "141000,54300"
5958)
5959)
5960thePort (LogicalPort
5961decl (Decl
5962n "SROUT_in_0"
5963t "std_logic"
5964o 4
5965suid 52,0
5966)
5967)
5968)
5969*199 (CptPort
5970uid 3153,0
5971ps "OnEdgeStrategy"
5972shape (Triangle
5973uid 3154,0
5974ro 90
5975va (VaSet
5976vasetType 1
5977fg "0,65535,0"
5978)
5979xt "139250,54625,140000,55375"
5980)
5981tg (CPTG
5982uid 3155,0
5983ps "CptPortTextPlaceStrategy"
5984stg "VerticalLayoutStrategy"
5985f (Text
5986uid 3156,0
5987va (VaSet
5988)
5989xt "141000,54500,146400,55500"
5990st "SROUT_in_1"
5991blo "141000,55300"
5992)
5993)
5994thePort (LogicalPort
5995decl (Decl
5996n "SROUT_in_1"
5997t "std_logic"
5998o 5
5999suid 53,0
6000)
6001)
6002)
6003*200 (CptPort
6004uid 3157,0
6005ps "OnEdgeStrategy"
6006shape (Triangle
6007uid 3158,0
6008ro 90
6009va (VaSet
6010vasetType 1
6011fg "0,65535,0"
6012)
6013xt "139250,55625,140000,56375"
6014)
6015tg (CPTG
6016uid 3159,0
6017ps "CptPortTextPlaceStrategy"
6018stg "VerticalLayoutStrategy"
6019f (Text
6020uid 3160,0
6021va (VaSet
6022)
6023xt "141000,55500,146400,56500"
6024st "SROUT_in_2"
6025blo "141000,56300"
6026)
6027)
6028thePort (LogicalPort
6029decl (Decl
6030n "SROUT_in_2"
6031t "std_logic"
6032o 6
6033suid 54,0
6034)
6035)
6036)
6037*201 (CptPort
6038uid 3161,0
6039ps "OnEdgeStrategy"
6040shape (Triangle
6041uid 3162,0
6042ro 90
6043va (VaSet
6044vasetType 1
6045fg "0,65535,0"
6046)
6047xt "139250,56625,140000,57375"
6048)
6049tg (CPTG
6050uid 3163,0
6051ps "CptPortTextPlaceStrategy"
6052stg "VerticalLayoutStrategy"
6053f (Text
6054uid 3164,0
6055va (VaSet
6056)
6057xt "141000,56500,146400,57500"
6058st "SROUT_in_3"
6059blo "141000,57300"
6060)
6061)
6062thePort (LogicalPort
6063decl (Decl
6064n "SROUT_in_3"
6065t "std_logic"
6066o 7
6067suid 55,0
6068)
6069)
6070)
6071*202 (CptPort
6072uid 3165,0
6073ps "OnEdgeStrategy"
6074shape (Triangle
6075uid 3166,0
6076ro 270
6077va (VaSet
6078vasetType 1
6079fg "0,65535,0"
6080)
6081xt "139250,59625,140000,60375"
6082)
6083tg (CPTG
6084uid 3167,0
6085ps "CptPortTextPlaceStrategy"
6086stg "VerticalLayoutStrategy"
6087f (Text
6088uid 3168,0
6089va (VaSet
6090)
6091xt "141000,59500,145200,60500"
6092st "RSRLOAD"
6093blo "141000,60300"
6094)
6095)
6096thePort (LogicalPort
6097m 1
6098decl (Decl
6099n "RSRLOAD"
6100t "std_logic"
6101o 23
6102suid 56,0
6103i "'0'"
6104)
6105)
6106)
6107*203 (CptPort
6108uid 3169,0
6109ps "OnEdgeStrategy"
6110shape (Triangle
6111uid 3170,0
6112ro 270
6113va (VaSet
6114vasetType 1
6115fg "0,65535,0"
6116)
6117xt "139250,60625,140000,61375"
6118)
6119tg (CPTG
6120uid 3171,0
6121ps "CptPortTextPlaceStrategy"
6122stg "VerticalLayoutStrategy"
6123f (Text
6124uid 3172,0
6125va (VaSet
6126)
6127xt "141000,60500,144000,61500"
6128st "SRCLK"
6129blo "141000,61300"
6130)
6131)
6132thePort (LogicalPort
6133m 1
6134decl (Decl
6135n "SRCLK"
6136t "std_logic"
6137o 24
6138suid 57,0
6139i "'0'"
6140)
6141)
6142)
6143*204 (CptPort
6144uid 3173,0
6145ps "OnEdgeStrategy"
6146shape (Triangle
6147uid 3174,0
6148ro 90
6149va (VaSet
6150vasetType 1
6151fg "0,65535,0"
6152)
6153xt "168000,46625,168750,47375"
6154)
6155tg (CPTG
6156uid 3175,0
6157ps "CptPortTextPlaceStrategy"
6158stg "RightVerticalLayoutStrategy"
6159f (Text
6160uid 3176,0
6161va (VaSet
6162)
6163xt "165300,46500,167000,47500"
6164st "sclk"
6165ju 2
6166blo "167000,47300"
6167)
6168)
6169thePort (LogicalPort
6170m 1
6171decl (Decl
6172n "sclk"
6173t "std_logic"
6174o 42
6175suid 62,0
6176)
6177)
6178)
6179*205 (CptPort
6180uid 3177,0
6181ps "OnEdgeStrategy"
6182shape (Diamond
6183uid 3178,0
6184ro 90
6185va (VaSet
6186vasetType 1
6187fg "0,65535,0"
6188)
6189xt "168000,47625,168750,48375"
6190)
6191tg (CPTG
6192uid 3179,0
6193ps "CptPortTextPlaceStrategy"
6194stg "RightVerticalLayoutStrategy"
6195f (Text
6196uid 3180,0
6197va (VaSet
6198)
6199xt "165600,47500,167000,48500"
6200st "sio"
6201ju 2
6202blo "167000,48300"
6203)
6204)
6205thePort (LogicalPort
6206m 2
6207decl (Decl
6208n "sio"
6209t "std_logic"
6210preAdd 0
6211posAdd 0
6212o 52
6213suid 63,0
6214)
6215)
6216)
6217*206 (CptPort
6218uid 3181,0
6219ps "OnEdgeStrategy"
6220shape (Triangle
6221uid 3182,0
6222ro 90
6223va (VaSet
6224vasetType 1
6225fg "0,65535,0"
6226)
6227xt "168000,35625,168750,36375"
6228)
6229tg (CPTG
6230uid 3183,0
6231ps "CptPortTextPlaceStrategy"
6232stg "RightVerticalLayoutStrategy"
6233f (Text
6234uid 3184,0
6235va (VaSet
6236)
6237xt "164200,35500,167000,36500"
6238st "dac_cs"
6239ju 2
6240blo "167000,36300"
6241)
6242)
6243thePort (LogicalPort
6244m 1
6245decl (Decl
6246n "dac_cs"
6247t "std_logic"
6248o 31
6249suid 64,0
6250)
6251)
6252)
6253*207 (CptPort
6254uid 3185,0
6255ps "OnEdgeStrategy"
6256shape (Triangle
6257uid 3186,0
6258ro 90
6259va (VaSet
6260vasetType 1
6261fg "0,65535,0"
6262)
6263xt "168000,37625,168750,38375"
6264)
6265tg (CPTG
6266uid 3187,0
6267ps "CptPortTextPlaceStrategy"
6268stg "RightVerticalLayoutStrategy"
6269f (Text
6270uid 3188,0
6271va (VaSet
6272)
6273xt "160500,37500,167000,38500"
6274st "sensor_cs : (3:0)"
6275ju 2
6276blo "167000,38300"
6277)
6278)
6279thePort (LogicalPort
6280m 1
6281decl (Decl
6282n "sensor_cs"
6283t "std_logic_vector"
6284b "(3 DOWNTO 0)"
6285o 43
6286suid 65,0
6287)
6288)
6289)
6290*208 (CptPort
6291uid 3189,0
6292ps "OnEdgeStrategy"
6293shape (Triangle
6294uid 3190,0
6295ro 90
6296va (VaSet
6297vasetType 1
6298fg "0,65535,0"
6299)
6300xt "168000,48625,168750,49375"
6301)
6302tg (CPTG
6303uid 3191,0
6304ps "CptPortTextPlaceStrategy"
6305stg "RightVerticalLayoutStrategy"
6306f (Text
6307uid 3192,0
6308va (VaSet
6309)
6310xt "165000,48500,167000,49500"
6311st "mosi"
6312ju 2
6313blo "167000,49300"
6314)
6315)
6316thePort (LogicalPort
6317m 1
6318decl (Decl
6319n "mosi"
6320t "std_logic"
6321o 40
6322suid 66,0
6323i "'0'"
6324)
6325)
6326)
6327*209 (CptPort
6328uid 3193,0
6329ps "OnEdgeStrategy"
6330shape (Triangle
6331uid 3194,0
6332ro 270
6333va (VaSet
6334vasetType 1
6335fg "0,65535,0"
6336)
6337xt "139250,61625,140000,62375"
6338)
6339tg (CPTG
6340uid 3195,0
6341ps "CptPortTextPlaceStrategy"
6342stg "VerticalLayoutStrategy"
6343f (Text
6344uid 3196,0
6345va (VaSet
6346)
6347xt "141000,61500,144000,62500"
6348st "denable"
6349blo "141000,62300"
6350)
6351)
6352thePort (LogicalPort
6353m 1
6354decl (Decl
6355n "denable"
6356t "std_logic"
6357eolc "-- default domino wave off"
6358posAdd 0
6359o 34
6360suid 67,0
6361i "'0'"
6362)
6363)
6364)
6365*210 (CptPort
6366uid 3197,0
6367ps "OnEdgeStrategy"
6368shape (Triangle
6369uid 3198,0
6370ro 270
6371va (VaSet
6372vasetType 1
6373fg "0,65535,0"
6374)
6375xt "139250,67625,140000,68375"
6376)
6377tg (CPTG
6378uid 3199,0
6379ps "CptPortTextPlaceStrategy"
6380stg "VerticalLayoutStrategy"
6381f (Text
6382uid 3200,0
6383va (VaSet
6384)
6385xt "141000,67500,144700,68500"
6386st "SRIN_out"
6387blo "141000,68300"
6388)
6389)
6390thePort (LogicalPort
6391m 1
6392decl (Decl
6393n "SRIN_out"
6394t "std_logic"
6395o 25
6396suid 85,0
6397i "'0'"
6398)
6399)
6400)
6401*211 (CptPort
6402uid 3201,0
6403ps "OnEdgeStrategy"
6404shape (Triangle
6405uid 3202,0
6406ro 90
6407va (VaSet
6408vasetType 1
6409fg "0,65535,0"
6410)
6411xt "168000,73625,168750,74375"
6412)
6413tg (CPTG
6414uid 3203,0
6415ps "CptPortTextPlaceStrategy"
6416stg "RightVerticalLayoutStrategy"
6417f (Text
6418uid 3204,0
6419va (VaSet
6420)
6421xt "164600,73500,167000,74500"
6422st "green"
6423ju 2
6424blo "167000,74300"
6425)
6426)
6427thePort (LogicalPort
6428m 1
6429decl (Decl
6430n "green"
6431t "std_logic"
6432o 37
6433suid 86,0
6434)
6435)
6436)
6437*212 (CptPort
6438uid 3205,0
6439ps "OnEdgeStrategy"
6440shape (Triangle
6441uid 3206,0
6442ro 90
6443va (VaSet
6444vasetType 1
6445fg "0,65535,0"
6446)
6447xt "168000,75625,168750,76375"
6448)
6449tg (CPTG
6450uid 3207,0
6451ps "CptPortTextPlaceStrategy"
6452stg "RightVerticalLayoutStrategy"
6453f (Text
6454uid 3208,0
6455va (VaSet
6456)
6457xt "164500,75500,167000,76500"
6458st "amber"
6459ju 2
6460blo "167000,76300"
6461)
6462)
6463thePort (LogicalPort
6464m 1
6465decl (Decl
6466n "amber"
6467t "std_logic"
6468o 29
6469suid 87,0
6470)
6471)
6472)
6473*213 (CptPort
6474uid 3209,0
6475ps "OnEdgeStrategy"
6476shape (Triangle
6477uid 3210,0
6478ro 90
6479va (VaSet
6480vasetType 1
6481fg "0,65535,0"
6482)
6483xt "168000,74625,168750,75375"
6484)
6485tg (CPTG
6486uid 3211,0
6487ps "CptPortTextPlaceStrategy"
6488stg "RightVerticalLayoutStrategy"
6489f (Text
6490uid 3212,0
6491va (VaSet
6492)
6493xt "165500,74500,167000,75500"
6494st "red"
6495ju 2
6496blo "167000,75300"
6497)
6498)
6499thePort (LogicalPort
6500m 1
6501decl (Decl
6502n "red"
6503t "std_logic"
6504o 41
6505suid 88,0
6506)
6507)
6508)
6509*214 (CptPort
6510uid 3213,0
6511ps "OnEdgeStrategy"
6512shape (Triangle
6513uid 3214,0
6514ro 90
6515va (VaSet
6516vasetType 1
6517fg "0,65535,0"
6518)
6519xt "139250,70625,140000,71375"
6520)
6521tg (CPTG
6522uid 3215,0
6523ps "CptPortTextPlaceStrategy"
6524stg "VerticalLayoutStrategy"
6525f (Text
6526uid 3216,0
6527va (VaSet
6528)
6529xt "141000,70500,146500,71500"
6530st "D_T_in : (1:0)"
6531blo "141000,71300"
6532)
6533)
6534thePort (LogicalPort
6535decl (Decl
6536n "D_T_in"
6537t "std_logic_vector"
6538b "(1 DOWNTO 0)"
6539o 2
6540suid 91,0
6541)
6542)
6543)
6544*215 (CptPort
6545uid 3217,0
6546ps "OnEdgeStrategy"
6547shape (Triangle
6548uid 3218,0
6549ro 90
6550va (VaSet
6551vasetType 1
6552fg "0,65535,0"
6553)
6554xt "139250,71625,140000,72375"
6555)
6556tg (CPTG
6557uid 3219,0
6558ps "CptPortTextPlaceStrategy"
6559stg "VerticalLayoutStrategy"
6560f (Text
6561uid 3220,0
6562va (VaSet
6563)
6564xt "141000,71500,146100,72500"
6565st "drs_refclk_in"
6566blo "141000,72300"
6567)
6568)
6569thePort (LogicalPort
6570decl (Decl
6571n "drs_refclk_in"
6572t "std_logic"
6573eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
6574o 12
6575suid 92,0
6576)
6577)
6578)
6579*216 (CptPort
6580uid 3221,0
6581ps "OnEdgeStrategy"
6582shape (Triangle
6583uid 3222,0
6584ro 90
6585va (VaSet
6586vasetType 1
6587fg "0,65535,0"
6588)
6589xt "139250,72625,140000,73375"
6590)
6591tg (CPTG
6592uid 3223,0
6593ps "CptPortTextPlaceStrategy"
6594stg "VerticalLayoutStrategy"
6595f (Text
6596uid 3224,0
6597va (VaSet
6598)
6599xt "141000,72500,147100,73500"
6600st "plllock_in : (3:0)"
6601blo "141000,73300"
6602)
6603)
6604thePort (LogicalPort
6605decl (Decl
6606n "plllock_in"
6607t "std_logic_vector"
6608b "(3 DOWNTO 0)"
6609eolc "-- high level, if dominowave is running and DRS PLL locked"
6610o 13
6611suid 93,0
6612)
6613)
6614)
6615*217 (CptPort
6616uid 3225,0
6617ps "OnEdgeStrategy"
6618shape (Triangle
6619uid 3226,0
6620ro 90
6621va (VaSet
6622vasetType 1
6623fg "0,65535,0"
6624)
6625xt "168000,72625,168750,73375"
6626)
6627tg (CPTG
6628uid 3227,0
6629ps "CptPortTextPlaceStrategy"
6630stg "RightVerticalLayoutStrategy"
6631f (Text
6632uid 3228,0
6633va (VaSet
6634)
6635xt "158400,72500,167000,73500"
6636st "counter_result : (11:0)"
6637ju 2
6638blo "167000,73300"
6639)
6640)
6641thePort (LogicalPort
6642m 1
6643decl (Decl
6644n "counter_result"
6645t "std_logic_vector"
6646b "(11 DOWNTO 0)"
6647o 30
6648suid 94,0
6649)
6650)
6651)
6652*218 (CptPort
6653uid 3229,0
6654ps "OnEdgeStrategy"
6655shape (Triangle
6656uid 3230,0
6657ro 90
6658va (VaSet
6659vasetType 1
6660fg "0,65535,0"
6661)
6662xt "168000,69625,168750,70375"
6663)
6664tg (CPTG
6665uid 3231,0
6666ps "CptPortTextPlaceStrategy"
6667stg "RightVerticalLayoutStrategy"
6668f (Text
6669uid 3232,0
6670va (VaSet
6671)
6672xt "158400,69500,167000,70500"
6673st "alarm_refclk_too_high"
6674ju 2
6675blo "167000,70300"
6676)
6677)
6678thePort (LogicalPort
6679m 1
6680decl (Decl
6681n "alarm_refclk_too_high"
6682t "std_logic"
6683o 27
6684suid 95,0
6685)
6686)
6687)
6688*219 (CptPort
6689uid 3233,0
6690ps "OnEdgeStrategy"
6691shape (Triangle
6692uid 3234,0
6693ro 90
6694va (VaSet
6695vasetType 1
6696fg "0,65535,0"
6697)
6698xt "168000,70625,168750,71375"
6699)
6700tg (CPTG
6701uid 3235,0
6702ps "CptPortTextPlaceStrategy"
6703stg "RightVerticalLayoutStrategy"
6704f (Text
6705uid 3236,0
6706va (VaSet
6707)
6708xt "158800,70500,167000,71500"
6709st "alarm_refclk_too_low"
6710ju 2
6711blo "167000,71300"
6712)
6713)
6714thePort (LogicalPort
6715m 1
6716decl (Decl
6717n "alarm_refclk_too_low"
6718t "std_logic"
6719posAdd 0
6720o 28
6721suid 96,0
6722)
6723)
6724)
6725*220 (CptPort
6726uid 3237,0
6727ps "OnEdgeStrategy"
6728shape (Triangle
6729uid 3238,0
6730ro 270
6731va (VaSet
6732vasetType 1
6733fg "0,65535,0"
6734)
6735xt "139250,19625,140000,20375"
6736)
6737tg (CPTG
6738uid 3239,0
6739ps "CptPortTextPlaceStrategy"
6740stg "VerticalLayoutStrategy"
6741f (Text
6742uid 3240,0
6743va (VaSet
6744)
6745xt "141000,19500,145000,20500"
6746st "ADC_CLK"
6747blo "141000,20300"
6748)
6749)
6750thePort (LogicalPort
6751lang 2
6752m 1
6753decl (Decl
6754n "ADC_CLK"
6755t "std_logic"
6756o 16
6757suid 97,0
6758)
6759)
6760)
6761*221 (CptPort
6762uid 3241,0
6763ps "OnEdgeStrategy"
6764shape (Triangle
6765uid 3242,0
6766ro 90
6767va (VaSet
6768vasetType 1
6769fg "0,65535,0"
6770)
6771xt "168000,83625,168750,84375"
6772)
6773tg (CPTG
6774uid 3243,0
6775ps "CptPortTextPlaceStrategy"
6776stg "RightVerticalLayoutStrategy"
6777f (Text
6778uid 3244,0
6779va (VaSet
6780)
6781xt "162100,83500,167000,84500"
6782st "trigger_veto"
6783ju 2
6784blo "167000,84300"
6785)
6786)
6787thePort (LogicalPort
6788m 1
6789decl (Decl
6790n "trigger_veto"
6791t "std_logic"
6792o 45
6793suid 98,0
6794i "'1'"
6795)
6796)
6797)
6798*222 (CptPort
6799uid 3245,0
6800ps "OnEdgeStrategy"
6801shape (Triangle
6802uid 3246,0
6803ro 90
6804va (VaSet
6805vasetType 1
6806fg "0,65535,0"
6807)
6808xt "139250,73625,140000,74375"
6809)
6810tg (CPTG
6811uid 3247,0
6812ps "CptPortTextPlaceStrategy"
6813stg "VerticalLayoutStrategy"
6814f (Text
6815uid 3248,0
6816va (VaSet
6817)
6818xt "141000,73500,148000,74500"
6819st "FTM_RS485_rx_d"
6820blo "141000,74300"
6821)
6822)
6823thePort (LogicalPort
6824decl (Decl
6825n "FTM_RS485_rx_d"
6826t "std_logic"
6827o 3
6828suid 99,0
6829)
6830)
6831)
6832*223 (CptPort
6833uid 3249,0
6834ps "OnEdgeStrategy"
6835shape (Triangle
6836uid 3250,0
6837ro 90
6838va (VaSet
6839vasetType 1
6840fg "0,65535,0"
6841)
6842xt "168000,80625,168750,81375"
6843)
6844tg (CPTG
6845uid 3251,0
6846ps "CptPortTextPlaceStrategy"
6847stg "RightVerticalLayoutStrategy"
6848f (Text
6849uid 3252,0
6850va (VaSet
6851)
6852xt "160100,80500,167000,81500"
6853st "FTM_RS485_tx_d"
6854ju 2
6855blo "167000,81300"
6856)
6857)
6858thePort (LogicalPort
6859m 1
6860decl (Decl
6861n "FTM_RS485_tx_d"
6862t "std_logic"
6863o 21
6864suid 100,0
6865)
6866)
6867)
6868*224 (CptPort
6869uid 3253,0
6870ps "OnEdgeStrategy"
6871shape (Triangle
6872uid 3254,0
6873ro 90
6874va (VaSet
6875vasetType 1
6876fg "0,65535,0"
6877)
6878xt "168000,79625,168750,80375"
6879)
6880tg (CPTG
6881uid 3255,0
6882ps "CptPortTextPlaceStrategy"
6883stg "RightVerticalLayoutStrategy"
6884f (Text
6885uid 3256,0
6886va (VaSet
6887)
6888xt "159600,79500,167000,80500"
6889st "FTM_RS485_rx_en"
6890ju 2
6891blo "167000,80300"
6892)
6893)
6894thePort (LogicalPort
6895m 1
6896decl (Decl
6897n "FTM_RS485_rx_en"
6898t "std_logic"
6899o 20
6900suid 101,0
6901)
6902)
6903)
6904*225 (CptPort
6905uid 3257,0
6906ps "OnEdgeStrategy"
6907shape (Triangle
6908uid 3258,0
6909ro 90
6910va (VaSet
6911vasetType 1
6912fg "0,65535,0"
6913)
6914xt "168000,81625,168750,82375"
6915)
6916tg (CPTG
6917uid 3259,0
6918ps "CptPortTextPlaceStrategy"
6919stg "RightVerticalLayoutStrategy"
6920f (Text
6921uid 3260,0
6922va (VaSet
6923)
6924xt "159700,81500,167000,82500"
6925st "FTM_RS485_tx_en"
6926ju 2
6927blo "167000,82300"
6928)
6929)
6930thePort (LogicalPort
6931m 1
6932decl (Decl
6933n "FTM_RS485_tx_en"
6934t "std_logic"
6935o 22
6936suid 102,0
6937)
6938)
6939)
6940*226 (CptPort
6941uid 3261,0
6942ps "OnEdgeStrategy"
6943shape (Triangle
6944uid 3262,0
6945ro 90
6946va (VaSet
6947vasetType 1
6948fg "0,65535,0"
6949)
6950xt "168000,84625,168750,85375"
6951)
6952tg (CPTG
6953uid 3263,0
6954ps "CptPortTextPlaceStrategy"
6955stg "RightVerticalLayoutStrategy"
6956f (Text
6957uid 3264,0
6958va (VaSet
6959)
6960xt "159900,84500,167000,85500"
6961st "w5300_state : (7:0)"
6962ju 2
6963blo "167000,85300"
6964)
6965)
6966thePort (LogicalPort
6967m 1
6968decl (Decl
6969n "w5300_state"
6970t "std_logic_vector"
6971b "(7 DOWNTO 0)"
6972eolc "-- state is encoded here ... useful for debugging."
6973posAdd 0
6974o 46
6975suid 103,0
6976)
6977)
6978)
6979*227 (CptPort
6980uid 3265,0
6981ps "OnEdgeStrategy"
6982shape (Triangle
6983uid 3266,0
6984ro 90
6985va (VaSet
6986vasetType 1
6987fg "0,65535,0"
6988)
6989xt "168000,76625,168750,77375"
6990)
6991tg (CPTG
6992uid 3267,0
6993ps "CptPortTextPlaceStrategy"
6994stg "RightVerticalLayoutStrategy"
6995f (Text
6996uid 3268,0
6997va (VaSet
6998)
6999xt "157900,76500,167000,77500"
7000st "debug_data_ram_empty"
7001ju 2
7002blo "167000,77300"
7003)
7004)
7005thePort (LogicalPort
7006m 1
7007decl (Decl
7008n "debug_data_ram_empty"
7009t "std_logic"
7010o 32
7011suid 104,0
7012)
7013)
7014)
7015*228 (CptPort
7016uid 3269,0
7017ps "OnEdgeStrategy"
7018shape (Triangle
7019uid 3270,0
7020ro 90
7021va (VaSet
7022vasetType 1
7023fg "0,65535,0"
7024)
7025xt "168000,77625,168750,78375"
7026)
7027tg (CPTG
7028uid 3271,0
7029ps "CptPortTextPlaceStrategy"
7030stg "RightVerticalLayoutStrategy"
7031f (Text
7032uid 3272,0
7033va (VaSet
7034)
7035xt "160400,77500,167000,78500"
7036st "debug_data_valid"
7037ju 2
7038blo "167000,78300"
7039)
7040)
7041thePort (LogicalPort
7042m 1
7043decl (Decl
7044n "debug_data_valid"
7045t "std_logic"
7046o 33
7047suid 105,0
7048)
7049)
7050)
7051*229 (CptPort
7052uid 3273,0
7053ps "OnEdgeStrategy"
7054shape (Triangle
7055uid 3274,0
7056ro 90
7057va (VaSet
7058vasetType 1
7059fg "0,65535,0"
7060)
7061xt "168000,82625,168750,83375"
7062)
7063tg (CPTG
7064uid 3275,0
7065ps "CptPortTextPlaceStrategy"
7066stg "RightVerticalLayoutStrategy"
7067f (Text
7068uid 3276,0
7069va (VaSet
7070)
7071xt "156600,82500,167000,83500"
7072st "mem_manager_state : (3:0)"
7073ju 2
7074blo "167000,83300"
7075)
7076)
7077thePort (LogicalPort
7078lang 2
7079m 1
7080decl (Decl
7081n "mem_manager_state"
7082t "std_logic_vector"
7083b "(3 DOWNTO 0)"
7084eolc "-- state is encoded here ... useful for debugging."
7085posAdd 0
7086o 39
7087suid 106,0
7088)
7089)
7090)
7091*230 (CptPort
7092uid 3277,0
7093ps "OnEdgeStrategy"
7094shape (Triangle
7095uid 3278,0
7096ro 90
7097va (VaSet
7098vasetType 1
7099fg "0,65535,0"
7100)
7101xt "168000,78625,168750,79375"
7102)
7103tg (CPTG
7104uid 3279,0
7105ps "CptPortTextPlaceStrategy"
7106stg "RightVerticalLayoutStrategy"
7107f (Text
7108uid 3280,0
7109va (VaSet
7110)
7111xt "160800,78500,167000,79500"
7112st "DG_state : (7:0)"
7113ju 2
7114blo "167000,79300"
7115)
7116)
7117thePort (LogicalPort
7118m 1
7119decl (Decl
7120n "DG_state"
7121t "std_logic_vector"
7122b "(7 downto 0)"
7123prec "-- for debugging"
7124preAdd 0
7125o 19
7126suid 108,0
7127)
7128)
7129)
7130*231 (CptPort
7131uid 3281,0
7132ps "OnEdgeStrategy"
7133shape (Triangle
7134uid 3282,0
7135ro 90
7136va (VaSet
7137vasetType 1
7138fg "0,65535,0"
7139)
7140xt "168000,85625,168750,86375"
7141)
7142tg (CPTG
7143uid 3283,0
7144ps "CptPortTextPlaceStrategy"
7145stg "RightVerticalLayoutStrategy"
7146f (Text
7147uid 3284,0
7148va (VaSet
7149)
7150xt "157100,85500,167000,86500"
7151st "socket_tx_free_out : (16:0)"
7152ju 2
7153blo "167000,86300"
7154)
7155)
7156thePort (LogicalPort
7157m 1
7158decl (Decl
7159n "socket_tx_free_out"
7160t "std_logic_vector"
7161b "(16 DOWNTO 0)"
7162eolc "-- 17bit value .. that's true"
7163posAdd 0
7164o 44
7165suid 109,0
7166)
7167)
7168)
7169]
7170shape (Rectangle
7171uid 3286,0
7172va (VaSet
7173vasetType 1
7174fg "0,65535,0"
7175lineColor "0,32896,0"
7176lineWidth 2
7177)
7178xt "140000,15000,168000,87000"
7179)
7180oxt "15000,-8000,43000,80000"
7181ttg (MlTextGroup
7182uid 3287,0
7183ps "CenterOffsetStrategy"
7184stg "VerticalLayoutStrategy"
7185textVec [
7186*232 (Text
7187uid 3288,0
7188va (VaSet
7189font "Arial,8,1"
7190)
7191xt "144200,80000,150400,81000"
7192st "FACT_FAD_lib"
7193blo "144200,80800"
7194tm "BdLibraryNameMgr"
7195)
7196*233 (Text
7197uid 3289,0
7198va (VaSet
7199font "Arial,8,1"
7200)
7201xt "144200,81000,154000,82000"
7202st "FAD_main_with_w53002"
7203blo "144200,81800"
7204tm "CptNameMgr"
7205)
7206*234 (Text
7207uid 3290,0
7208va (VaSet
7209font "Arial,8,1"
7210)
7211xt "144200,82000,145200,83000"
7212st "I0"
7213blo "144200,82800"
7214tm "InstanceNameMgr"
7215)
7216]
7217)
7218ga (GenericAssociation
7219uid 3291,0
7220ps "EdgeToEdgeStrategy"
7221matrix (Matrix
7222uid 3292,0
7223text (MLText
7224uid 3293,0
7225va (VaSet
7226font "Courier New,8,0"
7227)
7228xt "142000,14200,162000,15000"
7229st "RAMADDRWIDTH64b = 15    ( integer ) 
7230"
7231)
7232header ""
7233)
7234elements [
7235(GiElement
7236name "RAMADDRWIDTH64b"
7237type "integer"
7238value "15"
7239)
7240]
7241)
7242viewicon (ZoomableIcon
7243uid 3294,0
7244sl 0
7245va (VaSet
7246vasetType 1
7247fg "49152,49152,49152"
7248)
7249xt "140250,85250,141750,86750"
7250iconName "BlockDiagram.png"
7251iconMaskName "BlockDiagram.msk"
7252ftype 1
7253)
7254viewiconposition 0
7255portVis (PortSigDisplay
7256)
7257archFileType "UNKNOWN"
7258)
7259*235 (Wire
7260uid 286,0
7261shape (OrthoPolyLine
7262uid 287,0
7263va (VaSet
7264vasetType 3
7265)
7266xt "58750,21000,80250,21000"
7267pts [
7268"58750,21000"
7269"80250,21000"
7270]
7271)
7272start &70
7273end &27
7274sat 32
7275eat 32
7276st 0
7277sf 1
7278si 0
7279tg (WTG
7280uid 288,0
7281ps "ConnStartEndStrategy"
7282stg "STSignalDisplayStrategy"
7283f (Text
7284uid 289,0
7285va (VaSet
7286)
7287xt "71000,20000,72300,21000"
7288st "clk"
7289blo "71000,20800"
7290tm "WireNameMgr"
7291)
7292)
7293on &75
7294)
7295*236 (Wire
7296uid 318,0
7297shape (OrthoPolyLine
7298uid 319,0
7299va (VaSet
7300vasetType 3
7301lineWidth 2
7302)
7303xt "109750,21000,122250,21000"
7304pts [
7305"109750,21000"
7306"122250,21000"
7307]
7308)
7309start &19
7310end &158
7311sat 32
7312eat 32
7313sty 1
7314st 0
7315sf 1
7316si 0
7317tg (WTG
7318uid 320,0
7319ps "ConnStartEndStrategy"
7320stg "STSignalDisplayStrategy"
7321f (Text
7322uid 321,0
7323va (VaSet
7324)
7325xt "111000,20000,117000,21000"
7326st "wiz_addr : (9:0)"
7327blo "111000,20800"
7328tm "WireNameMgr"
7329)
7330)
7331on &76
7332)
7333*237 (Wire
7334uid 324,0
7335shape (OrthoPolyLine
7336uid 325,0
7337va (VaSet
7338vasetType 3
7339lineWidth 2
7340)
7341xt "109750,22000,122250,22000"
7342pts [
7343"109750,22000"
7344"122250,22000"
7345]
7346)
7347start &20
7348end &159
7349sat 32
7350eat 32
7351sty 1
7352st 0
7353sf 1
7354si 0
7355tg (WTG
7356uid 326,0
7357ps "ConnStartEndStrategy"
7358stg "STSignalDisplayStrategy"
7359f (Text
7360uid 327,0
7361va (VaSet
7362)
7363xt "111000,21000,117300,22000"
7364st "wiz_data : (15:0)"
7365blo "111000,21800"
7366tm "WireNameMgr"
7367)
7368)
7369on &77
7370)
7371*238 (Wire
7372uid 330,0
7373shape (OrthoPolyLine
7374uid 331,0
7375va (VaSet
7376vasetType 3
7377)
7378xt "109750,25000,122250,25000"
7379pts [
7380"109750,25000"
7381"122250,25000"
7382]
7383)
7384start &23
7385end &160
7386sat 32
7387eat 32
7388st 0
7389sf 1
7390si 0
7391tg (WTG
7392uid 332,0
7393ps "ConnStartEndStrategy"
7394stg "STSignalDisplayStrategy"
7395f (Text
7396uid 333,0
7397va (VaSet
7398)
7399xt "111000,24000,113600,25000"
7400st "wiz_rd"
7401blo "111000,24800"
7402tm "WireNameMgr"
7403)
7404)
7405on &78
7406)
7407*239 (Wire
7408uid 336,0
7409shape (OrthoPolyLine
7410uid 337,0
7411va (VaSet
7412vasetType 3
7413)
7414xt "109750,26000,122250,26000"
7415pts [
7416"109750,26000"
7417"122250,26000"
7418]
7419)
7420start &22
7421end &161
7422sat 32
7423eat 32
7424st 0
7425sf 1
7426si 0
7427tg (WTG
7428uid 338,0
7429ps "ConnStartEndStrategy"
7430stg "STSignalDisplayStrategy"
7431f (Text
7432uid 339,0
7433va (VaSet
7434)
7435xt "111000,25000,113700,26000"
7436st "wiz_wr"
7437blo "111000,25800"
7438tm "WireNameMgr"
7439)
7440)
7441on &79
7442)
7443*240 (Wire
7444uid 374,0
7445shape (OrthoPolyLine
7446uid 375,0
7447va (VaSet
7448vasetType 3
7449lineWidth 2
7450)
7451xt "109750,42000,122250,48000"
7452pts [
7453"109750,42000"
7454"120000,42000"
7455"120000,48000"
7456"122250,48000"
7457]
7458)
7459start &41
7460end &83
7461sat 32
7462eat 32
7463sty 1
7464st 0
7465sf 1
7466si 0
7467tg (WTG
7468uid 376,0
7469ps "ConnStartEndStrategy"
7470stg "STSignalDisplayStrategy"
7471f (Text
7472uid 377,0
7473va (VaSet
7474)
7475xt "111000,41000,117500,42000"
7476st "sensor_cs : (3:0)"
7477blo "111000,41800"
7478tm "WireNameMgr"
7479)
7480)
7481on &87
7482)
7483*241 (Wire
7484uid 380,0
7485shape (OrthoPolyLine
7486uid 381,0
7487va (VaSet
7488vasetType 3
7489)
7490xt "109750,51000,122250,51000"
7491pts [
7492"109750,51000"
7493"122250,51000"
7494]
7495)
7496start &38
7497end &81
7498sat 32
7499eat 32
7500st 0
7501sf 1
7502si 0
7503tg (WTG
7504uid 382,0
7505ps "ConnStartEndStrategy"
7506stg "STSignalDisplayStrategy"
7507f (Text
7508uid 383,0
7509va (VaSet
7510)
7511xt "111000,50000,112700,51000"
7512st "sclk"
7513blo "111000,50800"
7514tm "WireNameMgr"
7515)
7516)
7517on &88
7518)
7519*242 (Wire
7520uid 386,0
7521shape (OrthoPolyLine
7522uid 387,0
7523va (VaSet
7524vasetType 3
7525)
7526xt "109750,52000,122250,52000"
7527pts [
7528"109750,52000"
7529"122250,52000"
7530]
7531)
7532start &39
7533end &82
7534sat 32
7535eat 32
7536st 0
7537sf 1
7538si 0
7539tg (WTG
7540uid 388,0
7541ps "ConnStartEndStrategy"
7542stg "STSignalDisplayStrategy"
7543f (Text
7544uid 389,0
7545va (VaSet
7546)
7547xt "111000,51000,112400,52000"
7548st "sio"
7549blo "111000,51800"
7550tm "WireNameMgr"
7551)
7552)
7553on &89
7554)
7555*243 (Wire
7556uid 426,0
7557shape (OrthoPolyLine
7558uid 427,0
7559va (VaSet
7560vasetType 3
7561)
7562xt "58750,32000,80250,32000"
7563pts [
7564"58750,32000"
7565"80250,32000"
7566]
7567)
7568start &91
7569end &15
7570sat 32
7571eat 32
7572st 0
7573sf 1
7574tg (WTG
7575uid 428,0
7576ps "ConnStartEndStrategy"
7577stg "STSignalDisplayStrategy"
7578f (Text
7579uid 429,0
7580va (VaSet
7581)
7582xt "71000,31000,73800,32000"
7583st "trigger"
7584blo "71000,31800"
7585tm "WireNameMgr"
7586)
7587)
7588on &95
7589)
7590*244 (Wire
7591uid 442,0
7592shape (OrthoPolyLine
7593uid 443,0
7594va (VaSet
7595vasetType 3
7596lineWidth 2
7597)
7598xt "58000,34000,80250,42000"
7599pts [
7600"80250,34000"
7601"64000,34000"
7602"64000,42000"
7603"58000,42000"
7604]
7605)
7606start &17
7607end &96
7608sat 32
7609eat 2
7610sty 1
7611st 0
7612sf 1
7613si 0
7614tg (WTG
7615uid 446,0
7616ps "ConnStartEndStrategy"
7617stg "STSignalDisplayStrategy"
7618f (Text
7619uid 447,0
7620va (VaSet
7621)
7622xt "71000,33000,76900,34000"
7623st "board_id : (3:0)"
7624blo "71000,33800"
7625tm "WireNameMgr"
7626)
7627)
7628on &100
7629)
7630*245 (Wire
7631uid 450,0
7632shape (OrthoPolyLine
7633uid 451,0
7634va (VaSet
7635vasetType 3
7636lineWidth 2
7637)
7638xt "58000,35000,80250,43000"
7639pts [
7640"80250,35000"
7641"65000,35000"
7642"65000,43000"
7643"58000,43000"
7644]
7645)
7646start &18
7647end &96
7648sat 32
7649eat 2
7650sty 1
7651st 0
7652sf 1
7653si 0
7654tg (WTG
7655uid 454,0
7656ps "ConnStartEndStrategy"
7657stg "STSignalDisplayStrategy"
7658f (Text
7659uid 455,0
7660va (VaSet
7661)
7662xt "71000,34000,76700,35000"
7663st "crate_id : (1:0)"
7664blo "71000,34800"
7665tm "WireNameMgr"
7666)
7667)
7668on &101
7669)
7670*246 (Wire
7671uid 530,0
7672shape (OrthoPolyLine
7673uid 531,0
7674va (VaSet
7675vasetType 3
7676lineWidth 2
7677)
7678xt "58000,42000,80250,53000"
7679pts [
7680"80250,42000"
7681"68000,42000"
7682"68000,53000"
7683"58000,53000"
7684]
7685)
7686start &28
7687end &110
7688sat 32
7689eat 2
7690sty 1
7691st 0
7692sf 1
7693si 0
7694tg (WTG
7695uid 534,0
7696ps "ConnStartEndStrategy"
7697stg "STSignalDisplayStrategy"
7698f (Text
7699uid 535,0
7700va (VaSet
7701)
7702xt "71000,41000,79000,42000"
7703st "adc_otr_array : (3:0)"
7704blo "71000,41800"
7705tm "WireNameMgr"
7706)
7707)
7708on &114
7709)
7710*247 (Wire
7711uid 538,0
7712shape (OrthoPolyLine
7713uid 539,0
7714va (VaSet
7715vasetType 3
7716lineWidth 2
7717)
7718xt "58000,48000,80250,55000"
7719pts [
7720"80250,48000"
7721"70000,48000"
7722"70000,55000"
7723"58000,55000"
7724]
7725)
7726start &29
7727end &110
7728sat 32
7729eat 2
7730sty 1
7731st 0
7732sf 1
7733si 0
7734tg (WTG
7735uid 542,0
7736ps "ConnStartEndStrategy"
7737stg "STSignalDisplayStrategy"
7738f (Text
7739uid 543,0
7740va (VaSet
7741)
7742xt "71000,47000,76900,48000"
7743st "adc_data_array"
7744blo "71000,47800"
7745tm "WireNameMgr"
7746)
7747)
7748on &115
7749)
7750*248 (Wire
7751uid 546,0
7752shape (OrthoPolyLine
7753uid 547,0
7754va (VaSet
7755vasetType 3
7756)
7757xt "58000,43000,80250,54000"
7758pts [
7759"80250,43000"
7760"69000,43000"
7761"69000,54000"
7762"58000,54000"
7763]
7764)
7765start &16
7766end &110
7767sat 32
7768eat 1
7769st 0
7770sf 1
7771si 0
7772tg (WTG
7773uid 550,0
7774ps "ConnStartEndStrategy"
7775stg "STSignalDisplayStrategy"
7776f (Text
7777uid 551,0
7778va (VaSet
7779)
7780xt "71000,42000,74200,43000"
7781st "adc_oeb"
7782blo "71000,42800"
7783tm "WireNameMgr"
7784)
7785)
7786on &116
7787)
7788*249 (Wire
7789uid 554,0
7790shape (OrthoPolyLine
7791uid 555,0
7792va (VaSet
7793vasetType 3
7794)
7795xt "40750,54000,50000,54000"
7796pts [
7797"50000,54000"
7798"40750,54000"
7799]
7800)
7801start &110
7802end &106
7803sat 2
7804eat 32
7805st 0
7806sf 1
7807tg (WTG
7808uid 558,0
7809ps "ConnStartEndStrategy"
7810stg "STSignalDisplayStrategy"
7811f (Text
7812uid 559,0
7813va (VaSet
7814)
7815xt "42000,53000,45200,54000"
7816st "adc_oeb"
7817blo "42000,53800"
7818tm "WireNameMgr"
7819)
7820)
7821on &116
7822)
7823*250 (Wire
7824uid 562,0
7825shape (OrthoPolyLine
7826uid 563,0
7827va (VaSet
7828vasetType 3
7829)
7830xt "40750,53000,50000,53000"
7831pts [
7832"40750,53000"
7833"50000,53000"
7834]
7835)
7836start &105
7837end &110
7838sat 32
7839eat 1
7840st 0
7841sf 1
7842tg (WTG
7843uid 566,0
7844ps "ConnStartEndStrategy"
7845stg "STSignalDisplayStrategy"
7846f (Text
7847uid 567,0
7848va (VaSet
7849)
7850xt "42000,52000,44900,53000"
7851st "adc_otr"
7852blo "42000,52800"
7853tm "WireNameMgr"
7854)
7855)
7856on &117
7857)
7858*251 (Wire
7859uid 570,0
7860shape (OrthoPolyLine
7861uid 571,0
7862va (VaSet
7863vasetType 3
7864lineWidth 2
7865)
7866xt "40750,55000,50000,55000"
7867pts [
7868"40750,55000"
7869"50000,55000"
7870]
7871)
7872start &104
7873end &110
7874sat 32
7875eat 1
7876sty 1
7877st 0
7878sf 1
7879tg (WTG
7880uid 574,0
7881ps "ConnStartEndStrategy"
7882stg "STSignalDisplayStrategy"
7883f (Text
7884uid 575,0
7885va (VaSet
7886)
7887xt "42000,54000,48400,55000"
7888st "adc_data : (11:0)"
7889blo "42000,54800"
7890tm "WireNameMgr"
7891)
7892)
7893on &118
7894)
7895*252 (Wire
7896uid 578,0
7897shape (OrthoPolyLine
7898uid 579,0
7899va (VaSet
7900vasetType 3
7901)
7902xt "24000,53000,29250,53000"
7903pts [
7904"29250,53000"
7905"24000,53000"
7906]
7907)
7908start &103
7909sat 32
7910eat 16
7911st 0
7912sf 1
7913tg (WTG
7914uid 582,0
7915ps "ConnStartEndStrategy"
7916stg "STSignalDisplayStrategy"
7917f (Text
7918uid 583,0
7919va (VaSet
7920)
7921xt "25000,52000,29000,53000"
7922st "ADC_CLK"
7923blo "25000,52800"
7924tm "WireNameMgr"
7925)
7926)
7927on &155
7928)
7929*253 (Wire
7930uid 769,0
7931shape (OrthoPolyLine
7932uid 770,0
7933va (VaSet
7934vasetType 3
7935)
7936xt "109750,24000,116000,24000"
7937pts [
7938"109750,24000"
7939"116000,24000"
7940]
7941)
7942start &13
7943sat 32
7944eat 16
7945st 0
7946sf 1
7947si 0
7948tg (WTG
7949uid 773,0
7950ps "ConnStartEndStrategy"
7951stg "STSignalDisplayStrategy"
7952f (Text
7953uid 774,0
7954va (VaSet
7955)
7956xt "111000,23000,114600,24000"
7957st "wiz_reset"
7958blo "111000,23800"
7959tm "WireNameMgr"
7960)
7961)
7962on &119
7963)
7964*254 (Wire
7965uid 777,0
7966shape (OrthoPolyLine
7967uid 778,0
7968va (VaSet
7969vasetType 3
7970lineWidth 2
7971)
7972xt "109750,70000,116000,70000"
7973pts [
7974"109750,70000"
7975"116000,70000"
7976]
7977)
7978start &14
7979sat 32
7980eat 16
7981sty 1
7982st 0
7983sf 1
7984si 0
7985tg (WTG
7986uid 781,0
7987ps "ConnStartEndStrategy"
7988stg "STSignalDisplayStrategy"
7989f (Text
7990uid 782,0
7991va (VaSet
7992)
7993xt "111000,69000,115000,70000"
7994st "led : (7:0)"
7995blo "111000,69800"
7996tm "WireNameMgr"
7997)
7998)
7999on &120
8000)
8001*255 (Wire
8002uid 785,0
8003shape (OrthoPolyLine
8004uid 786,0
8005va (VaSet
8006vasetType 3
8007)
8008xt "109750,28000,122250,28000"
8009pts [
8010"109750,28000"
8011"122250,28000"
8012]
8013)
8014start &21
8015end &163
8016sat 32
8017eat 32
8018st 0
8019sf 1
8020si 0
8021tg (WTG
8022uid 789,0
8023ps "ConnStartEndStrategy"
8024stg "STSignalDisplayStrategy"
8025f (Text
8026uid 790,0
8027va (VaSet
8028)
8029xt "111000,27000,113700,28000"
8030st "wiz_cs"
8031blo "111000,27800"
8032tm "WireNameMgr"
8033)
8034)
8035on &121
8036)
8037*256 (Wire
8038uid 793,0
8039shape (OrthoPolyLine
8040uid 794,0
8041va (VaSet
8042vasetType 3
8043)
8044xt "109750,27000,122250,27000"
8045pts [
8046"122250,27000"
8047"109750,27000"
8048]
8049)
8050start &162
8051end &24
8052sat 32
8053eat 32
8054st 0
8055sf 1
8056si 0
8057tg (WTG
8058uid 797,0
8059ps "ConnStartEndStrategy"
8060stg "STSignalDisplayStrategy"
8061f (Text
8062uid 798,0
8063va (VaSet
8064)
8065xt "111000,26000,113700,27000"
8066st "wiz_int"
8067blo "111000,26800"
8068tm "WireNameMgr"
8069)
8070)
8071on &122
8072)
8073*257 (Wire
8074uid 801,0
8075shape (OrthoPolyLine
8076uid 802,0
8077va (VaSet
8078vasetType 3
8079)
8080xt "109750,40000,116000,40000"
8081pts [
8082"109750,40000"
8083"116000,40000"
8084]
8085)
8086start &40
8087sat 32
8088eat 16
8089st 0
8090sf 1
8091si 0
8092tg (WTG
8093uid 805,0
8094ps "ConnStartEndStrategy"
8095stg "STSignalDisplayStrategy"
8096f (Text
8097uid 806,0
8098va (VaSet
8099)
8100xt "111000,39000,113800,40000"
8101st "dac_cs"
8102blo "111000,39800"
8103tm "WireNameMgr"
8104)
8105)
8106on &123
8107)
8108*258 (Wire
8109uid 809,0
8110shape (OrthoPolyLine
8111uid 810,0
8112va (VaSet
8113vasetType 3
8114)
8115xt "109750,53000,116000,53000"
8116pts [
8117"109750,53000"
8118"116000,53000"
8119]
8120)
8121start &42
8122sat 32
8123eat 16
8124st 0
8125sf 1
8126si 0
8127tg (WTG
8128uid 813,0
8129ps "ConnStartEndStrategy"
8130stg "STSignalDisplayStrategy"
8131f (Text
8132uid 814,0
8133va (VaSet
8134)
8135xt "111000,52000,113000,53000"
8136st "mosi"
8137blo "111000,52800"
8138tm "WireNameMgr"
8139)
8140)
8141on &124
8142)
8143*259 (Wire
8144uid 817,0
8145shape (OrthoPolyLine
8146uid 818,0
8147va (VaSet
8148vasetType 3
8149)
8150xt "70000,66000,80250,66000"
8151pts [
8152"80250,66000"
8153"70000,66000"
8154]
8155)
8156start &43
8157sat 32
8158eat 16
8159st 0
8160sf 1
8161si 0
8162tg (WTG
8163uid 821,0
8164ps "ConnStartEndStrategy"
8165stg "STSignalDisplayStrategy"
8166f (Text
8167uid 822,0
8168va (VaSet
8169)
8170xt "71000,65000,74000,66000"
8171st "denable"
8172blo "71000,65800"
8173tm "WireNameMgr"
8174)
8175)
8176on &125
8177)
8178*260 (Wire
8179uid 825,0
8180shape (OrthoPolyLine
8181uid 826,0
8182va (VaSet
8183vasetType 3
8184)
8185xt "70000,23000,80250,23000"
8186pts [
8187"80250,23000"
8188"70000,23000"
8189]
8190)
8191start &25
8192sat 32
8193eat 16
8194st 0
8195sf 1
8196si 0
8197tg (WTG
8198uid 829,0
8199ps "ConnStartEndStrategy"
8200stg "STSignalDisplayStrategy"
8201f (Text
8202uid 830,0
8203va (VaSet
8204)
8205xt "71000,22000,75500,23000"
8206st "CLK_25_PS"
8207blo "71000,22800"
8208tm "WireNameMgr"
8209)
8210)
8211on &126
8212)
8213*261 (Wire
8214uid 833,0
8215shape (OrthoPolyLine
8216uid 834,0
8217va (VaSet
8218vasetType 3
8219)
8220xt "70000,22000,80250,22000"
8221pts [
8222"80250,22000"
8223"70000,22000"
8224]
8225)
8226start &26
8227sat 32
8228eat 16
8229st 0
8230sf 1
8231si 0
8232tg (WTG
8233uid 837,0
8234ps "ConnStartEndStrategy"
8235stg "STSignalDisplayStrategy"
8236f (Text
8237uid 838,0
8238va (VaSet
8239)
8240xt "71000,21000,74100,22000"
8241st "CLK_50"
8242blo "71000,21800"
8243tm "WireNameMgr"
8244)
8245)
8246on &127
8247)
8248*262 (Wire
8249uid 841,0
8250shape (OrthoPolyLine
8251uid 842,0
8252va (VaSet
8253vasetType 3
8254lineWidth 2
8255)
8256xt "70000,62000,80250,62000"
8257pts [
8258"80250,62000"
8259"70000,62000"
8260]
8261)
8262start &30
8263sat 32
8264eat 16
8265sty 1
8266st 0
8267sf 1
8268si 0
8269tg (WTG
8270uid 845,0
8271ps "ConnStartEndStrategy"
8272stg "STSignalDisplayStrategy"
8273f (Text
8274uid 846,0
8275va (VaSet
8276)
8277xt "71000,61000,79500,62000"
8278st "drs_channel_id : (3:0)"
8279blo "71000,61800"
8280tm "WireNameMgr"
8281)
8282)
8283on &128
8284)
8285*263 (Wire
8286uid 849,0
8287shape (OrthoPolyLine
8288uid 850,0
8289va (VaSet
8290vasetType 3
8291)
8292xt "70000,67000,80250,67000"
8293pts [
8294"80250,67000"
8295"70000,67000"
8296]
8297)
8298start &31
8299ss 0
8300sat 32
8301eat 16
8302st 0
8303sf 1
8304si 0
8305tg (WTG
8306uid 853,0
8307ps "ConnStartEndStrategy"
8308stg "STSignalDisplayStrategy"
8309f (Text
8310uid 854,0
8311va (VaSet
8312)
8313xt "71000,66000,75300,67000"
8314st "drs_dwrite"
8315blo "71000,66800"
8316tm "WireNameMgr"
8317)
8318)
8319on &129
8320)
8321*264 (Wire
8322uid 857,0
8323shape (OrthoPolyLine
8324uid 858,0
8325va (VaSet
8326vasetType 3
8327)
8328xt "70000,64000,80250,64000"
8329pts [
8330"80250,64000"
8331"70000,64000"
8332]
8333)
8334start &36
8335sat 32
8336eat 16
8337st 0
8338sf 1
8339si 0
8340tg (WTG
8341uid 861,0
8342ps "ConnStartEndStrategy"
8343stg "STSignalDisplayStrategy"
8344f (Text
8345uid 862,0
8346va (VaSet
8347)
8348xt "71000,63000,75200,64000"
8349st "RSRLOAD"
8350blo "71000,63800"
8351tm "WireNameMgr"
8352)
8353)
8354on &130
8355)
8356*265 (Wire
8357uid 865,0
8358shape (OrthoPolyLine
8359uid 866,0
8360va (VaSet
8361vasetType 3
8362)
8363xt "70000,65000,80250,65000"
8364pts [
8365"80250,65000"
8366"70000,65000"
8367]
8368)
8369start &37
8370sat 32
8371eat 16
8372st 0
8373sf 1
8374si 0
8375tg (WTG
8376uid 869,0
8377ps "ConnStartEndStrategy"
8378stg "STSignalDisplayStrategy"
8379f (Text
8380uid 870,0
8381va (VaSet
8382)
8383xt "71000,64000,74000,65000"
8384st "SRCLK"
8385blo "71000,64800"
8386tm "WireNameMgr"
8387)
8388)
8389on &131
8390)
8391*266 (Wire
8392uid 873,0
8393shape (OrthoPolyLine
8394uid 874,0
8395va (VaSet
8396vasetType 3
8397)
8398xt "70000,58000,80250,58000"
8399pts [
8400"70000,58000"
8401"80250,58000"
8402]
8403)
8404end &32
8405sat 16
8406eat 32
8407st 0
8408sf 1
8409si 0
8410tg (WTG
8411uid 877,0
8412ps "ConnStartEndStrategy"
8413stg "STSignalDisplayStrategy"
8414f (Text
8415uid 878,0
8416va (VaSet
8417)
8418xt "71000,57000,76400,58000"
8419st "SROUT_in_0"
8420blo "71000,57800"
8421tm "WireNameMgr"
8422)
8423)
8424on &132
8425)
8426*267 (Wire
8427uid 881,0
8428shape (OrthoPolyLine
8429uid 882,0
8430va (VaSet
8431vasetType 3
8432)
8433xt "70000,59000,80250,59000"
8434pts [
8435"70000,59000"
8436"80250,59000"
8437]
8438)
8439end &33
8440sat 16
8441eat 32
8442st 0
8443sf 1
8444si 0
8445tg (WTG
8446uid 885,0
8447ps "ConnStartEndStrategy"
8448stg "STSignalDisplayStrategy"
8449f (Text
8450uid 886,0
8451va (VaSet
8452)
8453xt "71000,58000,76400,59000"
8454st "SROUT_in_1"
8455blo "71000,58800"
8456tm "WireNameMgr"
8457)
8458)
8459on &133
8460)
8461*268 (Wire
8462uid 889,0
8463shape (OrthoPolyLine
8464uid 890,0
8465va (VaSet
8466vasetType 3
8467)
8468xt "70000,60000,80250,60000"
8469pts [
8470"70000,60000"
8471"80250,60000"
8472]
8473)
8474end &34
8475sat 16
8476eat 32
8477st 0
8478sf 1
8479si 0
8480tg (WTG
8481uid 893,0
8482ps "ConnStartEndStrategy"
8483stg "STSignalDisplayStrategy"
8484f (Text
8485uid 894,0
8486va (VaSet
8487)
8488xt "71000,59000,76400,60000"
8489st "SROUT_in_2"
8490blo "71000,59800"
8491tm "WireNameMgr"
8492)
8493)
8494on &134
8495)
8496*269 (Wire
8497uid 897,0
8498shape (OrthoPolyLine
8499uid 898,0
8500va (VaSet
8501vasetType 3
8502)
8503xt "70000,61000,80250,61000"
8504pts [
8505"70000,61000"
8506"80250,61000"
8507]
8508)
8509end &35
8510sat 16
8511eat 32
8512st 0
8513sf 1
8514si 0
8515tg (WTG
8516uid 901,0
8517ps "ConnStartEndStrategy"
8518stg "STSignalDisplayStrategy"
8519f (Text
8520uid 902,0
8521va (VaSet
8522)
8523xt "71000,60000,76400,61000"
8524st "SROUT_in_3"
8525blo "71000,60800"
8526tm "WireNameMgr"
8527)
8528)
8529on &135
8530)
8531*270 (Wire
8532uid 1437,0
8533shape (OrthoPolyLine
8534uid 1438,0
8535va (VaSet
8536vasetType 3
8537)
8538xt "73000,72000,80250,72000"
8539pts [
8540"80250,72000"
8541"73000,72000"
8542]
8543)
8544start &53
8545sat 32
8546eat 16
8547st 0
8548sf 1
8549si 0
8550tg (WTG
8551uid 1441,0
8552ps "ConnStartEndStrategy"
8553stg "STSignalDisplayStrategy"
8554f (Text
8555uid 1442,0
8556va (VaSet
8557)
8558xt "76000,72000,79700,73000"
8559st "SRIN_out"
8560blo "76000,72800"
8561tm "WireNameMgr"
8562)
8563)
8564on &136
8565)
8566*271 (Wire
8567uid 1445,0
8568shape (OrthoPolyLine
8569uid 1446,0
8570va (VaSet
8571vasetType 3
8572)
8573xt "109750,80000,115000,80000"
8574pts [
8575"109750,80000"
8576"115000,80000"
8577]
8578)
8579start &46
8580sat 32
8581eat 16
8582st 0
8583sf 1
8584si 0
8585tg (WTG
8586uid 1449,0
8587ps "ConnStartEndStrategy"
8588stg "STSignalDisplayStrategy"
8589f (Text
8590uid 1450,0
8591va (VaSet
8592)
8593xt "111000,79000,113500,80000"
8594st "amber"
8595blo "111000,79800"
8596tm "WireNameMgr"
8597)
8598)
8599on &137
8600)
8601*272 (Wire
8602uid 1453,0
8603shape (OrthoPolyLine
8604uid 1454,0
8605va (VaSet
8606vasetType 3
8607)
8608xt "109750,79000,114000,79000"
8609pts [
8610"109750,79000"
8611"114000,79000"
8612]
8613)
8614start &52
8615sat 32
8616eat 16
8617st 0
8618sf 1
8619si 0
8620tg (WTG
8621uid 1457,0
8622ps "ConnStartEndStrategy"
8623stg "STSignalDisplayStrategy"
8624f (Text
8625uid 1458,0
8626va (VaSet
8627)
8628xt "111000,78000,112500,79000"
8629st "red"
8630blo "111000,78800"
8631tm "WireNameMgr"
8632)
8633)
8634on &138
8635)
8636*273 (Wire
8637uid 1461,0
8638shape (OrthoPolyLine
8639uid 1462,0
8640va (VaSet
8641vasetType 3
8642)
8643xt "109750,78000,114000,78000"
8644pts [
8645"109750,78000"
8646"114000,78000"
8647]
8648)
8649start &50
8650sat 32
8651eat 16
8652st 0
8653sf 1
8654si 0
8655tg (WTG
8656uid 1465,0
8657ps "ConnStartEndStrategy"
8658stg "STSignalDisplayStrategy"
8659f (Text
8660uid 1466,0
8661va (VaSet
8662)
8663xt "111000,77000,113400,78000"
8664st "green"
8665blo "111000,77800"
8666tm "WireNameMgr"
8667)
8668)
8669on &139
8670)
8671*274 (Wire
8672uid 1469,0
8673shape (OrthoPolyLine
8674uid 1470,0
8675va (VaSet
8676vasetType 3
8677lineWidth 2
8678)
8679xt "109750,77000,121000,77000"
8680pts [
8681"109750,77000"
8682"121000,77000"
8683]
8684)
8685start &47
8686sat 32
8687eat 16
8688sty 1
8689st 0
8690sf 1
8691si 0
8692tg (WTG
8693uid 1473,0
8694ps "ConnStartEndStrategy"
8695stg "STSignalDisplayStrategy"
8696f (Text
8697uid 1474,0
8698va (VaSet
8699)
8700xt "111000,76000,119600,77000"
8701st "counter_result : (11:0)"
8702blo "111000,76800"
8703tm "WireNameMgr"
8704)
8705)
8706on &140
8707)
8708*275 (Wire
8709uid 1477,0
8710shape (OrthoPolyLine
8711uid 1478,0
8712va (VaSet
8713vasetType 3
8714)
8715xt "109750,75000,120000,75000"
8716pts [
8717"109750,75000"
8718"120000,75000"
8719]
8720)
8721start &45
8722sat 32
8723eat 16
8724st 0
8725sf 1
8726si 0
8727tg (WTG
8728uid 1481,0
8729ps "ConnStartEndStrategy"
8730stg "STSignalDisplayStrategy"
8731f (Text
8732uid 1482,0
8733va (VaSet
8734)
8735xt "111000,74000,119200,75000"
8736st "alarm_refclk_too_low"
8737blo "111000,74800"
8738tm "WireNameMgr"
8739)
8740)
8741on &141
8742)
8743*276 (Wire
8744uid 1485,0
8745shape (OrthoPolyLine
8746uid 1486,0
8747va (VaSet
8748vasetType 3
8749)
8750xt "109750,74000,121000,74000"
8751pts [
8752"109750,74000"
8753"121000,74000"
8754]
8755)
8756start &44
8757sat 32
8758eat 16
8759st 0
8760sf 1
8761si 0
8762tg (WTG
8763uid 1489,0
8764ps "ConnStartEndStrategy"
8765stg "STSignalDisplayStrategy"
8766f (Text
8767uid 1490,0
8768va (VaSet
8769)
8770xt "111000,73000,119600,74000"
8771st "alarm_refclk_too_high"
8772blo "111000,73800"
8773tm "WireNameMgr"
8774)
8775)
8776on &142
8777)
8778*277 (Wire
8779uid 1503,0
8780shape (OrthoPolyLine
8781uid 1504,0
8782va (VaSet
8783vasetType 3
8784lineWidth 2
8785)
8786xt "73000,75000,80250,75000"
8787pts [
8788"73000,75000"
8789"80250,75000"
8790]
8791)
8792end &48
8793sat 16
8794eat 32
8795sty 1
8796st 0
8797sf 1
8798si 0
8799tg (WTG
8800uid 1507,0
8801ps "ConnStartEndStrategy"
8802stg "STSignalDisplayStrategy"
8803f (Text
8804uid 1508,0
8805va (VaSet
8806)
8807xt "74000,74000,79500,75000"
8808st "D_T_in : (1:0)"
8809blo "74000,74800"
8810tm "WireNameMgr"
8811)
8812)
8813on &147
8814)
8815*278 (Wire
8816uid 1529,0
8817shape (OrthoPolyLine
8818uid 1530,0
8819va (VaSet
8820vasetType 3
8821)
8822xt "66750,76000,80250,79000"
8823pts [
8824"66750,79000"
8825"70000,79000"
8826"70000,76000"
8827"80250,76000"
8828]
8829)
8830start &149
8831end &49
8832sat 32
8833eat 32
8834st 0
8835sf 1
8836si 0
8837tg (WTG
8838uid 1531,0
8839ps "ConnStartEndStrategy"
8840stg "STSignalDisplayStrategy"
8841f (Text
8842uid 1532,0
8843va (VaSet
8844)
8845xt "68750,78000,72650,79000"
8846st "REF_CLK"
8847blo "68750,78800"
8848tm "WireNameMgr"
8849)
8850)
8851on &156
8852)
8853*279 (Wire
8854uid 1533,0
8855shape (OrthoPolyLine
8856uid 1534,0
8857va (VaSet
8858vasetType 3
8859)
8860xt "35000,70000,45000,70000"
8861pts [
8862"35000,70000"
8863"45000,70000"
8864]
8865)
8866start &143
8867sat 2
8868eat 16
8869st 0
8870sf 1
8871si 0
8872tg (WTG
8873uid 1539,0
8874ps "ConnStartEndStrategy"
8875stg "STSignalDisplayStrategy"
8876f (Text
8877uid 1540,0
8878va (VaSet
8879)
8880xt "37000,69000,42500,70000"
8881st "D_T_in : (1:0)"
8882blo "37000,69800"
8883tm "WireNameMgr"
8884)
8885)
8886on &147
8887)
8888*280 (Wire
8889uid 1561,0
8890shape (OrthoPolyLine
8891uid 1562,0
8892va (VaSet
8893vasetType 3
8894lineWidth 2
8895)
8896xt "72000,77000,80250,77000"
8897pts [
8898"72000,77000"
8899"80250,77000"
8900]
8901)
8902end &51
8903sat 16
8904eat 32
8905sty 1
8906st 0
8907sf 1
8908si 0
8909tg (WTG
8910uid 1565,0
8911ps "ConnStartEndStrategy"
8912stg "STSignalDisplayStrategy"
8913f (Text
8914uid 1566,0
8915va (VaSet
8916)
8917xt "73000,76000,79100,77000"
8918st "plllock_in : (3:0)"
8919blo "73000,76800"
8920tm "WireNameMgr"
8921)
8922)
8923on &154
8924)
8925*281 (Wire
8926uid 1567,0
8927shape (OrthoPolyLine
8928uid 1568,0
8929va (VaSet
8930vasetType 3
8931)
8932xt "35000,71000,45000,71000"
8933pts [
8934"35000,71000"
8935"45000,71000"
8936]
8937)
8938start &143
8939sat 2
8940eat 16
8941st 0
8942sf 1
8943si 0
8944tg (WTG
8945uid 1573,0
8946ps "ConnStartEndStrategy"
8947stg "STSignalDisplayStrategy"
8948f (Text
8949uid 1574,0
8950va (VaSet
8951)
8952xt "37000,70000,43100,71000"
8953st "plllock_in : (3:0)"
8954blo "37000,70800"
8955tm "WireNameMgr"
8956)
8957)
8958on &154
8959)
8960*282 (Wire
8961uid 1684,0
8962shape (OrthoPolyLine
8963uid 1685,0
8964va (VaSet
8965vasetType 3
8966)
8967xt "70000,24000,80250,24000"
8968pts [
8969"80250,24000"
8970"70000,24000"
8971]
8972)
8973start &54
8974sat 32
8975eat 16
8976st 0
8977sf 1
8978si 0
8979tg (WTG
8980uid 1688,0
8981ps "ConnStartEndStrategy"
8982stg "STSignalDisplayStrategy"
8983f (Text
8984uid 1689,0
8985va (VaSet
8986)
8987xt "71000,23000,75000,24000"
8988st "ADC_CLK"
8989blo "71000,23800"
8990tm "WireNameMgr"
8991)
8992)
8993on &155
8994)
8995*283 (Wire
8996uid 2707,0
8997shape (OrthoPolyLine
8998uid 2708,0
8999va (VaSet
9000vasetType 3
9001)
9002xt "109750,81000,122000,81000"
9003pts [
9004"109750,81000"
9005"122000,81000"
9006]
9007)
9008start &55
9009sat 32
9010eat 16
9011st 0
9012sf 1
9013si 0
9014tg (WTG
9015uid 2711,0
9016ps "ConnStartEndStrategy"
9017stg "STSignalDisplayStrategy"
9018f (Text
9019uid 2712,0
9020va (VaSet
9021)
9022xt "111000,80000,121400,81000"
9023st "debug_data_ram_empty"
9024blo "111000,80800"
9025tm "WireNameMgr"
9026)
9027)
9028on &167
9029)
9030*284 (Wire
9031uid 2715,0
9032shape (OrthoPolyLine
9033uid 2716,0
9034va (VaSet
9035vasetType 3
9036)
9037xt "109750,82000,120000,82000"
9038pts [
9039"109750,82000"
9040"120000,82000"
9041]
9042)
9043start &56
9044sat 32
9045eat 16
9046st 0
9047sf 1
9048si 0
9049tg (WTG
9050uid 2719,0
9051ps "ConnStartEndStrategy"
9052stg "STSignalDisplayStrategy"
9053f (Text
9054uid 2720,0
9055va (VaSet
9056)
9057xt "111000,81000,118500,82000"
9058st "debug_data_valid"
9059blo "111000,81800"
9060tm "WireNameMgr"
9061)
9062)
9063on &168
9064)
9065*285 (Wire
9066uid 2723,0
9067shape (OrthoPolyLine
9068uid 2724,0
9069va (VaSet
9070vasetType 3
9071lineWidth 2
9072)
9073xt "109750,83000,119000,83000"
9074pts [
9075"109750,83000"
9076"119000,83000"
9077]
9078)
9079start &57
9080sat 32
9081eat 16
9082sty 1
9083st 0
9084sf 1
9085si 0
9086tg (WTG
9087uid 2727,0
9088ps "ConnStartEndStrategy"
9089stg "STSignalDisplayStrategy"
9090f (Text
9091uid 2728,0
9092va (VaSet
9093)
9094xt "111000,82000,117900,83000"
9095st "DG_state : (7:0)"
9096blo "111000,82800"
9097tm "WireNameMgr"
9098)
9099)
9100on &169
9101)
9102*286 (Wire
9103uid 2731,0
9104shape (OrthoPolyLine
9105uid 2732,0
9106va (VaSet
9107vasetType 3
9108)
9109xt "109750,84000,120000,84000"
9110pts [
9111"109750,84000"
9112"120000,84000"
9113]
9114)
9115start &59
9116sat 32
9117eat 16
9118st 0
9119sf 1
9120si 0
9121tg (WTG
9122uid 2735,0
9123ps "ConnStartEndStrategy"
9124stg "STSignalDisplayStrategy"
9125f (Text
9126uid 2736,0
9127va (VaSet
9128)
9129xt "111000,83000,119400,84000"
9130st "FTM_RS485_rx_en"
9131blo "111000,83800"
9132tm "WireNameMgr"
9133)
9134)
9135on &170
9136)
9137*287 (Wire
9138uid 2739,0
9139shape (OrthoPolyLine
9140uid 2740,0
9141va (VaSet
9142vasetType 3
9143)
9144xt "109750,85000,120000,85000"
9145pts [
9146"109750,85000"
9147"120000,85000"
9148]
9149)
9150start &60
9151sat 32
9152eat 16
9153st 0
9154sf 1
9155si 0
9156tg (WTG
9157uid 2743,0
9158ps "ConnStartEndStrategy"
9159stg "STSignalDisplayStrategy"
9160f (Text
9161uid 2744,0
9162va (VaSet
9163)
9164xt "111000,84000,119100,85000"
9165st "FTM_RS485_tx_d"
9166blo "111000,84800"
9167tm "WireNameMgr"
9168)
9169)
9170on &171
9171)
9172*288 (Wire
9173uid 2747,0
9174shape (OrthoPolyLine
9175uid 2748,0
9176va (VaSet
9177vasetType 3
9178)
9179xt "109750,86000,120000,86000"
9180pts [
9181"109750,86000"
9182"120000,86000"
9183]
9184)
9185start &61
9186sat 32
9187eat 16
9188st 0
9189sf 1
9190si 0
9191tg (WTG
9192uid 2751,0
9193ps "ConnStartEndStrategy"
9194stg "STSignalDisplayStrategy"
9195f (Text
9196uid 2752,0
9197va (VaSet
9198)
9199xt "111000,85000,119400,86000"
9200st "FTM_RS485_tx_en"
9201blo "111000,85800"
9202tm "WireNameMgr"
9203)
9204)
9205on &172
9206)
9207*289 (Wire
9208uid 2755,0
9209shape (OrthoPolyLine
9210uid 2756,0
9211va (VaSet
9212vasetType 3
9213lineWidth 2
9214)
9215xt "109750,87000,123000,87000"
9216pts [
9217"109750,87000"
9218"123000,87000"
9219]
9220)
9221start &62
9222sat 32
9223eat 16
9224sty 1
9225st 0
9226sf 1
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10158]
10159)
10160ss 0
10161es 0
10162sat 32
10163eat 32
10164st 0
10165sf 1
10166si 0
10167tg (WTG
10168ps "ConnStartEndStrategy"
10169stg "STSignalDisplayStrategy"
10170f (Text
10171va (VaSet
10172)
10173xt "0,0,1900,1000"
10174st "sig0"
10175blo "0,800"
10176tm "WireNameMgr"
10177)
10178)
10179)
10180defaultBus (Wire
10181shape (OrthoPolyLine
10182va (VaSet
10183vasetType 3
10184lineWidth 2
10185)
10186pts [
10187"0,0"
10188"0,0"
10189]
10190)
10191ss 0
10192es 0
10193sat 32
10194eat 32
10195sty 1
10196st 0
10197sf 1
10198si 0
10199tg (WTG
10200ps "ConnStartEndStrategy"
10201stg "STSignalDisplayStrategy"
10202f (Text
10203va (VaSet
10204)
10205xt "0,0,2400,1000"
10206st "dbus0"
10207blo "0,800"
10208tm "WireNameMgr"
10209)
10210)
10211)
10212defaultBundle (Bundle
10213shape (OrthoPolyLine
10214va (VaSet
10215vasetType 3
10216lineColor "32768,0,0"
10217lineWidth 2
10218)
10219pts [
10220"0,0"
10221"0,0"
10222]
10223)
10224ss 0
10225es 0
10226sat 32
10227eat 32
10228textGroup (BiTextGroup
10229ps "ConnStartEndStrategy"
10230stg "VerticalLayoutStrategy"
10231first (Text
10232va (VaSet
10233)
10234xt "0,0,3000,1000"
10235st "bundle0"
10236blo "0,800"
10237tm "BundleNameMgr"
10238)
10239second (MLText
10240va (VaSet
10241)
10242xt "0,1000,1000,2000"
10243st "()"
10244tm "BundleContentsMgr"
10245)
10246)
10247bundleNet &0
10248)
10249defaultPortMapFrame (PortMapFrame
10250ps "PortMapFrameStrategy"
10251shape (RectFrame
10252va (VaSet
10253vasetType 1
10254fg "65535,65535,65535"
10255lineColor "0,0,32768"
10256lineWidth 2
10257)
10258xt "0,0,10000,12000"
10259)
10260portMapText (BiTextGroup
10261ps "BottomRightOffsetStrategy"
10262stg "VerticalLayoutStrategy"
10263first (MLText
10264va (VaSet
10265)
10266)
10267second (MLText
10268va (VaSet
10269)
10270tm "PortMapTextMgr"
10271)
10272)
10273)
10274defaultGenFrame (Frame
10275shape (RectFrame
10276va (VaSet
10277vasetType 1
10278fg "65535,65535,65535"
10279lineColor "26368,26368,26368"
10280lineStyle 2
10281lineWidth 2
10282)
10283xt "0,0,20000,20000"
10284)
10285title (TextAssociate
10286ps "TopLeftStrategy"
10287text (MLText
10288va (VaSet
10289)
10290xt "0,-1100,12600,-100"
10291st "g0: FOR i IN 0 TO n GENERATE"
10292tm "FrameTitleTextMgr"
10293)
10294)
10295seqNum (FrameSequenceNumber
10296ps "TopLeftStrategy"
10297shape (Rectangle
10298va (VaSet
10299vasetType 1
10300fg "65535,65535,65535"
10301)
10302xt "50,50,1250,1450"
10303)
10304num (Text
10305va (VaSet
10306)
10307xt "250,250,1050,1250"
10308st "1"
10309blo "250,1050"
10310tm "FrameSeqNumMgr"
10311)
10312)
10313decls (MlTextGroup
10314ps "BottomRightOffsetStrategy"
10315stg "VerticalLayoutStrategy"
10316textVec [
10317*321 (Text
10318va (VaSet
10319font "Arial,8,1"
10320)
10321xt "14100,20000,22000,21000"
10322st "Frame Declarations"
10323blo "14100,20800"
10324)
10325*322 (MLText
10326va (VaSet
10327)
10328xt "14100,21000,14100,21000"
10329tm "BdFrameDeclTextMgr"
10330)
10331]
10332)
10333)
10334defaultBlockFrame (Frame
10335shape (RectFrame
10336va (VaSet
10337vasetType 1
10338fg "65535,65535,65535"
10339lineColor "26368,26368,26368"
10340lineStyle 1
10341lineWidth 2
10342)
10343xt "0,0,20000,20000"
10344)
10345title (TextAssociate
10346ps "TopLeftStrategy"
10347text (MLText
10348va (VaSet
10349)
10350xt "0,-1100,7400,-100"
10351st "b0: BLOCK (guard)"
10352tm "FrameTitleTextMgr"
10353)
10354)
10355seqNum (FrameSequenceNumber
10356ps "TopLeftStrategy"
10357shape (Rectangle
10358va (VaSet
10359vasetType 1
10360fg "65535,65535,65535"
10361)
10362xt "50,50,1250,1450"
10363)
10364num (Text
10365va (VaSet
10366)
10367xt "250,250,1050,1250"
10368st "1"
10369blo "250,1050"
10370tm "FrameSeqNumMgr"
10371)
10372)
10373decls (MlTextGroup
10374ps "BottomRightOffsetStrategy"
10375stg "VerticalLayoutStrategy"
10376textVec [
10377*323 (Text
10378va (VaSet
10379font "Arial,8,1"
10380)
10381xt "14100,20000,22000,21000"
10382st "Frame Declarations"
10383blo "14100,20800"
10384)
10385*324 (MLText
10386va (VaSet
10387)
10388xt "14100,21000,14100,21000"
10389tm "BdFrameDeclTextMgr"
10390)
10391]
10392)
10393style 3
10394)
10395defaultSaCptPort (CptPort
10396ps "OnEdgeStrategy"
10397shape (Triangle
10398ro 90
10399va (VaSet
10400vasetType 1
10401fg "0,65535,0"
10402)
10403xt "0,0,750,750"
10404)
10405tg (CPTG
10406ps "CptPortTextPlaceStrategy"
10407stg "VerticalLayoutStrategy"
10408f (Text
10409va (VaSet
10410)
10411xt "0,750,1800,1750"
10412st "Port"
10413blo "0,1550"
10414)
10415)
10416thePort (LogicalPort
10417decl (Decl
10418n "Port"
10419t ""
10420o 0
10421)
10422)
10423)
10424defaultSaCptPortBuffer (CptPort
10425ps "OnEdgeStrategy"
10426shape (Diamond
10427va (VaSet
10428vasetType 1
10429fg "65535,65535,65535"
10430)
10431xt "0,0,750,750"
10432)
10433tg (CPTG
10434ps "CptPortTextPlaceStrategy"
10435stg "VerticalLayoutStrategy"
10436f (Text
10437va (VaSet
10438)
10439xt "0,750,1800,1750"
10440st "Port"
10441blo "0,1550"
10442)
10443)
10444thePort (LogicalPort
10445m 3
10446decl (Decl
10447n "Port"
10448t ""
10449o 0
10450)
10451)
10452)
10453defaultDeclText (MLText
10454va (VaSet
10455font "Courier New,8,0"
10456)
10457)
10458archDeclarativeBlock (BdArchDeclBlock
10459uid 1,0
10460stg "BdArchDeclBlockLS"
10461declLabel (Text
10462uid 2,0
10463va (VaSet
10464font "Arial,8,1"
10465)
10466xt "-92000,21600,-86600,22600"
10467st "Declarations"
10468blo "-92000,22400"
10469)
10470portLabel (Text
10471uid 3,0
10472va (VaSet
10473font "Arial,8,1"
10474)
10475xt "-92000,22600,-89300,23600"
10476st "Ports:"
10477blo "-92000,23400"
10478)
10479preUserLabel (Text
10480uid 4,0
10481va (VaSet
10482isHidden 1
10483font "Arial,8,1"
10484)
10485xt "-92000,21600,-88200,22600"
10486st "Pre User:"
10487blo "-92000,22400"
10488)
10489preUserText (MLText
10490uid 5,0
10491va (VaSet
10492isHidden 1
10493font "Courier New,8,0"
10494)
10495xt "-92000,21600,-92000,21600"
10496tm "BdDeclarativeTextMgr"
10497)
10498diagSignalLabel (Text
10499uid 6,0
10500va (VaSet
10501font "Arial,8,1"
10502)
10503xt "-92000,23600,-84900,24600"
10504st "Diagram Signals:"
10505blo "-92000,24400"
10506)
10507postUserLabel (Text
10508uid 7,0
10509va (VaSet
10510isHidden 1
10511font "Arial,8,1"
10512)
10513xt "-92000,21600,-87300,22600"
10514st "Post User:"
10515blo "-92000,22400"
10516)
10517postUserText (MLText
10518uid 8,0
10519va (VaSet
10520isHidden 1
10521font "Courier New,8,0"
10522)
10523xt "-92000,21600,-92000,21600"
10524tm "BdDeclarativeTextMgr"
10525)
10526)
10527commonDM (CommonDM
10528ldm (LogicalDM
10529suid 64,0
10530usingSuid 1
10531emptyRow *325 (LEmptyRow
10532)
10533uid 54,0
10534optionalChildren [
10535*326 (RefLabelRowHdr
10536)
10537*327 (TitleRowHdr
10538)
10539*328 (FilterRowHdr
10540)
10541*329 (RefLabelColHdr
10542tm "RefLabelColHdrMgr"
10543)
10544*330 (RowExpandColHdr
10545tm "RowExpandColHdrMgr"
10546)
10547*331 (GroupColHdr
10548tm "GroupColHdrMgr"
10549)
10550*332 (NameColHdr
10551tm "BlockDiagramNameColHdrMgr"
10552)
10553*333 (ModeColHdr
10554tm "BlockDiagramModeColHdrMgr"
10555)
10556*334 (TypeColHdr
10557tm "BlockDiagramTypeColHdrMgr"
10558)
10559*335 (BoundsColHdr
10560tm "BlockDiagramBoundsColHdrMgr"
10561)
10562*336 (InitColHdr
10563tm "BlockDiagramInitColHdrMgr"
10564)
10565*337 (EolColHdr
10566tm "BlockDiagramEolColHdrMgr"
10567)
10568*338 (LeafLogPort
10569port (LogicalPort
10570m 4
10571decl (Decl
10572n "clk"
10573t "STD_LOGIC"
10574preAdd 0
10575posAdd 0
10576o 1
10577suid 1,0
10578)
10579)
10580uid 340,0
10581)
10582*339 (LeafLogPort
10583port (LogicalPort
10584m 4
10585decl (Decl
10586n "wiz_addr"
10587t "std_logic_vector"
10588b "(9 DOWNTO 0)"
10589o 2
10590suid 2,0
10591)
10592)
10593uid 342,0
10594)
10595*340 (LeafLogPort
10596port (LogicalPort
10597m 4
10598decl (Decl
10599n "wiz_data"
10600t "std_logic_vector"
10601b "(15 DOWNTO 0)"
10602o 3
10603suid 3,0
10604)
10605)
10606uid 344,0
10607)
10608*341 (LeafLogPort
10609port (LogicalPort
10610m 4
10611decl (Decl
10612n "wiz_rd"
10613t "std_logic"
10614o 4
10615suid 4,0
10616i "'1'"
10617)
10618)
10619uid 346,0
10620)
10621*342 (LeafLogPort
10622port (LogicalPort
10623m 4
10624decl (Decl
10625n "wiz_wr"
10626t "std_logic"
10627o 5
10628suid 5,0
10629i "'1'"
10630)
10631)
10632uid 348,0
10633)
10634*343 (LeafLogPort
10635port (LogicalPort
10636m 4
10637decl (Decl
10638n "sensor_cs"
10639t "std_logic_vector"
10640b "(3 DOWNTO 0)"
10641o 6
10642suid 6,0
10643)
10644)
10645uid 404,0
10646)
10647*344 (LeafLogPort
10648port (LogicalPort
10649m 4
10650decl (Decl
10651n "sclk"
10652t "std_logic"
10653o 7
10654suid 7,0
10655)
10656)
10657uid 406,0
10658)
10659*345 (LeafLogPort
10660port (LogicalPort
10661m 4
10662decl (Decl
10663n "sio"
10664t "std_logic"
10665preAdd 0
10666posAdd 0
10667o 8
10668suid 8,0
10669)
10670)
10671uid 408,0
10672)
10673*346 (LeafLogPort
10674port (LogicalPort
10675m 4
10676decl (Decl
10677n "trigger"
10678t "std_logic"
10679preAdd 0
10680posAdd 0
10681o 9
10682suid 9,0
10683)
10684)
10685uid 456,0
10686)
10687*347 (LeafLogPort
10688port (LogicalPort
10689m 4
10690decl (Decl
10691n "board_id"
10692t "std_logic_vector"
10693b "(3 downto 0)"
10694preAdd 0
10695posAdd 0
10696o 10
10697suid 10,0
10698)
10699)
10700uid 458,0
10701)
10702*348 (LeafLogPort
10703port (LogicalPort
10704m 4
10705decl (Decl
10706n "crate_id"
10707t "std_logic_vector"
10708b "(1 downto 0)"
10709o 11
10710suid 11,0
10711)
10712)
10713uid 460,0
10714)
10715*349 (LeafLogPort
10716port (LogicalPort
10717m 4
10718decl (Decl
10719n "adc_otr_array"
10720t "std_logic_vector"
10721b "(3 DOWNTO 0)"
10722o 12
10723suid 12,0
10724)
10725)
10726uid 584,0
10727)
10728*350 (LeafLogPort
10729port (LogicalPort
10730m 4
10731decl (Decl
10732n "adc_data_array"
10733t "adc_data_array_type"
10734o 13
10735suid 13,0
10736)
10737)
10738uid 586,0
10739)
10740*351 (LeafLogPort
10741port (LogicalPort
10742m 4
10743decl (Decl
10744n "adc_oeb"
10745t "std_logic"
10746preAdd 0
10747posAdd 0
10748o 14
10749suid 14,0
10750)
10751)
10752uid 588,0
10753)
10754*352 (LeafLogPort
10755port (LogicalPort
10756m 4
10757decl (Decl
10758n "adc_otr"
10759t "STD_LOGIC"
10760preAdd 0
10761posAdd 0
10762o 16
10763suid 16,0
10764)
10765)
10766uid 590,0
10767)
10768*353 (LeafLogPort
10769port (LogicalPort
10770m 4
10771decl (Decl
10772n "adc_data"
10773t "std_logic_vector"
10774b "(11 DOWNTO 0)"
10775preAdd 0
10776posAdd 0
10777o 17
10778suid 17,0
10779)
10780)
10781uid 592,0
10782)
10783*354 (LeafLogPort
10784port (LogicalPort
10785m 4
10786decl (Decl
10787n "wiz_reset"
10788t "std_logic"
10789o 21
10790suid 23,0
10791i "'1'"
10792)
10793)
10794uid 903,0
10795)
10796*355 (LeafLogPort
10797port (LogicalPort
10798m 4
10799decl (Decl
10800n "led"
10801t "std_logic_vector"
10802b "(7 DOWNTO 0)"
10803posAdd 0
10804o 22
10805suid 24,0
10806i "(OTHERS => '0')"
10807)
10808)
10809uid 905,0
10810)
10811*356 (LeafLogPort
10812port (LogicalPort
10813m 4
10814decl (Decl
10815n "wiz_cs"
10816t "std_logic"
10817o 23
10818suid 25,0
10819i "'1'"
10820)
10821)
10822uid 907,0
10823)
10824*357 (LeafLogPort
10825port (LogicalPort
10826m 4
10827decl (Decl
10828n "wiz_int"
10829t "std_logic"
10830o 24
10831suid 26,0
10832)
10833)
10834uid 909,0
10835)
10836*358 (LeafLogPort
10837port (LogicalPort
10838m 4
10839decl (Decl
10840n "dac_cs"
10841t "std_logic"
10842o 25
10843suid 27,0
10844)
10845)
10846uid 911,0
10847)
10848*359 (LeafLogPort
10849port (LogicalPort
10850m 4
10851decl (Decl
10852n "mosi"
10853t "std_logic"
10854o 26
10855suid 28,0
10856i "'0'"
10857)
10858)
10859uid 913,0
10860)
10861*360 (LeafLogPort
10862port (LogicalPort
10863m 4
10864decl (Decl
10865n "denable"
10866t "std_logic"
10867eolc "-- default domino wave off"
10868posAdd 0
10869o 27
10870suid 29,0
10871i "'0'"
10872)
10873)
10874uid 915,0
10875)
10876*361 (LeafLogPort
10877port (LogicalPort
10878m 4
10879decl (Decl
10880n "CLK_25_PS"
10881t "std_logic"
10882o 28
10883suid 30,0
10884)
10885)
10886uid 917,0
10887)
10888*362 (LeafLogPort
10889port (LogicalPort
10890m 4
10891decl (Decl
10892n "CLK_50"
10893t "std_logic"
10894o 29
10895suid 31,0
10896)
10897)
10898uid 919,0
10899)
10900*363 (LeafLogPort
10901port (LogicalPort
10902m 4
10903decl (Decl
10904n "drs_channel_id"
10905t "std_logic_vector"
10906b "(3 downto 0)"
10907o 30
10908suid 32,0
10909i "(others => '0')"
10910)
10911)
10912uid 921,0
10913)
10914*364 (LeafLogPort
10915port (LogicalPort
10916m 4
10917decl (Decl
10918n "drs_dwrite"
10919t "std_logic"
10920o 31
10921suid 33,0
10922i "'1'"
10923)
10924)
10925uid 923,0
10926)
10927*365 (LeafLogPort
10928port (LogicalPort
10929m 4
10930decl (Decl
10931n "RSRLOAD"
10932t "std_logic"
10933o 32
10934suid 34,0
10935i "'0'"
10936)
10937)
10938uid 925,0
10939)
10940*366 (LeafLogPort
10941port (LogicalPort
10942m 4
10943decl (Decl
10944n "SRCLK"
10945t "std_logic"
10946o 33
10947suid 35,0
10948i "'0'"
10949)
10950)
10951uid 927,0
10952)
10953*367 (LeafLogPort
10954port (LogicalPort
10955m 4
10956decl (Decl
10957n "SROUT_in_0"
10958t "std_logic"
10959o 30
10960suid 36,0
10961)
10962)
10963uid 929,0
10964)
10965*368 (LeafLogPort
10966port (LogicalPort
10967m 4
10968decl (Decl
10969n "SROUT_in_1"
10970t "std_logic"
10971o 31
10972suid 37,0
10973)
10974)
10975uid 931,0
10976)
10977*369 (LeafLogPort
10978port (LogicalPort
10979m 4
10980decl (Decl
10981n "SROUT_in_2"
10982t "std_logic"
10983o 32
10984suid 38,0
10985)
10986)
10987uid 933,0
10988)
10989*370 (LeafLogPort
10990port (LogicalPort
10991m 4
10992decl (Decl
10993n "SROUT_in_3"
10994t "std_logic"
10995o 33
10996suid 39,0
10997)
10998)
10999uid 935,0
11000)
11001*371 (LeafLogPort
11002port (LogicalPort
11003m 4
11004decl (Decl
11005n "SRIN_out"
11006t "std_logic"
11007o 34
11008suid 40,0
11009i "'0'"
11010)
11011)
11012uid 1541,0
11013)
11014*372 (LeafLogPort
11015port (LogicalPort
11016m 4
11017decl (Decl
11018n "amber"
11019t "std_logic"
11020o 35
11021suid 41,0
11022)
11023)
11024uid 1543,0
11025)
11026*373 (LeafLogPort
11027port (LogicalPort
11028m 4
11029decl (Decl
11030n "red"
11031t "std_logic"
11032o 36
11033suid 42,0
11034)
11035)
11036uid 1545,0
11037)
11038*374 (LeafLogPort
11039port (LogicalPort
11040m 4
11041decl (Decl
11042n "green"
11043t "std_logic"
11044o 37
11045suid 43,0
11046)
11047)
11048uid 1547,0
11049)
11050*375 (LeafLogPort
11051port (LogicalPort
11052m 4
11053decl (Decl
11054n "counter_result"
11055t "std_logic_vector"
11056b "(11 DOWNTO 0)"
11057o 38
11058suid 44,0
11059)
11060)
11061uid 1549,0
11062)
11063*376 (LeafLogPort
11064port (LogicalPort
11065m 4
11066decl (Decl
11067n "alarm_refclk_too_low"
11068t "std_logic"
11069posAdd 0
11070o 39
11071suid 45,0
11072)
11073)
11074uid 1551,0
11075)
11076*377 (LeafLogPort
11077port (LogicalPort
11078m 4
11079decl (Decl
11080n "alarm_refclk_too_high"
11081t "std_logic"
11082o 40
11083suid 46,0
11084)
11085)
11086uid 1553,0
11087)
11088*378 (LeafLogPort
11089port (LogicalPort
11090m 4
11091decl (Decl
11092n "D_T_in"
11093t "std_logic_vector"
11094b "(1 DOWNTO 0)"
11095o 41
11096suid 47,0
11097)
11098)
11099uid 1555,0
11100)
11101*379 (LeafLogPort
11102port (LogicalPort
11103m 4
11104decl (Decl
11105n "plllock_in"
11106t "std_logic_vector"
11107b "(3 DOWNTO 0)"
11108eolc "-- high level, if dominowave is running and DRS PLL locked"
11109o 43
11110suid 49,0
11111)
11112)
11113uid 1575,0
11114)
11115*380 (LeafLogPort
11116port (LogicalPort
11117lang 2
11118m 4
11119decl (Decl
11120n "ADC_CLK"
11121t "std_logic"
11122o 44
11123suid 50,0
11124)
11125)
11126uid 1690,0
11127)
11128*381 (LeafLogPort
11129port (LogicalPort
11130m 4
11131decl (Decl
11132n "REF_CLK"
11133t "STD_LOGIC"
11134o 42
11135suid 51,0
11136i "'0'"
11137)
11138)
11139uid 2003,0
11140)
11141*382 (LeafLogPort
11142port (LogicalPort
11143m 4
11144decl (Decl
11145n "debug_data_ram_empty"
11146t "std_logic"
11147o 45
11148suid 53,0
11149)
11150)
11151uid 2785,0
11152)
11153*383 (LeafLogPort
11154port (LogicalPort
11155m 4
11156decl (Decl
11157n "debug_data_valid"
11158t "std_logic"
11159o 46
11160suid 54,0
11161)
11162)
11163uid 2787,0
11164)
11165*384 (LeafLogPort
11166port (LogicalPort
11167m 4
11168decl (Decl
11169n "DG_state"
11170t "std_logic_vector"
11171b "(7 downto 0)"
11172prec "-- for debugging"
11173preAdd 0
11174o 47
11175suid 55,0
11176)
11177)
11178uid 2789,0
11179)
11180*385 (LeafLogPort
11181port (LogicalPort
11182m 4
11183decl (Decl
11184n "FTM_RS485_rx_en"
11185t "std_logic"
11186o 48
11187suid 56,0
11188)
11189)
11190uid 2791,0
11191)
11192*386 (LeafLogPort
11193port (LogicalPort
11194m 4
11195decl (Decl
11196n "FTM_RS485_tx_d"
11197t "std_logic"
11198o 49
11199suid 57,0
11200)
11201)
11202uid 2793,0
11203)
11204*387 (LeafLogPort
11205port (LogicalPort
11206m 4
11207decl (Decl
11208n "FTM_RS485_tx_en"
11209t "std_logic"
11210o 50
11211suid 58,0
11212)
11213)
11214uid 2795,0
11215)
11216*388 (LeafLogPort
11217port (LogicalPort
11218lang 2
11219m 4
11220decl (Decl
11221n "mem_manager_state"
11222t "std_logic_vector"
11223b "(3 DOWNTO 0)"
11224eolc "-- state is encoded here ... useful for debugging."
11225posAdd 0
11226o 51
11227suid 59,0
11228)
11229)
11230uid 2797,0
11231)
11232*389 (LeafLogPort
11233port (LogicalPort
11234m 4
11235decl (Decl
11236n "trigger_veto"
11237t "std_logic"
11238o 52
11239suid 60,0
11240i "'1'"
11241)
11242)
11243uid 2799,0
11244)
11245*390 (LeafLogPort
11246port (LogicalPort
11247m 4
11248decl (Decl
11249n "w5300_state"
11250t "std_logic_vector"
11251b "(7 DOWNTO 0)"
11252eolc "-- state is encoded here ... useful for debugging."
11253posAdd 0
11254o 53
11255suid 61,0
11256)
11257)
11258uid 2801,0
11259)
11260*391 (LeafLogPort
11261port (LogicalPort
11262m 4
11263decl (Decl
11264n "FTM_RS485_rx_d"
11265t "std_logic"
11266o 54
11267suid 62,0
11268)
11269)
11270uid 2803,0
11271)
11272*392 (LeafLogPort
11273port (LogicalPort
11274m 4
11275decl (Decl
11276n "socket_tx_free_out"
11277t "std_logic_vector"
11278b "(16 DOWNTO 0)"
11279eolc "-- 17bit value .. that's true"
11280posAdd 0
11281o 55
11282suid 64,0
11283)
11284)
11285uid 2950,0
11286)
11287]
11288)
11289pdm (PhysicalDM
11290displayShortBounds 1
11291editShortBounds 1
11292uid 67,0
11293optionalChildren [
11294*393 (Sheet
11295sheetRow (SheetRow
11296headerVa (MVa
11297cellColor "49152,49152,49152"
11298fontColor "0,0,0"
11299font "Tahoma,10,0"
11300)
11301cellVa (MVa
11302cellColor "65535,65535,65535"
11303fontColor "0,0,0"
11304font "Tahoma,10,0"
11305)
11306groupVa (MVa
11307cellColor "39936,56832,65280"
11308fontColor "0,0,0"
11309font "Tahoma,10,0"
11310)
11311emptyMRCItem *394 (MRCItem
11312litem &325
11313pos 55
11314dimension 20
11315)
11316uid 69,0
11317optionalChildren [
11318*395 (MRCItem
11319litem &326
11320pos 0
11321dimension 20
11322uid 70,0
11323)
11324*396 (MRCItem
11325litem &327
11326pos 1
11327dimension 23
11328uid 71,0
11329)
11330*397 (MRCItem
11331litem &328
11332pos 2
11333hidden 1
11334dimension 20
11335uid 72,0
11336)
11337*398 (MRCItem
11338litem &338
11339pos 0
11340dimension 20
11341uid 341,0
11342)
11343*399 (MRCItem
11344litem &339
11345pos 1
11346dimension 20
11347uid 343,0
11348)
11349*400 (MRCItem
11350litem &340
11351pos 2
11352dimension 20
11353uid 345,0
11354)
11355*401 (MRCItem
11356litem &341
11357pos 3
11358dimension 20
11359uid 347,0
11360)
11361*402 (MRCItem
11362litem &342
11363pos 4
11364dimension 20
11365uid 349,0
11366)
11367*403 (MRCItem
11368litem &343
11369pos 5
11370dimension 20
11371uid 405,0
11372)
11373*404 (MRCItem
11374litem &344
11375pos 6
11376dimension 20
11377uid 407,0
11378)
11379*405 (MRCItem
11380litem &345
11381pos 7
11382dimension 20
11383uid 409,0
11384)
11385*406 (MRCItem
11386litem &346
11387pos 8
11388dimension 20
11389uid 457,0
11390)
11391*407 (MRCItem
11392litem &347
11393pos 9
11394dimension 20
11395uid 459,0
11396)
11397*408 (MRCItem
11398litem &348
11399pos 10
11400dimension 20
11401uid 461,0
11402)
11403*409 (MRCItem
11404litem &349
11405pos 11
11406dimension 20
11407uid 585,0
11408)
11409*410 (MRCItem
11410litem &350
11411pos 12
11412dimension 20
11413uid 587,0
11414)
11415*411 (MRCItem
11416litem &351
11417pos 13
11418dimension 20
11419uid 589,0
11420)
11421*412 (MRCItem
11422litem &352
11423pos 14
11424dimension 20
11425uid 591,0
11426)
11427*413 (MRCItem
11428litem &353
11429pos 15
11430dimension 20
11431uid 593,0
11432)
11433*414 (MRCItem
11434litem &354
11435pos 16
11436dimension 20
11437uid 904,0
11438)
11439*415 (MRCItem
11440litem &355
11441pos 17
11442dimension 20
11443uid 906,0
11444)
11445*416 (MRCItem
11446litem &356
11447pos 18
11448dimension 20
11449uid 908,0
11450)
11451*417 (MRCItem
11452litem &357
11453pos 19
11454dimension 20
11455uid 910,0
11456)
11457*418 (MRCItem
11458litem &358
11459pos 20
11460dimension 20
11461uid 912,0
11462)
11463*419 (MRCItem
11464litem &359
11465pos 21
11466dimension 20
11467uid 914,0
11468)
11469*420 (MRCItem
11470litem &360
11471pos 22
11472dimension 20
11473uid 916,0
11474)
11475*421 (MRCItem
11476litem &361
11477pos 23
11478dimension 20
11479uid 918,0
11480)
11481*422 (MRCItem
11482litem &362
11483pos 24
11484dimension 20
11485uid 920,0
11486)
11487*423 (MRCItem
11488litem &363
11489pos 25
11490dimension 20
11491uid 922,0
11492)
11493*424 (MRCItem
11494litem &364
11495pos 26
11496dimension 20
11497uid 924,0
11498)
11499*425 (MRCItem
11500litem &365
11501pos 27
11502dimension 20
11503uid 926,0
11504)
11505*426 (MRCItem
11506litem &366
11507pos 28
11508dimension 20
11509uid 928,0
11510)
11511*427 (MRCItem
11512litem &367
11513pos 29
11514dimension 20
11515uid 930,0
11516)
11517*428 (MRCItem
11518litem &368
11519pos 30
11520dimension 20
11521uid 932,0
11522)
11523*429 (MRCItem
11524litem &369
11525pos 31
11526dimension 20
11527uid 934,0
11528)
11529*430 (MRCItem
11530litem &370
11531pos 32
11532dimension 20
11533uid 936,0
11534)
11535*431 (MRCItem
11536litem &371
11537pos 33
11538dimension 20
11539uid 1542,0
11540)
11541*432 (MRCItem
11542litem &372
11543pos 34
11544dimension 20
11545uid 1544,0
11546)
11547*433 (MRCItem
11548litem &373
11549pos 35
11550dimension 20
11551uid 1546,0
11552)
11553*434 (MRCItem
11554litem &374
11555pos 36
11556dimension 20
11557uid 1548,0
11558)
11559*435 (MRCItem
11560litem &375
11561pos 37
11562dimension 20
11563uid 1550,0
11564)
11565*436 (MRCItem
11566litem &376
11567pos 38
11568dimension 20
11569uid 1552,0
11570)
11571*437 (MRCItem
11572litem &377
11573pos 39
11574dimension 20
11575uid 1554,0
11576)
11577*438 (MRCItem
11578litem &378
11579pos 40
11580dimension 20
11581uid 1556,0
11582)
11583*439 (MRCItem
11584litem &379
11585pos 41
11586dimension 20
11587uid 1576,0
11588)
11589*440 (MRCItem
11590litem &380
11591pos 42
11592dimension 20
11593uid 1691,0
11594)
11595*441 (MRCItem
11596litem &381
11597pos 43
11598dimension 20
11599uid 2004,0
11600)
11601*442 (MRCItem
11602litem &382
11603pos 44
11604dimension 20
11605uid 2786,0
11606)
11607*443 (MRCItem
11608litem &383
11609pos 45
11610dimension 20
11611uid 2788,0
11612)
11613*444 (MRCItem
11614litem &384
11615pos 46
11616dimension 20
11617uid 2790,0
11618)
11619*445 (MRCItem
11620litem &385
11621pos 47
11622dimension 20
11623uid 2792,0
11624)
11625*446 (MRCItem
11626litem &386
11627pos 48
11628dimension 20
11629uid 2794,0
11630)
11631*447 (MRCItem
11632litem &387
11633pos 49
11634dimension 20
11635uid 2796,0
11636)
11637*448 (MRCItem
11638litem &388
11639pos 50
11640dimension 20
11641uid 2798,0
11642)
11643*449 (MRCItem
11644litem &389
11645pos 51
11646dimension 20
11647uid 2800,0
11648)
11649*450 (MRCItem
11650litem &390
11651pos 52
11652dimension 20
11653uid 2802,0
11654)
11655*451 (MRCItem
11656litem &391
11657pos 53
11658dimension 20
11659uid 2804,0
11660)
11661*452 (MRCItem
11662litem &392
11663pos 54
11664dimension 20
11665uid 2951,0
11666)
11667]
11668)
11669sheetCol (SheetCol
11670propVa (MVa
11671cellColor "0,49152,49152"
11672fontColor "0,0,0"
11673font "Tahoma,10,0"
11674textAngle 90
11675)
11676uid 73,0
11677optionalChildren [
11678*453 (MRCItem
11679litem &329
11680pos 0
11681dimension 20
11682uid 74,0
11683)
11684*454 (MRCItem
11685litem &331
11686pos 1
11687dimension 50
11688uid 75,0
11689)
11690*455 (MRCItem
11691litem &332
11692pos 2
11693dimension 100
11694uid 76,0
11695)
11696*456 (MRCItem
11697litem &333
11698pos 3
11699dimension 50
11700uid 77,0
11701)
11702*457 (MRCItem
11703litem &334
11704pos 4
11705dimension 100
11706uid 78,0
11707)
11708*458 (MRCItem
11709litem &335
11710pos 5
11711dimension 100
11712uid 79,0
11713)
11714*459 (MRCItem
11715litem &336
11716pos 6
11717dimension 50
11718uid 80,0
11719)
11720*460 (MRCItem
11721litem &337
11722pos 7
11723dimension 80
11724uid 81,0
11725)
11726]
11727)
11728fixedCol 4
11729fixedRow 2
11730name "Ports"
11731uid 68,0
11732vaOverrides [
11733]
11734)
11735]
11736)
11737uid 53,0
11738)
11739genericsCommonDM (CommonDM
11740ldm (LogicalDM
11741emptyRow *461 (LEmptyRow
11742)
11743uid 83,0
11744optionalChildren [
11745*462 (RefLabelRowHdr
11746)
11747*463 (TitleRowHdr
11748)
11749*464 (FilterRowHdr
11750)
11751*465 (RefLabelColHdr
11752tm "RefLabelColHdrMgr"
11753)
11754*466 (RowExpandColHdr
11755tm "RowExpandColHdrMgr"
11756)
11757*467 (GroupColHdr
11758tm "GroupColHdrMgr"
11759)
11760*468 (NameColHdr
11761tm "GenericNameColHdrMgr"
11762)
11763*469 (TypeColHdr
11764tm "GenericTypeColHdrMgr"
11765)
11766*470 (InitColHdr
11767tm "GenericValueColHdrMgr"
11768)
11769*471 (PragmaColHdr
11770tm "GenericPragmaColHdrMgr"
11771)
11772*472 (EolColHdr
11773tm "GenericEolColHdrMgr"
11774)
11775]
11776)
11777pdm (PhysicalDM
11778displayShortBounds 1
11779editShortBounds 1
11780uid 95,0
11781optionalChildren [
11782*473 (Sheet
11783sheetRow (SheetRow
11784headerVa (MVa
11785cellColor "49152,49152,49152"
11786fontColor "0,0,0"
11787font "Tahoma,10,0"
11788)
11789cellVa (MVa
11790cellColor "65535,65535,65535"
11791fontColor "0,0,0"
11792font "Tahoma,10,0"
11793)
11794groupVa (MVa
11795cellColor "39936,56832,65280"
11796fontColor "0,0,0"
11797font "Tahoma,10,0"
11798)
11799emptyMRCItem *474 (MRCItem
11800litem &461
11801pos 0
11802dimension 20
11803)
11804uid 97,0
11805optionalChildren [
11806*475 (MRCItem
11807litem &462
11808pos 0
11809dimension 20
11810uid 98,0
11811)
11812*476 (MRCItem
11813litem &463
11814pos 1
11815dimension 23
11816uid 99,0
11817)
11818*477 (MRCItem
11819litem &464
11820pos 2
11821hidden 1
11822dimension 20
11823uid 100,0
11824)
11825]
11826)
11827sheetCol (SheetCol
11828propVa (MVa
11829cellColor "0,49152,49152"
11830fontColor "0,0,0"
11831font "Tahoma,10,0"
11832textAngle 90
11833)
11834uid 101,0
11835optionalChildren [
11836*478 (MRCItem
11837litem &465
11838pos 0
11839dimension 20
11840uid 102,0
11841)
11842*479 (MRCItem
11843litem &467
11844pos 1
11845dimension 50
11846uid 103,0
11847)
11848*480 (MRCItem
11849litem &468
11850pos 2
11851dimension 100
11852uid 104,0
11853)
11854*481 (MRCItem
11855litem &469
11856pos 3
11857dimension 100
11858uid 105,0
11859)
11860*482 (MRCItem
11861litem &470
11862pos 4
11863dimension 50
11864uid 106,0
11865)
11866*483 (MRCItem
11867litem &471
11868pos 5
11869dimension 50
11870uid 107,0
11871)
11872*484 (MRCItem
11873litem &472
11874pos 6
11875dimension 80
11876uid 108,0
11877)
11878]
11879)
11880fixedCol 3
11881fixedRow 2
11882name "Ports"
11883uid 96,0
11884vaOverrides [
11885]
11886)
11887]
11888)
11889uid 82,0
11890type 1
11891)
11892activeModelName "BlockDiag"
11893)
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