source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd @ 10225

Last change on this file since 10225 was 10225, checked in by neise, 9 years ago
new data format implemented. setting of DAC during run is possible.
File size: 110.3 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8)
9(DmPackageRef
10library "ieee"
11unitName "std_logic_arith"
12)
13(DmPackageRef
14library "ieee"
15unitName "std_logic_unsigned"
16)
17(DmPackageRef
18library "FACT_FAD_lib"
19unitName "fad_definitions"
20)
21(DmPackageRef
22library "ieee"
23unitName "std_logic_textio"
24)
25(DmPackageRef
26library "std"
27unitName "textio"
28)
29]
30instances [
31(Instance
32name "I_mainTB_FPGA"
33duLibraryName "FACT_FAD_lib"
34duName "FAD_main"
35elements [
36(GiElement
37name "RAMADDRWIDTH64b"
38type "integer"
39value "15"
40)
41]
42mwi 0
43uid 233,0
44)
45(Instance
46name "I_mainTB_clock"
47duLibraryName "FACT_FAD_TB_lib"
48duName "clock_generator"
49elements [
50(GiElement
51name "clock_period"
52type "time"
53value "20 ns"
54)
55(GiElement
56name "reset_time"
57type "time"
58value "50 ns"
59)
60]
61mwi 0
62uid 274,0
63)
64(Instance
65name "I_mainTB_max6662"
66duLibraryName "FACT_FAD_TB_lib"
67duName "max6662_emulator"
68elements [
69(GiElement
70name "DRS_TEMPERATURE"
71type "integer"
72value "51"
73)
74]
75mwi 0
76uid 362,0
77)
78(Instance
79name "I_mainTB_trigger"
80duLibraryName "FACT_FAD_TB_lib"
81duName "trigger_generator"
82elements [
83(GiElement
84name "TRIGGER_RATE"
85type "time"
86value "1 ms"
87)
88(GiElement
89name "PULSE_WIDTH"
90type "time"
91value "20 ns"
92)
93]
94mwi 0
95uid 414,0
96)
97(Instance
98name "I_mainTB_adc"
99duLibraryName "FACT_FAD_TB_lib"
100duName "adc_emulator"
101elements [
102(GiElement
103name "INPUT_FILE"
104type "string"
105value "\"../memory_files/analog_input_ch0.txt\""
106)
107]
108mwi 0
109uid 508,0
110)
111(Instance
112name "I_mainTB_clock1"
113duLibraryName "FACT_FAD_TB_lib"
114duName "clock_generator"
115elements [
116(GiElement
117name "clock_period"
118type "time"
119value "1 us"
120)
121(GiElement
122name "reset_time"
123type "time"
124value "1 us"
125)
126]
127mwi 0
128uid 1509,0
129)
130(Instance
131name "I_mainTB_w5300"
132duLibraryName "FACT_FAD_TB_lib"
133duName "w5300_emulator"
134elements [
135]
136mwi 0
137uid 2336,0
138)
139]
140embeddedInstances [
141(EmbeddedInstance
142name "eb_mainTB_ID"
143number "1"
144)
145(EmbeddedInstance
146name "eb_mainTB_adc"
147number "2"
148)
149(EmbeddedInstance
150name "eb_mainTB_adc1"
151number "3"
152)
153]
154libraryRefs [
155"ieee"
156"FACT_FAD_lib"
157"std"
158]
159)
160version "29.1"
161appVersion "2009.1 (Build 12)"
162noEmbeddedEditors 1
163model (BlockDiag
164VExpander (VariableExpander
165vvMap [
166(vvPair
167variable "HDLDir"
168value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
169)
170(vvPair
171variable "HDSDir"
172value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
173)
174(vvPair
175variable "SideDataDesignDir"
176value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
177)
178(vvPair
179variable "SideDataUserDir"
180value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
181)
182(vvPair
183variable "SourceDir"
184value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
185)
186(vvPair
187variable "appl"
188value "HDL Designer"
189)
190(vvPair
191variable "arch_name"
192value "struct"
193)
194(vvPair
195variable "config"
196value "%(unit)_%(view)_config"
197)
198(vvPair
199variable "d"
200value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
201)
202(vvPair
203variable "d_logical"
204value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
205)
206(vvPair
207variable "date"
208value "02.03.2011"
209)
210(vvPair
211variable "day"
212value "Mi"
213)
214(vvPair
215variable "day_long"
216value "Mittwoch"
217)
218(vvPair
219variable "dd"
220value "02"
221)
222(vvPair
223variable "entity_name"
224value "fad_main_tb"
225)
226(vvPair
227variable "ext"
228value "<TBD>"
229)
230(vvPair
231variable "f"
232value "struct.bd"
233)
234(vvPair
235variable "f_logical"
236value "struct.bd"
237)
238(vvPair
239variable "f_noext"
240value "struct"
241)
242(vvPair
243variable "group"
244value "UNKNOWN"
245)
246(vvPair
247variable "host"
248value "IHP110"
249)
250(vvPair
251variable "language"
252value "VHDL"
253)
254(vvPair
255variable "library"
256value "FACT_FAD_TB_lib"
257)
258(vvPair
259variable "library_downstream_HdsLintPlugin"
260value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
261)
262(vvPair
263variable "library_downstream_ISEPARInvoke"
264value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
265)
266(vvPair
267variable "library_downstream_ImpactInvoke"
268value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
269)
270(vvPair
271variable "library_downstream_ModelSimCompiler"
272value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
273)
274(vvPair
275variable "library_downstream_XSTDataPrep"
276value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
277)
278(vvPair
279variable "mm"
280value "03"
281)
282(vvPair
283variable "module_name"
284value "fad_main_tb"
285)
286(vvPair
287variable "month"
288value "Mrz"
289)
290(vvPair
291variable "month_long"
292value "März"
293)
294(vvPair
295variable "p"
296value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
297)
298(vvPair
299variable "p_logical"
300value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
301)
302(vvPair
303variable "package_name"
304value "<Undefined Variable>"
305)
306(vvPair
307variable "project_name"
308value "FACT_FAD"
309)
310(vvPair
311variable "series"
312value "HDL Designer Series"
313)
314(vvPair
315variable "task_DesignCompilerPath"
316value "<TBD>"
317)
318(vvPair
319variable "task_LeonardoPath"
320value "<TBD>"
321)
322(vvPair
323variable "task_ModelSimPath"
324value "D:\\modeltech_6.5e\\win32"
325)
326(vvPair
327variable "task_NC-SimPath"
328value "<TBD>"
329)
330(vvPair
331variable "task_PrecisionRTLPath"
332value "<TBD>"
333)
334(vvPair
335variable "task_QuestaSimPath"
336value "<TBD>"
337)
338(vvPair
339variable "task_VCSPath"
340value "<TBD>"
341)
342(vvPair
343variable "this_ext"
344value "bd"
345)
346(vvPair
347variable "this_file"
348value "struct"
349)
350(vvPair
351variable "this_file_logical"
352value "struct"
353)
354(vvPair
355variable "time"
356value "15:31:34"
357)
358(vvPair
359variable "unit"
360value "fad_main_tb"
361)
362(vvPair
363variable "user"
364value "daqct3"
365)
366(vvPair
367variable "version"
368value "2009.1 (Build 12)"
369)
370(vvPair
371variable "view"
372value "struct"
373)
374(vvPair
375variable "year"
376value "2011"
377)
378(vvPair
379variable "yy"
380value "11"
381)
382]
383)
384LanguageMgr "VhdlLangMgr"
385uid 52,0
386optionalChildren [
387*1 (Grouping
388uid 9,0
389optionalChildren [
390*2 (CommentText
391uid 11,0
392shape (Rectangle
393uid 12,0
394sl 0
395va (VaSet
396vasetType 1
397fg "65280,65280,46080"
398)
399xt "109000,97000,126000,98000"
400)
401oxt "18000,70000,35000,71000"
402text (MLText
403uid 13,0
404va (VaSet
405fg "0,0,32768"
406bg "0,0,32768"
407)
408xt "109200,97000,119000,98000"
409st "
410by %user on %dd %month %year
411"
412tm "CommentText"
413wrapOption 3
414visibleHeight 1000
415visibleWidth 17000
416)
417position 1
418ignorePrefs 1
419titleBlock 1
420)
421*3 (CommentText
422uid 14,0
423shape (Rectangle
424uid 15,0
425sl 0
426va (VaSet
427vasetType 1
428fg "65280,65280,46080"
429)
430xt "126000,93000,130000,94000"
431)
432oxt "35000,66000,39000,67000"
433text (MLText
434uid 16,0
435va (VaSet
436fg "0,0,32768"
437bg "0,0,32768"
438)
439xt "126200,93000,129200,94000"
440st "
441Project:
442"
443tm "CommentText"
444wrapOption 3
445visibleHeight 1000
446visibleWidth 4000
447)
448position 1
449ignorePrefs 1
450titleBlock 1
451)
452*4 (CommentText
453uid 17,0
454shape (Rectangle
455uid 18,0
456sl 0
457va (VaSet
458vasetType 1
459fg "65280,65280,46080"
460)
461xt "109000,95000,126000,96000"
462)
463oxt "18000,68000,35000,69000"
464text (MLText
465uid 19,0
466va (VaSet
467fg "0,0,32768"
468bg "0,0,32768"
469)
470xt "109200,95000,119200,96000"
471st "
472<enter diagram title here>
473"
474tm "CommentText"
475wrapOption 3
476visibleHeight 1000
477visibleWidth 17000
478)
479position 1
480ignorePrefs 1
481titleBlock 1
482)
483*5 (CommentText
484uid 20,0
485shape (Rectangle
486uid 21,0
487sl 0
488va (VaSet
489vasetType 1
490fg "65280,65280,46080"
491)
492xt "105000,95000,109000,96000"
493)
494oxt "14000,68000,18000,69000"
495text (MLText
496uid 22,0
497va (VaSet
498fg "0,0,32768"
499bg "0,0,32768"
500)
501xt "105200,95000,107300,96000"
502st "
503Title:
504"
505tm "CommentText"
506wrapOption 3
507visibleHeight 1000
508visibleWidth 4000
509)
510position 1
511ignorePrefs 1
512titleBlock 1
513)
514*6 (CommentText
515uid 23,0
516shape (Rectangle
517uid 24,0
518sl 0
519va (VaSet
520vasetType 1
521fg "65280,65280,46080"
522)
523xt "126000,94000,146000,98000"
524)
525oxt "35000,67000,55000,71000"
526text (MLText
527uid 25,0
528va (VaSet
529fg "0,0,32768"
530bg "0,0,32768"
531)
532xt "126200,94200,135400,95200"
533st "
534<enter comments here>
535"
536tm "CommentText"
537wrapOption 3
538visibleHeight 4000
539visibleWidth 20000
540)
541ignorePrefs 1
542titleBlock 1
543)
544*7 (CommentText
545uid 26,0
546shape (Rectangle
547uid 27,0
548sl 0
549va (VaSet
550vasetType 1
551fg "65280,65280,46080"
552)
553xt "130000,93000,146000,94000"
554)
555oxt "39000,66000,55000,67000"
556text (MLText
557uid 28,0
558va (VaSet
559fg "0,0,32768"
560bg "0,0,32768"
561)
562xt "130200,93000,134700,94000"
563st "
564%project_name
565"
566tm "CommentText"
567wrapOption 3
568visibleHeight 1000
569visibleWidth 16000
570)
571position 1
572ignorePrefs 1
573titleBlock 1
574)
575*8 (CommentText
576uid 29,0
577shape (Rectangle
578uid 30,0
579sl 0
580va (VaSet
581vasetType 1
582fg "65280,65280,46080"
583)
584xt "105000,93000,126000,95000"
585)
586oxt "14000,66000,35000,68000"
587text (MLText
588uid 31,0
589va (VaSet
590fg "32768,0,0"
591)
592xt "112700,93000,118300,95000"
593st "
594TU Dortmund
595Physik / EE
596"
597ju 0
598tm "CommentText"
599wrapOption 3
600visibleHeight 2000
601visibleWidth 21000
602)
603position 1
604ignorePrefs 1
605titleBlock 1
606)
607*9 (CommentText
608uid 32,0
609shape (Rectangle
610uid 33,0
611sl 0
612va (VaSet
613vasetType 1
614fg "65280,65280,46080"
615)
616xt "105000,96000,109000,97000"
617)
618oxt "14000,69000,18000,70000"
619text (MLText
620uid 34,0
621va (VaSet
622fg "0,0,32768"
623bg "0,0,32768"
624)
625xt "105200,96000,107300,97000"
626st "
627Path:
628"
629tm "CommentText"
630wrapOption 3
631visibleHeight 1000
632visibleWidth 4000
633)
634position 1
635ignorePrefs 1
636titleBlock 1
637)
638*10 (CommentText
639uid 35,0
640shape (Rectangle
641uid 36,0
642sl 0
643va (VaSet
644vasetType 1
645fg "65280,65280,46080"
646)
647xt "105000,97000,109000,98000"
648)
649oxt "14000,70000,18000,71000"
650text (MLText
651uid 37,0
652va (VaSet
653fg "0,0,32768"
654bg "0,0,32768"
655)
656xt "105200,97000,107900,98000"
657st "
658Edited:
659"
660tm "CommentText"
661wrapOption 3
662visibleHeight 1000
663visibleWidth 4000
664)
665position 1
666ignorePrefs 1
667titleBlock 1
668)
669*11 (CommentText
670uid 38,0
671shape (Rectangle
672uid 39,0
673sl 0
674va (VaSet
675vasetType 1
676fg "65280,65280,46080"
677)
678xt "109000,96000,126000,97000"
679)
680oxt "18000,69000,35000,70000"
681text (MLText
682uid 40,0
683va (VaSet
684fg "0,0,32768"
685bg "0,0,32768"
686)
687xt "109200,96000,123400,97000"
688st "
689%library/%unit/%view
690"
691tm "CommentText"
692wrapOption 3
693visibleHeight 1000
694visibleWidth 17000
695)
696position 1
697ignorePrefs 1
698titleBlock 1
699)
700]
701shape (GroupingShape
702uid 10,0
703va (VaSet
704vasetType 1
705fg "65535,65535,65535"
706lineStyle 2
707lineWidth 2
708)
709xt "105000,93000,146000,98000"
710)
711oxt "14000,66000,55000,71000"
712)
713*12 (SaComponent
714uid 233,0
715optionalChildren [
716*13 (CptPort
717uid 109,0
718ps "OnEdgeStrategy"
719shape (Triangle
720uid 110,0
721ro 90
722va (VaSet
723vasetType 1
724fg "0,65535,0"
725)
726xt "109000,23625,109750,24375"
727)
728tg (CPTG
729uid 111,0
730ps "CptPortTextPlaceStrategy"
731stg "RightVerticalLayoutStrategy"
732f (Text
733uid 112,0
734va (VaSet
735)
736xt "104400,23500,108000,24500"
737st "wiz_reset"
738ju 2
739blo "108000,24300"
740)
741)
742thePort (LogicalPort
743m 1
744decl (Decl
745n "wiz_reset"
746t "std_logic"
747o 39
748suid 2,0
749i "'1'"
750)
751)
752)
753*14 (CptPort
754uid 113,0
755ps "OnEdgeStrategy"
756shape (Triangle
757uid 114,0
758ro 90
759va (VaSet
760vasetType 1
761fg "0,65535,0"
762)
763xt "109000,69625,109750,70375"
764)
765tg (CPTG
766uid 115,0
767ps "CptPortTextPlaceStrategy"
768stg "RightVerticalLayoutStrategy"
769f (Text
770uid 116,0
771va (VaSet
772)
773xt "104000,69500,108000,70500"
774st "led : (7:0)"
775ju 2
776blo "108000,70300"
777)
778)
779thePort (LogicalPort
780m 1
781decl (Decl
782n "led"
783t "std_logic_vector"
784b "(7 DOWNTO 0)"
785posAdd 0
786o 31
787suid 7,0
788i "(OTHERS => '0')"
789)
790)
791)
792*15 (CptPort
793uid 117,0
794ps "OnEdgeStrategy"
795shape (Triangle
796uid 118,0
797ro 90
798va (VaSet
799vasetType 1
800fg "0,65535,0"
801)
802xt "80250,31625,81000,32375"
803)
804tg (CPTG
805uid 119,0
806ps "CptPortTextPlaceStrategy"
807stg "VerticalLayoutStrategy"
808f (Text
809uid 120,0
810va (VaSet
811)
812xt "82000,31500,84800,32500"
813st "trigger"
814blo "82000,32300"
815)
816)
817thePort (LogicalPort
818decl (Decl
819n "trigger"
820t "std_logic"
821preAdd 0
822posAdd 0
823o 13
824suid 18,0
825)
826)
827)
828*16 (CptPort
829uid 121,0
830ps "OnEdgeStrategy"
831shape (Triangle
832uid 122,0
833ro 270
834va (VaSet
835vasetType 1
836fg "0,65535,0"
837)
838xt "80250,42625,81000,43375"
839)
840tg (CPTG
841uid 123,0
842ps "CptPortTextPlaceStrategy"
843stg "VerticalLayoutStrategy"
844f (Text
845uid 124,0
846va (VaSet
847)
848xt "82000,42500,85200,43500"
849st "adc_oeb"
850blo "82000,43300"
851)
852)
853thePort (LogicalPort
854m 1
855decl (Decl
856n "adc_oeb"
857t "std_logic"
858o 21
859suid 21,0
860i "'1'"
861)
862)
863)
864*17 (CptPort
865uid 125,0
866ps "OnEdgeStrategy"
867shape (Triangle
868uid 126,0
869ro 90
870va (VaSet
871vasetType 1
872fg "0,65535,0"
873)
874xt "80250,33625,81000,34375"
875)
876tg (CPTG
877uid 127,0
878ps "CptPortTextPlaceStrategy"
879stg "VerticalLayoutStrategy"
880f (Text
881uid 128,0
882va (VaSet
883)
884xt "82000,33500,87900,34500"
885st "board_id : (3:0)"
886blo "82000,34300"
887)
888)
889thePort (LogicalPort
890decl (Decl
891n "board_id"
892t "std_logic_vector"
893b "(3 DOWNTO 0)"
894o 9
895suid 24,0
896)
897)
898)
899*18 (CptPort
900uid 129,0
901ps "OnEdgeStrategy"
902shape (Triangle
903uid 130,0
904ro 90
905va (VaSet
906vasetType 1
907fg "0,65535,0"
908)
909xt "80250,34625,81000,35375"
910)
911tg (CPTG
912uid 131,0
913ps "CptPortTextPlaceStrategy"
914stg "VerticalLayoutStrategy"
915f (Text
916uid 132,0
917va (VaSet
918)
919xt "82000,34500,87700,35500"
920st "crate_id : (1:0)"
921blo "82000,35300"
922)
923)
924thePort (LogicalPort
925decl (Decl
926n "crate_id"
927t "std_logic_vector"
928b "(1 DOWNTO 0)"
929o 10
930suid 25,0
931)
932)
933)
934*19 (CptPort
935uid 133,0
936ps "OnEdgeStrategy"
937shape (Triangle
938uid 134,0
939ro 90
940va (VaSet
941vasetType 1
942fg "0,65535,0"
943)
944xt "109000,20625,109750,21375"
945)
946tg (CPTG
947uid 135,0
948ps "CptPortTextPlaceStrategy"
949stg "RightVerticalLayoutStrategy"
950f (Text
951uid 136,0
952va (VaSet
953)
954xt "102000,20500,108000,21500"
955st "wiz_addr : (9:0)"
956ju 2
957blo "108000,21300"
958)
959)
960thePort (LogicalPort
961m 1
962decl (Decl
963n "wiz_addr"
964t "std_logic_vector"
965b "(9 DOWNTO 0)"
966o 36
967suid 26,0
968)
969)
970)
971*20 (CptPort
972uid 137,0
973ps "OnEdgeStrategy"
974shape (Diamond
975uid 138,0
976ro 90
977va (VaSet
978vasetType 1
979fg "0,65535,0"
980)
981xt "109000,21625,109750,22375"
982)
983tg (CPTG
984uid 139,0
985ps "CptPortTextPlaceStrategy"
986stg "RightVerticalLayoutStrategy"
987f (Text
988uid 140,0
989va (VaSet
990)
991xt "101700,21500,108000,22500"
992st "wiz_data : (15:0)"
993ju 2
994blo "108000,22300"
995)
996)
997thePort (LogicalPort
998m 2
999decl (Decl
1000n "wiz_data"
1001t "std_logic_vector"
1002b "(15 DOWNTO 0)"
1003o 42
1004suid 27,0
1005)
1006)
1007)
1008*21 (CptPort
1009uid 141,0
1010ps "OnEdgeStrategy"
1011shape (Triangle
1012uid 142,0
1013ro 90
1014va (VaSet
1015vasetType 1
1016fg "0,65535,0"
1017)
1018xt "109000,27625,109750,28375"
1019)
1020tg (CPTG
1021uid 143,0
1022ps "CptPortTextPlaceStrategy"
1023stg "RightVerticalLayoutStrategy"
1024f (Text
1025uid 144,0
1026va (VaSet
1027)
1028xt "105300,27500,108000,28500"
1029st "wiz_cs"
1030ju 2
1031blo "108000,28300"
1032)
1033)
1034thePort (LogicalPort
1035m 1
1036decl (Decl
1037n "wiz_cs"
1038t "std_logic"
1039o 37
1040suid 28,0
1041i "'1'"
1042)
1043)
1044)
1045*22 (CptPort
1046uid 145,0
1047ps "OnEdgeStrategy"
1048shape (Triangle
1049uid 146,0
1050ro 90
1051va (VaSet
1052vasetType 1
1053fg "0,65535,0"
1054)
1055xt "109000,25625,109750,26375"
1056)
1057tg (CPTG
1058uid 147,0
1059ps "CptPortTextPlaceStrategy"
1060stg "RightVerticalLayoutStrategy"
1061f (Text
1062uid 148,0
1063va (VaSet
1064)
1065xt "105300,25500,108000,26500"
1066st "wiz_wr"
1067ju 2
1068blo "108000,26300"
1069)
1070)
1071thePort (LogicalPort
1072m 1
1073decl (Decl
1074n "wiz_wr"
1075t "std_logic"
1076o 40
1077suid 29,0
1078i "'1'"
1079)
1080)
1081)
1082*23 (CptPort
1083uid 149,0
1084ps "OnEdgeStrategy"
1085shape (Triangle
1086uid 150,0
1087ro 90
1088va (VaSet
1089vasetType 1
1090fg "0,65535,0"
1091)
1092xt "109000,24625,109750,25375"
1093)
1094tg (CPTG
1095uid 151,0
1096ps "CptPortTextPlaceStrategy"
1097stg "RightVerticalLayoutStrategy"
1098f (Text
1099uid 152,0
1100va (VaSet
1101)
1102xt "105400,24500,108000,25500"
1103st "wiz_rd"
1104ju 2
1105blo "108000,25300"
1106)
1107)
1108thePort (LogicalPort
1109m 1
1110decl (Decl
1111n "wiz_rd"
1112t "std_logic"
1113o 38
1114suid 30,0
1115i "'1'"
1116)
1117)
1118)
1119*24 (CptPort
1120uid 153,0
1121ps "OnEdgeStrategy"
1122shape (Triangle
1123uid 154,0
1124ro 270
1125va (VaSet
1126vasetType 1
1127fg "0,65535,0"
1128)
1129xt "109000,26625,109750,27375"
1130)
1131tg (CPTG
1132uid 155,0
1133ps "CptPortTextPlaceStrategy"
1134stg "RightVerticalLayoutStrategy"
1135f (Text
1136uid 156,0
1137va (VaSet
1138)
1139xt "105300,26500,108000,27500"
1140st "wiz_int"
1141ju 2
1142blo "108000,27300"
1143)
1144)
1145thePort (LogicalPort
1146decl (Decl
1147n "wiz_int"
1148t "std_logic"
1149o 14
1150suid 31,0
1151)
1152)
1153)
1154*25 (CptPort
1155uid 157,0
1156ps "OnEdgeStrategy"
1157shape (Triangle
1158uid 158,0
1159ro 270
1160va (VaSet
1161vasetType 1
1162fg "0,65535,0"
1163)
1164xt "80250,22625,81000,23375"
1165)
1166tg (CPTG
1167uid 159,0
1168ps "CptPortTextPlaceStrategy"
1169stg "VerticalLayoutStrategy"
1170f (Text
1171uid 160,0
1172va (VaSet
1173)
1174xt "82000,22500,86500,23500"
1175st "CLK_25_PS"
1176blo "82000,23300"
1177)
1178)
1179thePort (LogicalPort
1180m 1
1181decl (Decl
1182n "CLK_25_PS"
1183t "std_logic"
1184o 16
1185suid 35,0
1186)
1187)
1188)
1189*26 (CptPort
1190uid 161,0
1191ps "OnEdgeStrategy"
1192shape (Triangle
1193uid 162,0
1194ro 270
1195va (VaSet
1196vasetType 1
1197fg "0,65535,0"
1198)
1199xt "80250,21625,81000,22375"
1200)
1201tg (CPTG
1202uid 163,0
1203ps "CptPortTextPlaceStrategy"
1204stg "VerticalLayoutStrategy"
1205f (Text
1206uid 164,0
1207va (VaSet
1208)
1209xt "82000,21500,85100,22500"
1210st "CLK_50"
1211blo "82000,22300"
1212)
1213)
1214thePort (LogicalPort
1215m 1
1216decl (Decl
1217n "CLK_50"
1218t "std_logic"
1219preAdd 0
1220posAdd 0
1221o 17
1222suid 37,0
1223)
1224)
1225)
1226*27 (CptPort
1227uid 165,0
1228ps "OnEdgeStrategy"
1229shape (Triangle
1230uid 166,0
1231ro 90
1232va (VaSet
1233vasetType 1
1234fg "0,65535,0"
1235)
1236xt "80250,20625,81000,21375"
1237)
1238tg (CPTG
1239uid 167,0
1240ps "CptPortTextPlaceStrategy"
1241stg "VerticalLayoutStrategy"
1242f (Text
1243uid 168,0
1244va (VaSet
1245)
1246xt "82000,20500,83900,21500"
1247st "CLK"
1248blo "82000,21300"
1249)
1250)
1251thePort (LogicalPort
1252decl (Decl
1253n "CLK"
1254t "std_logic"
1255o 1
1256suid 38,0
1257)
1258)
1259)
1260*28 (CptPort
1261uid 169,0
1262ps "OnEdgeStrategy"
1263shape (Triangle
1264uid 170,0
1265ro 90
1266va (VaSet
1267vasetType 1
1268fg "0,65535,0"
1269)
1270xt "80250,41625,81000,42375"
1271)
1272tg (CPTG
1273uid 171,0
1274ps "CptPortTextPlaceStrategy"
1275stg "VerticalLayoutStrategy"
1276f (Text
1277uid 172,0
1278va (VaSet
1279)
1280xt "82000,41500,90000,42500"
1281st "adc_otr_array : (3:0)"
1282blo "82000,42300"
1283)
1284)
1285thePort (LogicalPort
1286decl (Decl
1287n "adc_otr_array"
1288t "std_logic_vector"
1289b "(3 DOWNTO 0)"
1290o 8
1291suid 40,0
1292)
1293)
1294)
1295*29 (CptPort
1296uid 173,0
1297ps "OnEdgeStrategy"
1298shape (Triangle
1299uid 174,0
1300ro 90
1301va (VaSet
1302vasetType 1
1303fg "0,65535,0"
1304)
1305xt "80250,47625,81000,48375"
1306)
1307tg (CPTG
1308uid 175,0
1309ps "CptPortTextPlaceStrategy"
1310stg "VerticalLayoutStrategy"
1311f (Text
1312uid 176,0
1313va (VaSet
1314)
1315xt "82000,47500,87900,48500"
1316st "adc_data_array"
1317blo "82000,48300"
1318)
1319)
1320thePort (LogicalPort
1321decl (Decl
1322n "adc_data_array"
1323t "adc_data_array_type"
1324o 7
1325suid 41,0
1326)
1327)
1328)
1329*30 (CptPort
1330uid 177,0
1331ps "OnEdgeStrategy"
1332shape (Triangle
1333uid 178,0
1334ro 270
1335va (VaSet
1336vasetType 1
1337fg "0,65535,0"
1338)
1339xt "80250,61625,81000,62375"
1340)
1341tg (CPTG
1342uid 179,0
1343ps "CptPortTextPlaceStrategy"
1344stg "VerticalLayoutStrategy"
1345f (Text
1346uid 180,0
1347va (VaSet
1348)
1349xt "82000,61500,90500,62500"
1350st "drs_channel_id : (3:0)"
1351blo "82000,62300"
1352)
1353)
1354thePort (LogicalPort
1355m 1
1356decl (Decl
1357n "drs_channel_id"
1358t "std_logic_vector"
1359b "(3 downto 0)"
1360o 28
1361suid 48,0
1362i "(others => '0')"
1363)
1364)
1365)
1366*31 (CptPort
1367uid 181,0
1368ps "OnEdgeStrategy"
1369shape (Triangle
1370uid 182,0
1371ro 270
1372va (VaSet
1373vasetType 1
1374fg "0,65535,0"
1375)
1376xt "80250,66625,81000,67375"
1377)
1378tg (CPTG
1379uid 183,0
1380ps "CptPortTextPlaceStrategy"
1381stg "VerticalLayoutStrategy"
1382f (Text
1383uid 184,0
1384va (VaSet
1385)
1386xt "82000,66500,86300,67500"
1387st "drs_dwrite"
1388blo "82000,67300"
1389)
1390)
1391thePort (LogicalPort
1392m 1
1393decl (Decl
1394n "drs_dwrite"
1395t "std_logic"
1396o 29
1397suid 49,0
1398i "'1'"
1399)
1400)
1401)
1402*32 (CptPort
1403uid 185,0
1404ps "OnEdgeStrategy"
1405shape (Triangle
1406uid 186,0
1407ro 90
1408va (VaSet
1409vasetType 1
1410fg "0,65535,0"
1411)
1412xt "80250,57625,81000,58375"
1413)
1414tg (CPTG
1415uid 187,0
1416ps "CptPortTextPlaceStrategy"
1417stg "VerticalLayoutStrategy"
1418f (Text
1419uid 188,0
1420va (VaSet
1421)
1422xt "82000,57500,87400,58500"
1423st "SROUT_in_0"
1424blo "82000,58300"
1425)
1426)
1427thePort (LogicalPort
1428decl (Decl
1429n "SROUT_in_0"
1430t "std_logic"
1431o 3
1432suid 52,0
1433)
1434)
1435)
1436*33 (CptPort
1437uid 189,0
1438ps "OnEdgeStrategy"
1439shape (Triangle
1440uid 190,0
1441ro 90
1442va (VaSet
1443vasetType 1
1444fg "0,65535,0"
1445)
1446xt "80250,58625,81000,59375"
1447)
1448tg (CPTG
1449uid 191,0
1450ps "CptPortTextPlaceStrategy"
1451stg "VerticalLayoutStrategy"
1452f (Text
1453uid 192,0
1454va (VaSet
1455)
1456xt "82000,58500,87400,59500"
1457st "SROUT_in_1"
1458blo "82000,59300"
1459)
1460)
1461thePort (LogicalPort
1462decl (Decl
1463n "SROUT_in_1"
1464t "std_logic"
1465o 4
1466suid 53,0
1467)
1468)
1469)
1470*34 (CptPort
1471uid 193,0
1472ps "OnEdgeStrategy"
1473shape (Triangle
1474uid 194,0
1475ro 90
1476va (VaSet
1477vasetType 1
1478fg "0,65535,0"
1479)
1480xt "80250,59625,81000,60375"
1481)
1482tg (CPTG
1483uid 195,0
1484ps "CptPortTextPlaceStrategy"
1485stg "VerticalLayoutStrategy"
1486f (Text
1487uid 196,0
1488va (VaSet
1489)
1490xt "82000,59500,87400,60500"
1491st "SROUT_in_2"
1492blo "82000,60300"
1493)
1494)
1495thePort (LogicalPort
1496decl (Decl
1497n "SROUT_in_2"
1498t "std_logic"
1499o 5
1500suid 54,0
1501)
1502)
1503)
1504*35 (CptPort
1505uid 197,0
1506ps "OnEdgeStrategy"
1507shape (Triangle
1508uid 198,0
1509ro 90
1510va (VaSet
1511vasetType 1
1512fg "0,65535,0"
1513)
1514xt "80250,60625,81000,61375"
1515)
1516tg (CPTG
1517uid 199,0
1518ps "CptPortTextPlaceStrategy"
1519stg "VerticalLayoutStrategy"
1520f (Text
1521uid 200,0
1522va (VaSet
1523)
1524xt "82000,60500,87400,61500"
1525st "SROUT_in_3"
1526blo "82000,61300"
1527)
1528)
1529thePort (LogicalPort
1530decl (Decl
1531n "SROUT_in_3"
1532t "std_logic"
1533o 6
1534suid 55,0
1535)
1536)
1537)
1538*36 (CptPort
1539uid 201,0
1540ps "OnEdgeStrategy"
1541shape (Triangle
1542uid 202,0
1543ro 270
1544va (VaSet
1545vasetType 1
1546fg "0,65535,0"
1547)
1548xt "80250,63625,81000,64375"
1549)
1550tg (CPTG
1551uid 203,0
1552ps "CptPortTextPlaceStrategy"
1553stg "VerticalLayoutStrategy"
1554f (Text
1555uid 204,0
1556va (VaSet
1557)
1558xt "82000,63500,86200,64500"
1559st "RSRLOAD"
1560blo "82000,64300"
1561)
1562)
1563thePort (LogicalPort
1564m 1
1565decl (Decl
1566n "RSRLOAD"
1567t "std_logic"
1568o 18
1569suid 56,0
1570i "'0'"
1571)
1572)
1573)
1574*37 (CptPort
1575uid 205,0
1576ps "OnEdgeStrategy"
1577shape (Triangle
1578uid 206,0
1579ro 270
1580va (VaSet
1581vasetType 1
1582fg "0,65535,0"
1583)
1584xt "80250,64625,81000,65375"
1585)
1586tg (CPTG
1587uid 207,0
1588ps "CptPortTextPlaceStrategy"
1589stg "VerticalLayoutStrategy"
1590f (Text
1591uid 208,0
1592va (VaSet
1593)
1594xt "82000,64500,85000,65500"
1595st "SRCLK"
1596blo "82000,65300"
1597)
1598)
1599thePort (LogicalPort
1600m 1
1601decl (Decl
1602n "SRCLK"
1603t "std_logic"
1604o 19
1605suid 57,0
1606i "'0'"
1607)
1608)
1609)
1610*38 (CptPort
1611uid 209,0
1612ps "OnEdgeStrategy"
1613shape (Triangle
1614uid 210,0
1615ro 90
1616va (VaSet
1617vasetType 1
1618fg "0,65535,0"
1619)
1620xt "109000,50625,109750,51375"
1621)
1622tg (CPTG
1623uid 211,0
1624ps "CptPortTextPlaceStrategy"
1625stg "RightVerticalLayoutStrategy"
1626f (Text
1627uid 212,0
1628va (VaSet
1629)
1630xt "106300,50500,108000,51500"
1631st "sclk"
1632ju 2
1633blo "108000,51300"
1634)
1635)
1636thePort (LogicalPort
1637m 1
1638decl (Decl
1639n "sclk"
1640t "std_logic"
1641o 34
1642suid 62,0
1643)
1644)
1645)
1646*39 (CptPort
1647uid 213,0
1648ps "OnEdgeStrategy"
1649shape (Diamond
1650uid 214,0
1651ro 90
1652va (VaSet
1653vasetType 1
1654fg "0,65535,0"
1655)
1656xt "109000,51625,109750,52375"
1657)
1658tg (CPTG
1659uid 215,0
1660ps "CptPortTextPlaceStrategy"
1661stg "RightVerticalLayoutStrategy"
1662f (Text
1663uid 216,0
1664va (VaSet
1665)
1666xt "106600,51500,108000,52500"
1667st "sio"
1668ju 2
1669blo "108000,52300"
1670)
1671)
1672thePort (LogicalPort
1673m 2
1674decl (Decl
1675n "sio"
1676t "std_logic"
1677preAdd 0
1678posAdd 0
1679o 41
1680suid 63,0
1681)
1682)
1683)
1684*40 (CptPort
1685uid 217,0
1686ps "OnEdgeStrategy"
1687shape (Triangle
1688uid 218,0
1689ro 90
1690va (VaSet
1691vasetType 1
1692fg "0,65535,0"
1693)
1694xt "109000,39625,109750,40375"
1695)
1696tg (CPTG
1697uid 219,0
1698ps "CptPortTextPlaceStrategy"
1699stg "RightVerticalLayoutStrategy"
1700f (Text
1701uid 220,0
1702va (VaSet
1703)
1704xt "105200,39500,108000,40500"
1705st "dac_cs"
1706ju 2
1707blo "108000,40300"
1708)
1709)
1710thePort (LogicalPort
1711m 1
1712decl (Decl
1713n "dac_cs"
1714t "std_logic"
1715o 26
1716suid 64,0
1717)
1718)
1719)
1720*41 (CptPort
1721uid 221,0
1722ps "OnEdgeStrategy"
1723shape (Triangle
1724uid 222,0
1725ro 90
1726va (VaSet
1727vasetType 1
1728fg "0,65535,0"
1729)
1730xt "109000,41625,109750,42375"
1731)
1732tg (CPTG
1733uid 223,0
1734ps "CptPortTextPlaceStrategy"
1735stg "RightVerticalLayoutStrategy"
1736f (Text
1737uid 224,0
1738va (VaSet
1739)
1740xt "101500,41500,108000,42500"
1741st "sensor_cs : (3:0)"
1742ju 2
1743blo "108000,42300"
1744)
1745)
1746thePort (LogicalPort
1747m 1
1748decl (Decl
1749n "sensor_cs"
1750t "std_logic_vector"
1751b "(3 DOWNTO 0)"
1752o 35
1753suid 65,0
1754)
1755)
1756)
1757*42 (CptPort
1758uid 225,0
1759ps "OnEdgeStrategy"
1760shape (Triangle
1761uid 226,0
1762ro 90
1763va (VaSet
1764vasetType 1
1765fg "0,65535,0"
1766)
1767xt "109000,52625,109750,53375"
1768)
1769tg (CPTG
1770uid 227,0
1771ps "CptPortTextPlaceStrategy"
1772stg "RightVerticalLayoutStrategy"
1773f (Text
1774uid 228,0
1775va (VaSet
1776)
1777xt "106000,52500,108000,53500"
1778st "mosi"
1779ju 2
1780blo "108000,53300"
1781)
1782)
1783thePort (LogicalPort
1784m 1
1785decl (Decl
1786n "mosi"
1787t "std_logic"
1788o 32
1789suid 66,0
1790i "'0'"
1791)
1792)
1793)
1794*43 (CptPort
1795uid 229,0
1796ps "OnEdgeStrategy"
1797shape (Triangle
1798uid 230,0
1799ro 270
1800va (VaSet
1801vasetType 1
1802fg "0,65535,0"
1803)
1804xt "80250,65625,81000,66375"
1805)
1806tg (CPTG
1807uid 231,0
1808ps "CptPortTextPlaceStrategy"
1809stg "VerticalLayoutStrategy"
1810f (Text
1811uid 232,0
1812va (VaSet
1813)
1814xt "82000,65500,85000,66500"
1815st "denable"
1816blo "82000,66300"
1817)
1818)
1819thePort (LogicalPort
1820m 1
1821decl (Decl
1822n "denable"
1823t "std_logic"
1824eolc "-- default domino wave off"
1825posAdd 0
1826o 27
1827suid 67,0
1828i "'0'"
1829)
1830)
1831)
1832*44 (CptPort
1833uid 1395,0
1834ps "OnEdgeStrategy"
1835shape (Triangle
1836uid 1396,0
1837ro 90
1838va (VaSet
1839vasetType 1
1840fg "0,65535,0"
1841)
1842xt "109000,73625,109750,74375"
1843)
1844tg (CPTG
1845uid 1397,0
1846ps "CptPortTextPlaceStrategy"
1847stg "RightVerticalLayoutStrategy"
1848f (Text
1849uid 1398,0
1850va (VaSet
1851)
1852xt "99400,73500,108000,74500"
1853st "alarm_refclk_too_high"
1854ju 2
1855blo "108000,74300"
1856)
1857)
1858thePort (LogicalPort
1859m 1
1860decl (Decl
1861n "alarm_refclk_too_high"
1862t "std_logic"
1863o 22
1864suid 95,0
1865)
1866)
1867)
1868*45 (CptPort
1869uid 1399,0
1870ps "OnEdgeStrategy"
1871shape (Triangle
1872uid 1400,0
1873ro 90
1874va (VaSet
1875vasetType 1
1876fg "0,65535,0"
1877)
1878xt "109000,74625,109750,75375"
1879)
1880tg (CPTG
1881uid 1401,0
1882ps "CptPortTextPlaceStrategy"
1883stg "RightVerticalLayoutStrategy"
1884f (Text
1885uid 1402,0
1886va (VaSet
1887)
1888xt "99800,74500,108000,75500"
1889st "alarm_refclk_too_low"
1890ju 2
1891blo "108000,75300"
1892)
1893)
1894thePort (LogicalPort
1895m 1
1896decl (Decl
1897n "alarm_refclk_too_low"
1898t "std_logic"
1899posAdd 0
1900o 23
1901suid 96,0
1902)
1903)
1904)
1905*46 (CptPort
1906uid 1403,0
1907ps "OnEdgeStrategy"
1908shape (Triangle
1909uid 1404,0
1910ro 90
1911va (VaSet
1912vasetType 1
1913fg "0,65535,0"
1914)
1915xt "109000,79625,109750,80375"
1916)
1917tg (CPTG
1918uid 1405,0
1919ps "CptPortTextPlaceStrategy"
1920stg "RightVerticalLayoutStrategy"
1921f (Text
1922uid 1406,0
1923va (VaSet
1924)
1925xt "105500,79500,108000,80500"
1926st "amber"
1927ju 2
1928blo "108000,80300"
1929)
1930)
1931thePort (LogicalPort
1932m 1
1933decl (Decl
1934n "amber"
1935t "std_logic"
1936o 24
1937suid 87,0
1938)
1939)
1940)
1941*47 (CptPort
1942uid 1407,0
1943ps "OnEdgeStrategy"
1944shape (Triangle
1945uid 1408,0
1946ro 90
1947va (VaSet
1948vasetType 1
1949fg "0,65535,0"
1950)
1951xt "109000,76625,109750,77375"
1952)
1953tg (CPTG
1954uid 1409,0
1955ps "CptPortTextPlaceStrategy"
1956stg "RightVerticalLayoutStrategy"
1957f (Text
1958uid 1410,0
1959va (VaSet
1960)
1961xt "99400,76500,108000,77500"
1962st "counter_result : (11:0)"
1963ju 2
1964blo "108000,77300"
1965)
1966)
1967thePort (LogicalPort
1968m 1
1969decl (Decl
1970n "counter_result"
1971t "std_logic_vector"
1972b "(11 DOWNTO 0)"
1973o 25
1974suid 94,0
1975)
1976)
1977)
1978*48 (CptPort
1979uid 1411,0
1980ps "OnEdgeStrategy"
1981shape (Triangle
1982uid 1412,0
1983ro 90
1984va (VaSet
1985vasetType 1
1986fg "0,65535,0"
1987)
1988xt "80250,74625,81000,75375"
1989)
1990tg (CPTG
1991uid 1413,0
1992ps "CptPortTextPlaceStrategy"
1993stg "VerticalLayoutStrategy"
1994f (Text
1995uid 1414,0
1996va (VaSet
1997)
1998xt "82000,74500,87500,75500"
1999st "D_T_in : (1:0)"
2000blo "82000,75300"
2001)
2002)
2003thePort (LogicalPort
2004decl (Decl
2005n "D_T_in"
2006t "std_logic_vector"
2007b "(1 DOWNTO 0)"
2008o 2
2009suid 91,0
2010)
2011)
2012)
2013*49 (CptPort
2014uid 1415,0
2015ps "OnEdgeStrategy"
2016shape (Triangle
2017uid 1416,0
2018ro 90
2019va (VaSet
2020vasetType 1
2021fg "0,65535,0"
2022)
2023xt "80250,75625,81000,76375"
2024)
2025tg (CPTG
2026uid 1417,0
2027ps "CptPortTextPlaceStrategy"
2028stg "VerticalLayoutStrategy"
2029f (Text
2030uid 1418,0
2031va (VaSet
2032)
2033xt "82000,75500,87100,76500"
2034st "drs_refclk_in"
2035blo "82000,76300"
2036)
2037)
2038thePort (LogicalPort
2039decl (Decl
2040n "drs_refclk_in"
2041t "std_logic"
2042eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
2043o 11
2044suid 92,0
2045)
2046)
2047)
2048*50 (CptPort
2049uid 1419,0
2050ps "OnEdgeStrategy"
2051shape (Triangle
2052uid 1420,0
2053ro 90
2054va (VaSet
2055vasetType 1
2056fg "0,65535,0"
2057)
2058xt "109000,77625,109750,78375"
2059)
2060tg (CPTG
2061uid 1421,0
2062ps "CptPortTextPlaceStrategy"
2063stg "RightVerticalLayoutStrategy"
2064f (Text
2065uid 1422,0
2066va (VaSet
2067)
2068xt "105600,77500,108000,78500"
2069st "green"
2070ju 2
2071blo "108000,78300"
2072)
2073)
2074thePort (LogicalPort
2075m 1
2076decl (Decl
2077n "green"
2078t "std_logic"
2079o 30
2080suid 86,0
2081)
2082)
2083)
2084*51 (CptPort
2085uid 1423,0
2086ps "OnEdgeStrategy"
2087shape (Triangle
2088uid 1424,0
2089ro 90
2090va (VaSet
2091vasetType 1
2092fg "0,65535,0"
2093)
2094xt "80250,76625,81000,77375"
2095)
2096tg (CPTG
2097uid 1425,0
2098ps "CptPortTextPlaceStrategy"
2099stg "VerticalLayoutStrategy"
2100f (Text
2101uid 1426,0
2102va (VaSet
2103)
2104xt "82000,76500,88100,77500"
2105st "plllock_in : (3:0)"
2106blo "82000,77300"
2107)
2108)
2109thePort (LogicalPort
2110decl (Decl
2111n "plllock_in"
2112t "std_logic_vector"
2113b "(3 DOWNTO 0)"
2114eolc "-- high level, if dominowave is running and DRS PLL locked"
2115o 12
2116suid 93,0
2117)
2118)
2119)
2120*52 (CptPort
2121uid 1427,0
2122ps "OnEdgeStrategy"
2123shape (Triangle
2124uid 1428,0
2125ro 90
2126va (VaSet
2127vasetType 1
2128fg "0,65535,0"
2129)
2130xt "109000,78625,109750,79375"
2131)
2132tg (CPTG
2133uid 1429,0
2134ps "CptPortTextPlaceStrategy"
2135stg "RightVerticalLayoutStrategy"
2136f (Text
2137uid 1430,0
2138va (VaSet
2139)
2140xt "106500,78500,108000,79500"
2141st "red"
2142ju 2
2143blo "108000,79300"
2144)
2145)
2146thePort (LogicalPort
2147m 1
2148decl (Decl
2149n "red"
2150t "std_logic"
2151o 33
2152suid 88,0
2153)
2154)
2155)
2156*53 (CptPort
2157uid 1431,0
2158ps "OnEdgeStrategy"
2159shape (Triangle
2160uid 1432,0
2161ro 270
2162va (VaSet
2163vasetType 1
2164fg "0,65535,0"
2165)
2166xt "80250,71625,81000,72375"
2167)
2168tg (CPTG
2169uid 1433,0
2170ps "CptPortTextPlaceStrategy"
2171stg "VerticalLayoutStrategy"
2172f (Text
2173uid 1434,0
2174va (VaSet
2175)
2176xt "82000,71500,85700,72500"
2177st "SRIN_out"
2178blo "82000,72300"
2179)
2180)
2181thePort (LogicalPort
2182m 1
2183decl (Decl
2184n "SRIN_out"
2185t "std_logic"
2186o 20
2187suid 85,0
2188i "'0'"
2189)
2190)
2191)
2192*54 (CptPort
2193uid 1678,0
2194ps "OnEdgeStrategy"
2195shape (Triangle
2196uid 1679,0
2197ro 270
2198va (VaSet
2199vasetType 1
2200fg "0,65535,0"
2201)
2202xt "80250,23625,81000,24375"
2203)
2204tg (CPTG
2205uid 1680,0
2206ps "CptPortTextPlaceStrategy"
2207stg "VerticalLayoutStrategy"
2208f (Text
2209uid 1681,0
2210va (VaSet
2211)
2212xt "82000,23500,86000,24500"
2213st "ADC_CLK"
2214blo "82000,24300"
2215)
2216)
2217thePort (LogicalPort
2218lang 2
2219m 1
2220decl (Decl
2221n "ADC_CLK"
2222t "std_logic"
2223o 15
2224suid 97,0
2225)
2226)
2227)
2228]
2229shape (Rectangle
2230uid 234,0
2231va (VaSet
2232vasetType 1
2233fg "0,65535,0"
2234lineColor "0,32896,0"
2235lineWidth 2
2236)
2237xt "81000,19000,109000,81000"
2238)
2239oxt "15000,-8000,43000,46000"
2240ttg (MlTextGroup
2241uid 235,0
2242ps "CenterOffsetStrategy"
2243stg "VerticalLayoutStrategy"
2244textVec [
2245*55 (Text
2246uid 236,0
2247va (VaSet
2248font "Arial,8,1"
2249)
2250xt "83200,81000,89400,82000"
2251st "FACT_FAD_lib"
2252blo "83200,81800"
2253tm "BdLibraryNameMgr"
2254)
2255*56 (Text
2256uid 237,0
2257va (VaSet
2258font "Arial,8,1"
2259)
2260xt "83200,82000,87400,83000"
2261st "FAD_main"
2262blo "83200,82800"
2263tm "CptNameMgr"
2264)
2265*57 (Text
2266uid 238,0
2267va (VaSet
2268font "Arial,8,1"
2269)
2270xt "83200,83000,90000,84000"
2271st "I_mainTB_FPGA"
2272blo "83200,83800"
2273tm "InstanceNameMgr"
2274)
2275]
2276)
2277ga (GenericAssociation
2278uid 239,0
2279ps "EdgeToEdgeStrategy"
2280matrix (Matrix
2281uid 240,0
2282text (MLText
2283uid 241,0
2284va (VaSet
2285font "Courier New,8,0"
2286)
2287xt "81000,18200,101000,19000"
2288st "RAMADDRWIDTH64b = 15    ( integer )  "
2289)
2290header ""
2291)
2292elements [
2293(GiElement
2294name "RAMADDRWIDTH64b"
2295type "integer"
2296value "15"
2297)
2298]
2299)
2300viewicon (ZoomableIcon
2301uid 242,0
2302sl 0
2303va (VaSet
2304vasetType 1
2305fg "49152,49152,49152"
2306)
2307xt "81250,79250,82750,80750"
2308iconName "BlockDiagram.png"
2309iconMaskName "BlockDiagram.msk"
2310ftype 1
2311)
2312viewiconposition 0
2313portVis (PortSigDisplay
2314)
2315archFileType "UNKNOWN"
2316)
2317*58 (SaComponent
2318uid 274,0
2319optionalChildren [
2320*59 (CptPort
2321uid 266,0
2322ps "OnEdgeStrategy"
2323shape (Triangle
2324uid 267,0
2325ro 90
2326va (VaSet
2327vasetType 1
2328fg "0,65535,0"
2329)
2330xt "58000,20625,58750,21375"
2331)
2332tg (CPTG
2333uid 268,0
2334ps "CptPortTextPlaceStrategy"
2335stg "RightVerticalLayoutStrategy"
2336f (Text
2337uid 269,0
2338va (VaSet
2339)
2340xt "55700,20500,57000,21500"
2341st "clk"
2342ju 2
2343blo "57000,21300"
2344)
2345)
2346thePort (LogicalPort
2347m 1
2348decl (Decl
2349n "clk"
2350t "STD_LOGIC"
2351o 1
2352i "'0'"
2353)
2354)
2355)
2356*60 (CptPort
2357uid 270,0
2358ps "OnEdgeStrategy"
2359shape (Triangle
2360uid 271,0
2361ro 90
2362va (VaSet
2363vasetType 1
2364fg "0,65535,0"
2365)
2366xt "58000,21625,58750,22375"
2367)
2368tg (CPTG
2369uid 272,0
2370ps "CptPortTextPlaceStrategy"
2371stg "RightVerticalLayoutStrategy"
2372f (Text
2373uid 273,0
2374va (VaSet
2375)
2376xt "55700,21500,57000,22500"
2377st "rst"
2378ju 2
2379blo "57000,22300"
2380)
2381)
2382thePort (LogicalPort
2383m 1
2384decl (Decl
2385n "rst"
2386t "STD_LOGIC"
2387o 2
2388i "'0'"
2389)
2390)
2391)
2392]
2393shape (Rectangle
2394uid 275,0
2395va (VaSet
2396vasetType 1
2397fg "0,49152,49152"
2398lineColor "0,0,50000"
2399lineWidth 2
2400)
2401xt "50000,19000,58000,24000"
2402)
2403oxt "0,0,8000,10000"
2404ttg (MlTextGroup
2405uid 276,0
2406ps "CenterOffsetStrategy"
2407stg "VerticalLayoutStrategy"
2408textVec [
2409*61 (Text
2410uid 277,0
2411va (VaSet
2412font "Arial,8,1"
2413)
2414xt "50150,24000,57850,25000"
2415st "FACT_FAD_TB_lib"
2416blo "50150,24800"
2417tm "BdLibraryNameMgr"
2418)
2419*62 (Text
2420uid 278,0
2421va (VaSet
2422font "Arial,8,1"
2423)
2424xt "50150,25000,56850,26000"
2425st "clock_generator"
2426blo "50150,25800"
2427tm "CptNameMgr"
2428)
2429*63 (Text
2430uid 279,0
2431va (VaSet
2432font "Arial,8,1"
2433)
2434xt "50150,26000,56750,27000"
2435st "I_mainTB_clock"
2436blo "50150,26800"
2437tm "InstanceNameMgr"
2438)
2439]
2440)
2441ga (GenericAssociation
2442uid 280,0
2443ps "EdgeToEdgeStrategy"
2444matrix (Matrix
2445uid 281,0
2446text (MLText
2447uid 282,0
2448va (VaSet
2449font "Courier New,8,0"
2450)
2451xt "50000,17400,68500,19000"
2452st "clock_period = 20 ns    ( time ) 
2453reset_time   = 50 ns    ( time )  "
2454)
2455header ""
2456)
2457elements [
2458(GiElement
2459name "clock_period"
2460type "time"
2461value "20 ns"
2462)
2463(GiElement
2464name "reset_time"
2465type "time"
2466value "50 ns"
2467)
2468]
2469)
2470viewicon (ZoomableIcon
2471uid 283,0
2472sl 0
2473va (VaSet
2474vasetType 1
2475fg "49152,49152,49152"
2476)
2477xt "50250,22250,51750,23750"
2478iconName "VhdlFileViewIcon.png"
2479iconMaskName "VhdlFileViewIcon.msk"
2480ftype 10
2481)
2482ordering 1
2483viewiconposition 0
2484portVis (PortSigDisplay
2485)
2486archFileType "UNKNOWN"
2487)
2488*64 (Net
2489uid 284,0
2490decl (Decl
2491n "clk"
2492t "STD_LOGIC"
2493preAdd 0
2494posAdd 0
2495o 1
2496suid 1,0
2497)
2498declText (MLText
2499uid 285,0
2500va (VaSet
2501font "Courier New,8,0"
2502)
2503xt "-90000,41400,-68000,42200"
2504st "SIGNAL clk                   : STD_LOGIC"
2505)
2506)
2507*65 (Net
2508uid 316,0
2509decl (Decl
2510n "wiz_addr"
2511t "std_logic_vector"
2512b "(9 DOWNTO 0)"
2513o 2
2514suid 2,0
2515)
2516declText (MLText
2517uid 317,0
2518va (VaSet
2519font "Courier New,8,0"
2520)
2521xt "-90000,54200,-58500,55000"
2522st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)"
2523)
2524)
2525*66 (Net
2526uid 322,0
2527decl (Decl
2528n "wiz_data"
2529t "std_logic_vector"
2530b "(15 DOWNTO 0)"
2531o 3
2532suid 3,0
2533)
2534declText (MLText
2535uid 323,0
2536va (VaSet
2537font "Courier New,8,0"
2538)
2539xt "-90000,55800,-58000,56600"
2540st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)"
2541)
2542)
2543*67 (Net
2544uid 328,0
2545decl (Decl
2546n "wiz_rd"
2547t "std_logic"
2548o 4
2549suid 4,0
2550i "'1'"
2551)
2552declText (MLText
2553uid 329,0
2554va (VaSet
2555font "Courier New,8,0"
2556)
2557xt "-90000,57400,-55000,58200"
2558st "SIGNAL wiz_rd                : std_logic                    := '1'"
2559)
2560)
2561*68 (Net
2562uid 334,0
2563decl (Decl
2564n "wiz_wr"
2565t "std_logic"
2566o 5
2567suid 5,0
2568i "'1'"
2569)
2570declText (MLText
2571uid 335,0
2572va (VaSet
2573font "Courier New,8,0"
2574)
2575xt "-90000,59000,-55000,59800"
2576st "SIGNAL wiz_wr                : std_logic                    := '1'"
2577)
2578)
2579*69 (SaComponent
2580uid 362,0
2581optionalChildren [
2582*70 (CptPort
2583uid 350,0
2584ps "OnEdgeStrategy"
2585shape (Triangle
2586uid 351,0
2587ro 90
2588va (VaSet
2589vasetType 1
2590fg "0,65535,0"
2591)
2592xt "122250,50625,123000,51375"
2593)
2594tg (CPTG
2595uid 352,0
2596ps "CptPortTextPlaceStrategy"
2597stg "VerticalLayoutStrategy"
2598f (Text
2599uid 353,0
2600va (VaSet
2601)
2602xt "124000,50500,125700,51500"
2603st "sclk"
2604blo "124000,51300"
2605)
2606)
2607thePort (LogicalPort
2608decl (Decl
2609n "sclk"
2610t "std_logic"
2611preAdd 0
2612posAdd 0
2613o 1
2614suid 1,0
2615)
2616)
2617)
2618*71 (CptPort
2619uid 354,0
2620ps "OnEdgeStrategy"
2621shape (Diamond
2622uid 355,0
2623ro 270
2624va (VaSet
2625vasetType 1
2626fg "0,65535,0"
2627)
2628xt "122250,51625,123000,52375"
2629)
2630tg (CPTG
2631uid 356,0
2632ps "CptPortTextPlaceStrategy"
2633stg "VerticalLayoutStrategy"
2634f (Text
2635uid 357,0
2636va (VaSet
2637)
2638xt "124000,51500,125400,52500"
2639st "sio"
2640blo "124000,52300"
2641)
2642)
2643thePort (LogicalPort
2644m 2
2645decl (Decl
2646n "sio"
2647t "std_logic"
2648preAdd 0
2649posAdd 0
2650o 2
2651suid 2,0
2652)
2653)
2654)
2655*72 (CptPort
2656uid 358,0
2657ps "OnEdgeStrategy"
2658shape (Triangle
2659uid 359,0
2660ro 90
2661va (VaSet
2662vasetType 1
2663fg "0,65535,0"
2664)
2665xt "122250,47625,123000,48375"
2666)
2667tg (CPTG
2668uid 360,0
2669ps "CptPortTextPlaceStrategy"
2670stg "VerticalLayoutStrategy"
2671f (Text
2672uid 361,0
2673va (VaSet
2674)
2675xt "124000,47500,130500,48500"
2676st "sensor_cs : (3:0)"
2677blo "124000,48300"
2678)
2679)
2680thePort (LogicalPort
2681decl (Decl
2682n "sensor_cs"
2683t "std_logic_vector"
2684b "(3 downto 0)"
2685preAdd 0
2686posAdd 0
2687o 3
2688suid 3,0
2689)
2690)
2691)
2692]
2693shape (Rectangle
2694uid 363,0
2695va (VaSet
2696vasetType 1
2697fg "0,49152,49152"
2698lineColor "0,0,50000"
2699lineWidth 2
2700)
2701xt "123000,46000,133000,56000"
2702)
2703oxt "30000,3000,40000,13000"
2704ttg (MlTextGroup
2705uid 364,0
2706ps "CenterOffsetStrategy"
2707stg "VerticalLayoutStrategy"
2708textVec [
2709*73 (Text
2710uid 365,0
2711va (VaSet
2712font "Arial,8,1"
2713)
2714xt "123200,56000,130900,57000"
2715st "FACT_FAD_TB_lib"
2716blo "123200,56800"
2717tm "BdLibraryNameMgr"
2718)
2719*74 (Text
2720uid 366,0
2721va (VaSet
2722font "Arial,8,1"
2723)
2724xt "123200,57000,130800,58000"
2725st "max6662_emulator"
2726blo "123200,57800"
2727tm "CptNameMgr"
2728)
2729*75 (Text
2730uid 367,0
2731va (VaSet
2732font "Arial,8,1"
2733)
2734xt "123200,58000,131000,59000"
2735st "I_mainTB_max6662"
2736blo "123200,58800"
2737tm "InstanceNameMgr"
2738)
2739]
2740)
2741ga (GenericAssociation
2742uid 368,0
2743ps "EdgeToEdgeStrategy"
2744matrix (Matrix
2745uid 369,0
2746text (MLText
2747uid 370,0
2748va (VaSet
2749font "Courier New,8,0"
2750)
2751xt "123000,45200,143000,46000"
2752st "DRS_TEMPERATURE = 51    ( integer )  "
2753)
2754header ""
2755)
2756elements [
2757(GiElement
2758name "DRS_TEMPERATURE"
2759type "integer"
2760value "51"
2761)
2762]
2763)
2764viewicon (ZoomableIcon
2765uid 371,0
2766sl 0
2767va (VaSet
2768vasetType 1
2769fg "49152,49152,49152"
2770)
2771xt "123250,54250,124750,55750"
2772iconName "VhdlFileViewIcon.png"
2773iconMaskName "VhdlFileViewIcon.msk"
2774ftype 10
2775)
2776ordering 1
2777viewiconposition 0
2778portVis (PortSigDisplay
2779sIVOD 1
2780)
2781archFileType "UNKNOWN"
2782)
2783*76 (Net
2784uid 372,0
2785decl (Decl
2786n "sensor_cs"
2787t "std_logic_vector"
2788b "(3 DOWNTO 0)"
2789o 6
2790suid 6,0
2791)
2792declText (MLText
2793uid 373,0
2794va (VaSet
2795font "Courier New,8,0"
2796)
2797xt "-90000,51800,-58500,52600"
2798st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
2799)
2800)
2801*77 (Net
2802uid 378,0
2803decl (Decl
2804n "sclk"
2805t "std_logic"
2806o 7
2807suid 7,0
2808)
2809declText (MLText
2810uid 379,0
2811va (VaSet
2812font "Courier New,8,0"
2813)
2814xt "-90000,51000,-68000,51800"
2815st "SIGNAL sclk                  : std_logic"
2816)
2817)
2818*78 (Net
2819uid 384,0
2820decl (Decl
2821n "sio"
2822t "std_logic"
2823preAdd 0
2824posAdd 0
2825o 8
2826suid 8,0
2827)
2828declText (MLText
2829uid 385,0
2830va (VaSet
2831font "Courier New,8,0"
2832)
2833xt "-90000,52600,-68000,53400"
2834st "SIGNAL sio                   : std_logic"
2835)
2836)
2837*79 (SaComponent
2838uid 414,0
2839optionalChildren [
2840*80 (CptPort
2841uid 410,0
2842ps "OnEdgeStrategy"
2843shape (Triangle
2844uid 411,0
2845ro 90
2846va (VaSet
2847vasetType 1
2848fg "0,65535,0"
2849)
2850xt "58000,31625,58750,32375"
2851)
2852tg (CPTG
2853uid 412,0
2854ps "CptPortTextPlaceStrategy"
2855stg "RightVerticalLayoutStrategy"
2856f (Text
2857uid 413,0
2858va (VaSet
2859)
2860xt "54200,31500,57000,32500"
2861st "trigger"
2862ju 2
2863blo "57000,32300"
2864)
2865)
2866thePort (LogicalPort
2867m 1
2868decl (Decl
2869n "trigger"
2870t "std_logic"
2871preAdd 0
2872posAdd 0
2873o 1
2874suid 1,0
2875)
2876)
2877)
2878]
2879shape (Rectangle
2880uid 415,0
2881va (VaSet
2882vasetType 1
2883fg "0,49152,49152"
2884lineColor "0,0,50000"
2885lineWidth 2
2886)
2887xt "50000,30000,58000,36000"
2888)
2889oxt "19000,4000,29000,14000"
2890ttg (MlTextGroup
2891uid 416,0
2892ps "CenterOffsetStrategy"
2893stg "VerticalLayoutStrategy"
2894textVec [
2895*81 (Text
2896uid 417,0
2897va (VaSet
2898font "Arial,8,1"
2899)
2900xt "50200,36000,57900,37000"
2901st "FACT_FAD_TB_lib"
2902blo "50200,36800"
2903tm "BdLibraryNameMgr"
2904)
2905*82 (Text
2906uid 418,0
2907va (VaSet
2908font "Arial,8,1"
2909)
2910xt "50200,37000,57500,38000"
2911st "trigger_generator"
2912blo "50200,37800"
2913tm "CptNameMgr"
2914)
2915*83 (Text
2916uid 419,0
2917va (VaSet
2918font "Arial,8,1"
2919)
2920xt "50200,38000,57400,39000"
2921st "I_mainTB_trigger"
2922blo "50200,38800"
2923tm "InstanceNameMgr"
2924)
2925]
2926)
2927ga (GenericAssociation
2928uid 420,0
2929ps "EdgeToEdgeStrategy"
2930matrix (Matrix
2931uid 421,0
2932text (MLText
2933uid 422,0
2934va (VaSet
2935font "Courier New,8,0"
2936)
2937xt "50000,28400,68500,30000"
2938st "TRIGGER_RATE = 1 ms     ( time ) 
2939PULSE_WIDTH  = 20 ns    ( time )  "
2940)
2941header ""
2942)
2943elements [
2944(GiElement
2945name "TRIGGER_RATE"
2946type "time"
2947value "1 ms"
2948)
2949(GiElement
2950name "PULSE_WIDTH"
2951type "time"
2952value "20 ns"
2953)
2954]
2955)
2956viewicon (ZoomableIcon
2957uid 423,0
2958sl 0
2959va (VaSet
2960vasetType 1
2961fg "49152,49152,49152"
2962)
2963xt "50250,34250,51750,35750"
2964iconName "VhdlFileViewIcon.png"
2965iconMaskName "VhdlFileViewIcon.msk"
2966ftype 10
2967)
2968ordering 1
2969viewiconposition 0
2970portVis (PortSigDisplay
2971sIVOD 1
2972)
2973archFileType "UNKNOWN"
2974)
2975*84 (Net
2976uid 424,0
2977decl (Decl
2978n "trigger"
2979t "std_logic"
2980preAdd 0
2981posAdd 0
2982o 9
2983suid 9,0
2984)
2985declText (MLText
2986uid 425,0
2987va (VaSet
2988font "Courier New,8,0"
2989)
2990xt "-90000,53400,-68000,54200"
2991st "SIGNAL trigger               : std_logic"
2992)
2993)
2994*85 (HdlText
2995uid 430,0
2996optionalChildren [
2997*86 (EmbeddedText
2998uid 436,0
2999commentText (CommentText
3000uid 437,0
3001ps "CenterOffsetStrategy"
3002shape (Rectangle
3003uid 438,0
3004va (VaSet
3005vasetType 1
3006fg "65535,65535,65535"
3007lineColor "0,0,32768"
3008lineWidth 2
3009)
3010xt "50000,45000,60000,49000"
3011)
3012oxt "0,0,18000,5000"
3013text (MLText
3014uid 439,0
3015va (VaSet
3016)
3017xt "50200,45200,60200,48200"
3018st "
3019-- eb_ID 1: hard-wired IDs
3020board_id <= \"0101\";
3021crate_id <= \"01\";
3022
3023"
3024tm "HdlTextMgr"
3025wrapOption 3
3026visibleHeight 4000
3027visibleWidth 10000
3028)
3029)
3030)
3031]
3032shape (Rectangle
3033uid 431,0
3034va (VaSet
3035vasetType 1
3036fg "65535,65535,37120"
3037lineColor "0,0,32768"
3038lineWidth 2
3039)
3040xt "50000,40000,58000,45000"
3041)
3042oxt "0,0,8000,10000"
3043ttg (MlTextGroup
3044uid 432,0
3045ps "CenterOffsetStrategy"
3046stg "VerticalLayoutStrategy"
3047textVec [
3048*87 (Text
3049uid 433,0
3050va (VaSet
3051font "Arial,8,1"
3052)
3053xt "51150,41000,57350,42000"
3054st "eb_mainTB_ID"
3055blo "51150,41800"
3056tm "HdlTextNameMgr"
3057)
3058*88 (Text
3059uid 434,0
3060va (VaSet
3061font "Arial,8,1"
3062)
3063xt "51150,42000,51950,43000"
3064st "1"
3065blo "51150,42800"
3066tm "HdlTextNumberMgr"
3067)
3068]
3069)
3070viewicon (ZoomableIcon
3071uid 435,0
3072sl 0
3073va (VaSet
3074vasetType 1
3075fg "49152,49152,49152"
3076)
3077xt "50250,43250,51750,44750"
3078iconName "TextFile.png"
3079iconMaskName "TextFile.msk"
3080ftype 21
3081)
3082viewiconposition 0
3083)
3084*89 (Net
3085uid 440,0
3086decl (Decl
3087n "board_id"
3088t "std_logic_vector"
3089b "(3 downto 0)"
3090preAdd 0
3091posAdd 0
3092o 10
3093suid 10,0
3094)
3095declText (MLText
3096uid 441,0
3097va (VaSet
3098font "Courier New,8,0"
3099)
3100xt "-90000,40600,-58500,41400"
3101st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
3102)
3103)
3104*90 (Net
3105uid 448,0
3106decl (Decl
3107n "crate_id"
3108t "std_logic_vector"
3109b "(1 downto 0)"
3110o 11
3111suid 11,0
3112)
3113declText (MLText
3114uid 449,0
3115va (VaSet
3116font "Courier New,8,0"
3117)
3118xt "-90000,43000,-58500,43800"
3119st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
3120)
3121)
3122*91 (SaComponent
3123uid 508,0
3124optionalChildren [
3125*92 (CptPort
3126uid 489,0
3127ps "OnEdgeStrategy"
3128shape (Triangle
3129uid 490,0
3130ro 90
3131va (VaSet
3132vasetType 1
3133fg "0,65535,0"
3134)
3135xt "29250,52625,30000,53375"
3136)
3137tg (CPTG
3138uid 491,0
3139ps "CptPortTextPlaceStrategy"
3140stg "VerticalLayoutStrategy"
3141f (Text
3142uid 492,0
3143va (VaSet
3144)
3145xt "31000,52500,32300,53500"
3146st "clk"
3147blo "31000,53300"
3148)
3149)
3150thePort (LogicalPort
3151decl (Decl
3152n "clk"
3153t "STD_LOGIC"
3154preAdd 0
3155posAdd 0
3156o 1
3157suid 1,0
3158)
3159)
3160)
3161*93 (CptPort
3162uid 493,0
3163ps "OnEdgeStrategy"
3164shape (Triangle
3165uid 494,0
3166ro 90
3167va (VaSet
3168vasetType 1
3169fg "0,65535,0"
3170)
3171xt "40000,54625,40750,55375"
3172)
3173tg (CPTG
3174uid 495,0
3175ps "CptPortTextPlaceStrategy"
3176stg "RightVerticalLayoutStrategy"
3177f (Text
3178uid 496,0
3179va (VaSet
3180)
3181xt "34200,54500,39000,55500"
3182st "data : (11:0)"
3183ju 2
3184blo "39000,55300"
3185)
3186)
3187thePort (LogicalPort
3188m 1
3189decl (Decl
3190n "data"
3191t "STD_LOGIC_VECTOR"
3192b "(11 DOWNTO 0)"
3193preAdd 0
3194posAdd 0
3195o 2
3196suid 2,0
3197)
3198)
3199)
3200*94 (CptPort
3201uid 497,0
3202ps "OnEdgeStrategy"
3203shape (Triangle
3204uid 498,0
3205ro 90
3206va (VaSet
3207vasetType 1
3208fg "0,65535,0"
3209)
3210xt "40000,52625,40750,53375"
3211)
3212tg (CPTG
3213uid 499,0
3214ps "CptPortTextPlaceStrategy"
3215stg "RightVerticalLayoutStrategy"
3216f (Text
3217uid 500,0
3218va (VaSet
3219)
3220xt "37700,52500,39000,53500"
3221st "otr"
3222ju 2
3223blo "39000,53300"
3224)
3225)
3226thePort (LogicalPort
3227m 1
3228decl (Decl
3229n "otr"
3230t "STD_LOGIC"
3231preAdd 0
3232posAdd 0
3233o 3
3234suid 3,0
3235)
3236)
3237)
3238*95 (CptPort
3239uid 501,0
3240ps "OnEdgeStrategy"
3241shape (Triangle
3242uid 502,0
3243ro 270
3244va (VaSet
3245vasetType 1
3246fg "0,65535,0"
3247)
3248xt "40000,53625,40750,54375"
3249)
3250tg (CPTG
3251uid 503,0
3252ps "CptPortTextPlaceStrategy"
3253stg "RightVerticalLayoutStrategy"
3254f (Text
3255uid 504,0
3256va (VaSet
3257)
3258xt "37400,53500,39000,54500"
3259st "oeb"
3260ju 2
3261blo "39000,54300"
3262)
3263)
3264thePort (LogicalPort
3265decl (Decl
3266n "oeb"
3267t "STD_LOGIC"
3268preAdd 0
3269posAdd 0
3270o 4
3271suid 4,0
3272)
3273)
3274)
3275]
3276shape (Rectangle
3277uid 509,0
3278va (VaSet
3279vasetType 1
3280fg "0,49152,49152"
3281lineColor "0,0,50000"
3282lineWidth 2
3283)
3284xt "30000,51000,40000,58000"
3285)
3286oxt "29000,7000,39000,17000"
3287ttg (MlTextGroup
3288uid 510,0
3289ps "CenterOffsetStrategy"
3290stg "VerticalLayoutStrategy"
3291textVec [
3292*96 (Text
3293uid 511,0
3294va (VaSet
3295font "Arial,8,1"
3296)
3297xt "30200,58000,37900,59000"
3298st "FACT_FAD_TB_lib"
3299blo "30200,58800"
3300tm "BdLibraryNameMgr"
3301)
3302*97 (Text
3303uid 512,0
3304va (VaSet
3305font "Arial,8,1"
3306)
3307xt "30200,59000,36000,60000"
3308st "adc_emulator"
3309blo "30200,59800"
3310tm "CptNameMgr"
3311)
3312*98 (Text
3313uid 513,0
3314va (VaSet
3315font "Arial,8,1"
3316)
3317xt "30200,60000,36200,61000"
3318st "I_mainTB_adc"
3319blo "30200,60800"
3320tm "InstanceNameMgr"
3321)
3322]
3323)
3324ga (GenericAssociation
3325uid 514,0
3326ps "EdgeToEdgeStrategy"
3327matrix (Matrix
3328uid 515,0
3329text (MLText
3330uid 516,0
3331va (VaSet
3332font "Courier New,8,0"
3333)
3334xt "30000,50200,65500,51000"
3335st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\"    ( string )  "
3336)
3337header ""
3338)
3339elements [
3340(GiElement
3341name "INPUT_FILE"
3342type "string"
3343value "\"../memory_files/analog_input_ch0.txt\""
3344)
3345]
3346)
3347viewicon (ZoomableIcon
3348uid 517,0
3349sl 0
3350va (VaSet
3351vasetType 1
3352fg "49152,49152,49152"
3353)
3354xt "30250,56250,31750,57750"
3355iconName "VhdlFileViewIcon.png"
3356iconMaskName "VhdlFileViewIcon.msk"
3357ftype 10
3358)
3359ordering 1
3360viewiconposition 0
3361portVis (PortSigDisplay
3362sIVOD 1
3363)
3364archFileType "UNKNOWN"
3365)
3366*99 (HdlText
3367uid 518,0
3368optionalChildren [
3369*100 (EmbeddedText
3370uid 524,0
3371commentText (CommentText
3372uid 525,0
3373ps "CenterOffsetStrategy"
3374shape (Rectangle
3375uid 526,0
3376va (VaSet
3377vasetType 1
3378fg "65535,65535,65535"
3379lineColor "0,0,32768"
3380lineWidth 2
3381)
3382xt "50000,57000,62000,67000"
3383)
3384oxt "0,0,18000,5000"
3385text (MLText
3386uid 527,0
3387va (VaSet
3388)
3389xt "50200,57200,62100,66200"
3390st "
3391-- eb_adc 2: ADC routing
3392adc_data_array(0) <= adc_data;
3393adc_data_array(1) <= adc_data;
3394adc_data_array(2) <= adc_data;
3395adc_data_array(3) <= adc_data;
3396adc_otr_array(0) <= adc_otr;
3397adc_otr_array(1) <= adc_otr;
3398adc_otr_array(2) <= adc_otr;
3399adc_otr_array(3) <= adc_otr;
3400
3401"
3402tm "HdlTextMgr"
3403wrapOption 3
3404visibleHeight 10000
3405visibleWidth 12000
3406)
3407)
3408)
3409]
3410shape (Rectangle
3411uid 519,0
3412va (VaSet
3413vasetType 1
3414fg "65535,65535,37120"
3415lineColor "0,0,32768"
3416lineWidth 2
3417)
3418xt "50000,51000,58000,57000"
3419)
3420oxt "0,0,8000,10000"
3421ttg (MlTextGroup
3422uid 520,0
3423ps "CenterOffsetStrategy"
3424stg "VerticalLayoutStrategy"
3425textVec [
3426*101 (Text
3427uid 521,0
3428va (VaSet
3429font "Arial,8,1"
3430)
3431xt "51150,52000,57850,53000"
3432st "eb_mainTB_adc"
3433blo "51150,52800"
3434tm "HdlTextNameMgr"
3435)
3436*102 (Text
3437uid 522,0
3438va (VaSet
3439font "Arial,8,1"
3440)
3441xt "51150,53000,51950,54000"
3442st "2"
3443blo "51150,53800"
3444tm "HdlTextNumberMgr"
3445)
3446]
3447)
3448viewicon (ZoomableIcon
3449uid 523,0
3450sl 0
3451va (VaSet
3452vasetType 1
3453fg "49152,49152,49152"
3454)
3455xt "50250,55250,51750,56750"
3456iconName "TextFile.png"
3457iconMaskName "TextFile.msk"
3458ftype 21
3459)
3460viewiconposition 0
3461)
3462*103 (Net
3463uid 528,0
3464decl (Decl
3465n "adc_otr_array"
3466t "std_logic_vector"
3467b "(3 DOWNTO 0)"
3468o 12
3469suid 12,0
3470)
3471declText (MLText
3472uid 529,0
3473va (VaSet
3474font "Courier New,8,0"
3475)
3476xt "-90000,37400,-58500,38200"
3477st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)"
3478)
3479)
3480*104 (Net
3481uid 536,0
3482decl (Decl
3483n "adc_data_array"
3484t "adc_data_array_type"
3485o 13
3486suid 13,0
3487)
3488declText (MLText
3489uid 537,0
3490va (VaSet
3491font "Courier New,8,0"
3492)
3493xt "-90000,35000,-63000,35800"
3494st "SIGNAL adc_data_array        : adc_data_array_type"
3495)
3496)
3497*105 (Net
3498uid 544,0
3499decl (Decl
3500n "adc_oeb"
3501t "std_logic"
3502preAdd 0
3503posAdd 0
3504o 14
3505suid 14,0
3506)
3507declText (MLText
3508uid 545,0
3509va (VaSet
3510font "Courier New,8,0"
3511)
3512xt "-90000,35800,-68000,36600"
3513st "SIGNAL adc_oeb               : std_logic"
3514)
3515)
3516*106 (Net
3517uid 560,0
3518decl (Decl
3519n "adc_otr"
3520t "STD_LOGIC"
3521preAdd 0
3522posAdd 0
3523o 16
3524suid 16,0
3525)
3526declText (MLText
3527uid 561,0
3528va (VaSet
3529font "Courier New,8,0"
3530)
3531xt "-90000,36600,-68000,37400"
3532st "SIGNAL adc_otr               : STD_LOGIC"
3533)
3534)
3535*107 (Net
3536uid 568,0
3537decl (Decl
3538n "adc_data"
3539t "std_logic_vector"
3540b "(11 DOWNTO 0)"
3541preAdd 0
3542posAdd 0
3543o 17
3544suid 17,0
3545)
3546declText (MLText
3547uid 569,0
3548va (VaSet
3549font "Courier New,8,0"
3550)
3551xt "-90000,34200,-58000,35000"
3552st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)"
3553)
3554)
3555*108 (Net
3556uid 767,0
3557decl (Decl
3558n "wiz_reset"
3559t "std_logic"
3560o 21
3561suid 23,0
3562i "'1'"
3563)
3564declText (MLText
3565uid 768,0
3566va (VaSet
3567font "Courier New,8,0"
3568)
3569xt "-90000,58200,-55000,59000"
3570st "SIGNAL wiz_reset             : std_logic                    := '1'"
3571)
3572)
3573*109 (Net
3574uid 775,0
3575decl (Decl
3576n "led"
3577t "std_logic_vector"
3578b "(7 DOWNTO 0)"
3579posAdd 0
3580o 22
3581suid 24,0
3582i "(OTHERS => '0')"
3583)
3584declText (MLText
3585uid 776,0
3586va (VaSet
3587font "Courier New,8,0"
3588)
3589xt "-90000,47800,-49000,48600"
3590st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
3591)
3592)
3593*110 (Net
3594uid 783,0
3595decl (Decl
3596n "wiz_cs"
3597t "std_logic"
3598o 23
3599suid 25,0
3600i "'1'"
3601)
3602declText (MLText
3603uid 784,0
3604va (VaSet
3605font "Courier New,8,0"
3606)
3607xt "-90000,55000,-55000,55800"
3608st "SIGNAL wiz_cs                : std_logic                    := '1'"
3609)
3610)
3611*111 (Net
3612uid 791,0
3613decl (Decl
3614n "wiz_int"
3615t "std_logic"
3616o 24
3617suid 26,0
3618)
3619declText (MLText
3620uid 792,0
3621va (VaSet
3622font "Courier New,8,0"
3623)
3624xt "-90000,56600,-68000,57400"
3625st "SIGNAL wiz_int               : std_logic"
3626)
3627)
3628*112 (Net
3629uid 799,0
3630decl (Decl
3631n "dac_cs"
3632t "std_logic"
3633o 25
3634suid 27,0
3635)
3636declText (MLText
3637uid 800,0
3638va (VaSet
3639font "Courier New,8,0"
3640)
3641xt "-90000,43800,-68000,44600"
3642st "SIGNAL dac_cs                : std_logic"
3643)
3644)
3645*113 (Net
3646uid 807,0
3647decl (Decl
3648n "mosi"
3649t "std_logic"
3650o 26
3651suid 28,0
3652i "'0'"
3653)
3654declText (MLText
3655uid 808,0
3656va (VaSet
3657font "Courier New,8,0"
3658)
3659xt "-90000,48600,-55000,49400"
3660st "SIGNAL mosi                  : std_logic                    := '0'"
3661)
3662)
3663*114 (Net
3664uid 815,0
3665decl (Decl
3666n "denable"
3667t "std_logic"
3668eolc "-- default domino wave off"
3669posAdd 0
3670o 27
3671suid 29,0
3672i "'0'"
3673)
3674declText (MLText
3675uid 816,0
3676va (VaSet
3677font "Courier New,8,0"
3678)
3679xt "-90000,44600,-41500,45400"
3680st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off"
3681)
3682)
3683*115 (Net
3684uid 823,0
3685decl (Decl
3686n "CLK_25_PS"
3687t "std_logic"
3688o 28
3689suid 30,0
3690)
3691declText (MLText
3692uid 824,0
3693va (VaSet
3694font "Courier New,8,0"
3695)
3696xt "-90000,25400,-68000,26200"
3697st "SIGNAL CLK_25_PS             : std_logic"
3698)
3699)
3700*116 (Net
3701uid 831,0
3702decl (Decl
3703n "CLK_50"
3704t "std_logic"
3705o 29
3706suid 31,0
3707)
3708declText (MLText
3709uid 832,0
3710va (VaSet
3711font "Courier New,8,0"
3712)
3713xt "-90000,26200,-68000,27000"
3714st "SIGNAL CLK_50                : std_logic"
3715)
3716)
3717*117 (Net
3718uid 839,0
3719decl (Decl
3720n "drs_channel_id"
3721t "std_logic_vector"
3722b "(3 downto 0)"
3723o 30
3724suid 32,0
3725i "(others => '0')"
3726)
3727declText (MLText
3728uid 840,0
3729va (VaSet
3730font "Courier New,8,0"
3731)
3732xt "-90000,45400,-49000,46200"
3733st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')"
3734)
3735)
3736*118 (Net
3737uid 847,0
3738decl (Decl
3739n "drs_dwrite"
3740t "std_logic"
3741o 31
3742suid 33,0
3743i "'1'"
3744)
3745declText (MLText
3746uid 848,0
3747va (VaSet
3748font "Courier New,8,0"
3749)
3750xt "-90000,46200,-55000,47000"
3751st "SIGNAL drs_dwrite            : std_logic                    := '1'"
3752)
3753)
3754*119 (Net
3755uid 855,0
3756decl (Decl
3757n "RSRLOAD"
3758t "std_logic"
3759o 32
3760suid 34,0
3761i "'0'"
3762)
3763declText (MLText
3764uid 856,0
3765va (VaSet
3766font "Courier New,8,0"
3767)
3768xt "-90000,28600,-55000,29400"
3769st "SIGNAL RSRLOAD               : std_logic                    := '0'"
3770)
3771)
3772*120 (Net
3773uid 863,0
3774decl (Decl
3775n "SRCLK"
3776t "std_logic"
3777o 33
3778suid 35,0
3779i "'0'"
3780)
3781declText (MLText
3782uid 864,0
3783va (VaSet
3784font "Courier New,8,0"
3785)
3786xt "-90000,29400,-55000,30200"
3787st "SIGNAL SRCLK                 : std_logic                    := '0'"
3788)
3789)
3790*121 (Net
3791uid 871,0
3792decl (Decl
3793n "SROUT_in_0"
3794t "std_logic"
3795o 30
3796suid 36,0
3797)
3798declText (MLText
3799uid 872,0
3800va (VaSet
3801font "Courier New,8,0"
3802)
3803xt "-90000,31000,-68000,31800"
3804st "SIGNAL SROUT_in_0            : std_logic"
3805)
3806)
3807*122 (Net
3808uid 879,0
3809decl (Decl
3810n "SROUT_in_1"
3811t "std_logic"
3812o 31
3813suid 37,0
3814)
3815declText (MLText
3816uid 880,0
3817va (VaSet
3818font "Courier New,8,0"
3819)
3820xt "-90000,31800,-68000,32600"
3821st "SIGNAL SROUT_in_1            : std_logic"
3822)
3823)
3824*123 (Net
3825uid 887,0
3826decl (Decl
3827n "SROUT_in_2"
3828t "std_logic"
3829o 32
3830suid 38,0
3831)
3832declText (MLText
3833uid 888,0
3834va (VaSet
3835font "Courier New,8,0"
3836)
3837xt "-90000,32600,-68000,33400"
3838st "SIGNAL SROUT_in_2            : std_logic"
3839)
3840)
3841*124 (Net
3842uid 895,0
3843decl (Decl
3844n "SROUT_in_3"
3845t "std_logic"
3846o 33
3847suid 39,0
3848)
3849declText (MLText
3850uid 896,0
3851va (VaSet
3852font "Courier New,8,0"
3853)
3854xt "-90000,33400,-68000,34200"
3855st "SIGNAL SROUT_in_3            : std_logic"
3856)
3857)
3858*125 (Net
3859uid 1435,0
3860decl (Decl
3861n "SRIN_out"
3862t "std_logic"
3863o 34
3864suid 40,0
3865i "'0'"
3866)
3867declText (MLText
3868uid 1436,0
3869va (VaSet
3870font "Courier New,8,0"
3871)
3872xt "-90000,30200,-55000,31000"
3873st "SIGNAL SRIN_out              : std_logic                    := '0'"
3874)
3875)
3876*126 (Net
3877uid 1443,0
3878decl (Decl
3879n "amber"
3880t "std_logic"
3881o 35
3882suid 41,0
3883)
3884declText (MLText
3885uid 1444,0
3886va (VaSet
3887font "Courier New,8,0"
3888)
3889xt "-90000,39800,-68000,40600"
3890st "SIGNAL amber                 : std_logic"
3891)
3892)
3893*127 (Net
3894uid 1451,0
3895decl (Decl
3896n "red"
3897t "std_logic"
3898o 36
3899suid 42,0
3900)
3901declText (MLText
3902uid 1452,0
3903va (VaSet
3904font "Courier New,8,0"
3905)
3906xt "-90000,50200,-68000,51000"
3907st "SIGNAL red                   : std_logic"
3908)
3909)
3910*128 (Net
3911uid 1459,0
3912decl (Decl
3913n "green"
3914t "std_logic"
3915o 37
3916suid 43,0
3917)
3918declText (MLText
3919uid 1460,0
3920va (VaSet
3921font "Courier New,8,0"
3922)
3923xt "-90000,47000,-68000,47800"
3924st "SIGNAL green                 : std_logic"
3925)
3926)
3927*129 (Net
3928uid 1467,0
3929decl (Decl
3930n "counter_result"
3931t "std_logic_vector"
3932b "(11 DOWNTO 0)"
3933o 38
3934suid 44,0
3935)
3936declText (MLText
3937uid 1468,0
3938va (VaSet
3939font "Courier New,8,0"
3940)
3941xt "-90000,42200,-58000,43000"
3942st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
3943)
3944)
3945*130 (Net
3946uid 1475,0
3947decl (Decl
3948n "alarm_refclk_too_low"
3949t "std_logic"
3950posAdd 0
3951o 39
3952suid 45,0
3953)
3954declText (MLText
3955uid 1476,0
3956va (VaSet
3957font "Courier New,8,0"
3958)
3959xt "-90000,39000,-68000,39800"
3960st "SIGNAL alarm_refclk_too_low  : std_logic"
3961)
3962)
3963*131 (Net
3964uid 1483,0
3965decl (Decl
3966n "alarm_refclk_too_high"
3967t "std_logic"
3968o 40
3969suid 46,0
3970)
3971declText (MLText
3972uid 1484,0
3973va (VaSet
3974font "Courier New,8,0"
3975)
3976xt "-90000,38200,-68000,39000"
3977st "SIGNAL alarm_refclk_too_high : std_logic"
3978)
3979)
3980*132 (HdlText
3981uid 1491,0
3982optionalChildren [
3983*133 (EmbeddedText
3984uid 1497,0
3985commentText (CommentText
3986uid 1498,0
3987ps "CenterOffsetStrategy"
3988shape (Rectangle
3989uid 1499,0
3990va (VaSet
3991vasetType 1
3992fg "65535,65535,65535"
3993lineColor "0,0,32768"
3994lineWidth 2
3995)
3996xt "27000,72000,41000,77000"
3997)
3998oxt "0,0,18000,5000"
3999text (MLText
4000uid 1500,0
4001va (VaSet
4002)
4003xt "27200,72200,39400,77200"
4004st "
4005
4006D_T_in(1 downto 0) <= \"00\";
4007plllock_in(3 downto 0) <= \"1111\";
4008SROUT_in_0 <= '1';
4009SROUT_in_1 <= '0';
4010SROUT_in_2 <= '1';
4011SROUT_in_3 <= '0';
4012
4013"
4014tm "HdlTextMgr"
4015wrapOption 3
4016visibleHeight 5000
4017visibleWidth 14000
4018)
4019)
4020)
4021]
4022shape (Rectangle
4023uid 1492,0
4024va (VaSet
4025vasetType 1
4026fg "65535,65535,37120"
4027lineColor "0,0,32768"
4028lineWidth 2
4029)
4030xt "27000,69000,35000,72000"
4031)
4032oxt "0,0,8000,10000"
4033ttg (MlTextGroup
4034uid 1493,0
4035ps "CenterOffsetStrategy"
4036stg "VerticalLayoutStrategy"
4037textVec [
4038*134 (Text
4039uid 1494,0
4040va (VaSet
4041font "Arial,8,1"
4042)
4043xt "28150,69000,35250,70000"
4044st "eb_mainTB_adc1"
4045blo "28150,69800"
4046tm "HdlTextNameMgr"
4047)
4048*135 (Text
4049uid 1495,0
4050va (VaSet
4051font "Arial,8,1"
4052)
4053xt "28150,70000,28950,71000"
4054st "3"
4055blo "28150,70800"
4056tm "HdlTextNumberMgr"
4057)
4058]
4059)
4060viewicon (ZoomableIcon
4061uid 1496,0
4062sl 0
4063va (VaSet
4064vasetType 1
4065fg "49152,49152,49152"
4066)
4067xt "27250,70250,28750,71750"
4068iconName "TextFile.png"
4069iconMaskName "TextFile.msk"
4070ftype 21
4071)
4072viewiconposition 0
4073)
4074*136 (Net
4075uid 1501,0
4076decl (Decl
4077n "D_T_in"
4078t "std_logic_vector"
4079b "(1 DOWNTO 0)"
4080o 41
4081suid 47,0
4082)
4083declText (MLText
4084uid 1502,0
4085va (VaSet
4086font "Courier New,8,0"
4087)
4088xt "-90000,27000,-58500,27800"
4089st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
4090)
4091)
4092*137 (SaComponent
4093uid 1509,0
4094optionalChildren [
4095*138 (CptPort
4096uid 1519,0
4097ps "OnEdgeStrategy"
4098shape (Triangle
4099uid 1520,0
4100ro 90
4101va (VaSet
4102vasetType 1
4103fg "0,65535,0"
4104)
4105xt "66000,78625,66750,79375"
4106)
4107tg (CPTG
4108uid 1521,0
4109ps "CptPortTextPlaceStrategy"
4110stg "RightVerticalLayoutStrategy"
4111f (Text
4112uid 1522,0
4113va (VaSet
4114)
4115xt "63700,78500,65000,79500"
4116st "clk"
4117ju 2
4118blo "65000,79300"
4119)
4120)
4121thePort (LogicalPort
4122m 1
4123decl (Decl
4124n "clk"
4125t "STD_LOGIC"
4126o 1
4127i "'0'"
4128)
4129)
4130)
4131*139 (CptPort
4132uid 1523,0
4133ps "OnEdgeStrategy"
4134shape (Triangle
4135uid 1524,0
4136ro 90
4137va (VaSet
4138vasetType 1
4139fg "0,65535,0"
4140)
4141xt "66000,79625,66750,80375"
4142)
4143tg (CPTG
4144uid 1525,0
4145ps "CptPortTextPlaceStrategy"
4146stg "RightVerticalLayoutStrategy"
4147f (Text
4148uid 1526,0
4149va (VaSet
4150)
4151xt "63700,79500,65000,80500"
4152st "rst"
4153ju 2
4154blo "65000,80300"
4155)
4156)
4157thePort (LogicalPort
4158m 1
4159decl (Decl
4160n "rst"
4161t "STD_LOGIC"
4162o 2
4163i "'0'"
4164)
4165)
4166)
4167]
4168shape (Rectangle
4169uid 1510,0
4170va (VaSet
4171vasetType 1
4172fg "0,49152,49152"
4173lineColor "0,0,50000"
4174lineWidth 2
4175)
4176xt "55000,77000,66000,82000"
4177)
4178oxt "0,0,8000,10000"
4179ttg (MlTextGroup
4180uid 1511,0
4181ps "CenterOffsetStrategy"
4182stg "VerticalLayoutStrategy"
4183textVec [
4184*140 (Text
4185uid 1512,0
4186va (VaSet
4187font "Arial,8,1"
4188)
4189xt "56150,78000,63850,79000"
4190st "FACT_FAD_TB_lib"
4191blo "56150,78800"
4192tm "BdLibraryNameMgr"
4193)
4194*141 (Text
4195uid 1513,0
4196va (VaSet
4197font "Arial,8,1"
4198)
4199xt "56150,79000,62850,80000"
4200st "clock_generator"
4201blo "56150,79800"
4202tm "CptNameMgr"
4203)
4204*142 (Text
4205uid 1514,0
4206va (VaSet
4207font "Arial,8,1"
4208)
4209xt "56150,80000,63150,81000"
4210st "I_mainTB_clock1"
4211blo "56150,80800"
4212tm "InstanceNameMgr"
4213)
4214]
4215)
4216ga (GenericAssociation
4217uid 1515,0
4218ps "EdgeToEdgeStrategy"
4219matrix (Matrix
4220uid 1516,0
4221text (MLText
4222uid 1517,0
4223va (VaSet
4224font "Courier New,8,0"
4225)
4226xt "55000,82400,73000,84000"
4227st "clock_period = 1 us    ( time ) 
4228reset_time   = 1 us    ( time )  "
4229)
4230header ""
4231)
4232elements [
4233(GiElement
4234name "clock_period"
4235type "time"
4236value "1 us"
4237)
4238(GiElement
4239name "reset_time"
4240type "time"
4241value "1 us"
4242)
4243]
4244)
4245viewicon (ZoomableIcon
4246uid 1518,0
4247sl 0
4248va (VaSet
4249vasetType 1
4250fg "49152,49152,49152"
4251)
4252xt "55250,80250,56750,81750"
4253iconName "VhdlFileViewIcon.png"
4254iconMaskName "VhdlFileViewIcon.msk"
4255ftype 10
4256)
4257ordering 1
4258viewiconposition 0
4259portVis (PortSigDisplay
4260)
4261archFileType "UNKNOWN"
4262)
4263*143 (Net
4264uid 1559,0
4265decl (Decl
4266n "plllock_in"
4267t "std_logic_vector"
4268b "(3 DOWNTO 0)"
4269eolc "-- high level, if dominowave is running and DRS PLL locked"
4270o 43
4271suid 49,0
4272)
4273declText (MLText
4274uid 1560,0
4275va (VaSet
4276font "Courier New,8,0"
4277)
4278xt "-90000,49400,-29000,50200"
4279st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
4280)
4281)
4282*144 (Net
4283uid 1682,0
4284lang 2
4285decl (Decl
4286n "ADC_CLK"
4287t "std_logic"
4288o 44
4289suid 50,0
4290)
4291declText (MLText
4292uid 1683,0
4293va (VaSet
4294font "Courier New,8,0"
4295)
4296xt "-90000,24600,-68000,25400"
4297st "SIGNAL ADC_CLK               : std_logic"
4298)
4299)
4300*145 (Net
4301uid 2001,0
4302decl (Decl
4303n "REF_CLK"
4304t "STD_LOGIC"
4305o 42
4306suid 51,0
4307i "'0'"
4308)
4309declText (MLText
4310uid 2002,0
4311va (VaSet
4312font "Courier New,8,0"
4313)
4314xt "-90000,27800,-55000,28600"
4315st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'"
4316)
4317)
4318*146 (SaComponent
4319uid 2336,0
4320optionalChildren [
4321*147 (CptPort
4322uid 2315,0
4323ps "OnEdgeStrategy"
4324shape (Triangle
4325uid 2316,0
4326ro 90
4327va (VaSet
4328vasetType 1
4329fg "0,65535,0"
4330)
4331xt "122250,20625,123000,21375"
4332)
4333tg (CPTG
4334uid 2317,0
4335ps "CptPortTextPlaceStrategy"
4336stg "VerticalLayoutStrategy"
4337f (Text
4338uid 2318,0
4339va (VaSet
4340)
4341xt "124000,20500,128500,21500"
4342st "addr : (9:0)"
4343blo "124000,21300"
4344)
4345)
4346thePort (LogicalPort
4347decl (Decl
4348n "addr"
4349t "std_logic_vector"
4350b "(9 DOWNTO 0)"
4351preAdd 0
4352posAdd 0
4353o 2
4354suid 1,0
4355)
4356)
4357)
4358*148 (CptPort
4359uid 2319,0
4360ps "OnEdgeStrategy"
4361shape (Diamond
4362uid 2320,0
4363ro 270
4364va (VaSet
4365vasetType 1
4366fg "0,65535,0"
4367)
4368xt "122250,21625,123000,22375"
4369)
4370tg (CPTG
4371uid 2321,0
4372ps "CptPortTextPlaceStrategy"
4373stg "VerticalLayoutStrategy"
4374f (Text
4375uid 2322,0
4376va (VaSet
4377)
4378xt "124000,21500,128800,22500"
4379st "data : (15:0)"
4380blo "124000,22300"
4381)
4382)
4383thePort (LogicalPort
4384m 2
4385decl (Decl
4386n "data"
4387t "std_logic_vector"
4388b "(15 DOWNTO 0)"
4389preAdd 0
4390posAdd 0
4391o 3
4392suid 2,0
4393)
4394)
4395)
4396*149 (CptPort
4397uid 2323,0
4398ps "OnEdgeStrategy"
4399shape (Triangle
4400uid 2324,0
4401ro 90
4402va (VaSet
4403vasetType 1
4404fg "0,65535,0"
4405)
4406xt "122250,24625,123000,25375"
4407)
4408tg (CPTG
4409uid 2325,0
4410ps "CptPortTextPlaceStrategy"
4411stg "VerticalLayoutStrategy"
4412f (Text
4413uid 2326,0
4414va (VaSet
4415)
4416xt "124000,24500,125100,25500"
4417st "rd"
4418blo "124000,25300"
4419)
4420)
4421thePort (LogicalPort
4422decl (Decl
4423n "rd"
4424t "std_logic"
4425preAdd 0
4426posAdd 0
4427o 4
4428suid 3,0
4429)
4430)
4431)
4432*150 (CptPort
4433uid 2327,0
4434ps "OnEdgeStrategy"
4435shape (Triangle
4436uid 2328,0
4437ro 90
4438va (VaSet
4439vasetType 1
4440fg "0,65535,0"
4441)
4442xt "122250,25625,123000,26375"
4443)
4444tg (CPTG
4445uid 2329,0
4446ps "CptPortTextPlaceStrategy"
4447stg "VerticalLayoutStrategy"
4448f (Text
4449uid 2330,0
4450va (VaSet
4451)
4452xt "124000,25500,125200,26500"
4453st "wr"
4454blo "124000,26300"
4455)
4456)
4457thePort (LogicalPort
4458decl (Decl
4459n "wr"
4460t "std_logic"
4461preAdd 0
4462posAdd 0
4463o 5
4464suid 4,0
4465)
4466)
4467)
4468*151 (CptPort
4469uid 2331,0
4470ps "OnEdgeStrategy"
4471shape (Triangle
4472uid 2332,0
4473ro 270
4474va (VaSet
4475vasetType 1
4476fg "0,65535,0"
4477)
4478xt "122250,26625,123000,27375"
4479)
4480tg (CPTG
4481uid 2333,0
4482ps "CptPortTextPlaceStrategy"
4483stg "VerticalLayoutStrategy"
4484f (Text
4485uid 2334,0
4486va (VaSet
4487)
4488xt "124000,26500,125200,27500"
4489st "int"
4490blo "124000,27300"
4491)
4492t (Text
4493uid 2335,0
4494va (VaSet
4495)
4496xt "124000,27500,125200,28500"
4497st "'1'"
4498blo "124000,28300"
4499)
4500)
4501thePort (LogicalPort
4502m 1
4503decl (Decl
4504n "int"
4505t "std_logic"
4506o 1
4507suid 5,0
4508i "'1'"
4509)
4510)
4511)
4512]
4513shape (Rectangle
4514uid 2337,0
4515va (VaSet
4516vasetType 1
4517fg "0,49152,49152"
4518lineColor "0,0,50000"
4519lineWidth 2
4520)
4521xt "123000,19000,133000,31000"
4522)
4523oxt "29000,0,39000,12000"
4524ttg (MlTextGroup
4525uid 2338,0
4526ps "CenterOffsetStrategy"
4527stg "VerticalLayoutStrategy"
4528textVec [
4529*152 (Text
4530uid 2339,0
4531va (VaSet
4532font "Arial,8,1"
4533)
4534xt "123200,31000,130900,32000"
4535st "FACT_FAD_TB_lib"
4536blo "123200,31800"
4537tm "BdLibraryNameMgr"
4538)
4539*153 (Text
4540uid 2340,0
4541va (VaSet
4542font "Arial,8,1"
4543)
4544xt "123200,32000,129800,33000"
4545st "w5300_emulator"
4546blo "123200,32800"
4547tm "CptNameMgr"
4548)
4549*154 (Text
4550uid 2341,0
4551va (VaSet
4552font "Arial,8,1"
4553)
4554xt "123200,33000,130000,34000"
4555st "I_mainTB_w5300"
4556blo "123200,33800"
4557tm "InstanceNameMgr"
4558)
4559]
4560)
4561ga (GenericAssociation
4562uid 2342,0
4563ps "EdgeToEdgeStrategy"
4564matrix (Matrix
4565uid 2343,0
4566text (MLText
4567uid 2344,0
4568va (VaSet
4569font "Courier New,8,0"
4570)
4571xt "123000,18000,123000,18000"
4572)
4573header ""
4574)
4575elements [
4576]
4577)
4578viewicon (ZoomableIcon
4579uid 2345,0
4580sl 0
4581va (VaSet
4582vasetType 1
4583fg "49152,49152,49152"
4584)
4585xt "123250,29250,124750,30750"
4586iconName "VhdlFileViewIcon.png"
4587iconMaskName "VhdlFileViewIcon.msk"
4588ftype 10
4589)
4590ordering 1
4591viewiconposition 0
4592portVis (PortSigDisplay
4593sIVOD 1
4594)
4595archFileType "UNKNOWN"
4596)
4597*155 (Wire
4598uid 286,0
4599shape (OrthoPolyLine
4600uid 287,0
4601va (VaSet
4602vasetType 3
4603)
4604xt "58750,21000,80250,21000"
4605pts [
4606"58750,21000"
4607"80250,21000"
4608]
4609)
4610start &59
4611end &27
4612sat 32
4613eat 32
4614st 0
4615sf 1
4616si 0
4617tg (WTG
4618uid 288,0
4619ps "ConnStartEndStrategy"
4620stg "STSignalDisplayStrategy"
4621f (Text
4622uid 289,0
4623va (VaSet
4624)
4625xt "71000,20000,72300,21000"
4626st "clk"
4627blo "71000,20800"
4628tm "WireNameMgr"
4629)
4630)
4631on &64
4632)
4633*156 (Wire
4634uid 318,0
4635shape (OrthoPolyLine
4636uid 319,0
4637va (VaSet
4638vasetType 3
4639lineWidth 2
4640)
4641xt "109750,21000,122250,21000"
4642pts [
4643"109750,21000"
4644"122250,21000"
4645]
4646)
4647start &19
4648end &147
4649sat 32
4650eat 32
4651sty 1
4652st 0
4653sf 1
4654si 0
4655tg (WTG
4656uid 320,0
4657ps "ConnStartEndStrategy"
4658stg "STSignalDisplayStrategy"
4659f (Text
4660uid 321,0
4661va (VaSet
4662)
4663xt "111000,20000,117000,21000"
4664st "wiz_addr : (9:0)"
4665blo "111000,20800"
4666tm "WireNameMgr"
4667)
4668)
4669on &65
4670)
4671*157 (Wire
4672uid 324,0
4673shape (OrthoPolyLine
4674uid 325,0
4675va (VaSet
4676vasetType 3
4677lineWidth 2
4678)
4679xt "109750,22000,122250,22000"
4680pts [
4681"109750,22000"
4682"122250,22000"
4683]
4684)
4685start &20
4686end &148
4687sat 32
4688eat 32
4689sty 1
4690st 0
4691sf 1
4692si 0
4693tg (WTG
4694uid 326,0
4695ps "ConnStartEndStrategy"
4696stg "STSignalDisplayStrategy"
4697f (Text
4698uid 327,0
4699va (VaSet
4700)
4701xt "111000,21000,117300,22000"
4702st "wiz_data : (15:0)"
4703blo "111000,21800"
4704tm "WireNameMgr"
4705)
4706)
4707on &66
4708)
4709*158 (Wire
4710uid 330,0
4711shape (OrthoPolyLine
4712uid 331,0
4713va (VaSet
4714vasetType 3
4715)
4716xt "109750,25000,122250,25000"
4717pts [
4718"109750,25000"
4719"122250,25000"
4720]
4721)
4722start &23
4723end &149
4724sat 32
4725eat 32
4726st 0
4727sf 1
4728si 0
4729tg (WTG
4730uid 332,0
4731ps "ConnStartEndStrategy"
4732stg "STSignalDisplayStrategy"
4733f (Text
4734uid 333,0
4735va (VaSet
4736)
4737xt "111000,24000,113600,25000"
4738st "wiz_rd"
4739blo "111000,24800"
4740tm "WireNameMgr"
4741)
4742)
4743on &67
4744)
4745*159 (Wire
4746uid 336,0
4747shape (OrthoPolyLine
4748uid 337,0
4749va (VaSet
4750vasetType 3
4751)
4752xt "109750,26000,122250,26000"
4753pts [
4754"109750,26000"
4755"122250,26000"
4756]
4757)
4758start &22
4759end &150
4760sat 32
4761eat 32
4762st 0
4763sf 1
4764si 0
4765tg (WTG
4766uid 338,0
4767ps "ConnStartEndStrategy"
4768stg "STSignalDisplayStrategy"
4769f (Text
4770uid 339,0
4771va (VaSet
4772)
4773xt "111000,25000,113700,26000"
4774st "wiz_wr"
4775blo "111000,25800"
4776tm "WireNameMgr"
4777)
4778)
4779on &68
4780)
4781*160 (Wire
4782uid 374,0
4783shape (OrthoPolyLine
4784uid 375,0
4785va (VaSet
4786vasetType 3
4787lineWidth 2
4788)
4789xt "109750,42000,122250,48000"
4790pts [
4791"109750,42000"
4792"120000,42000"
4793"120000,48000"
4794"122250,48000"
4795]
4796)
4797start &41
4798end &72
4799sat 32
4800eat 32
4801sty 1
4802st 0
4803sf 1
4804si 0
4805tg (WTG
4806uid 376,0
4807ps "ConnStartEndStrategy"
4808stg "STSignalDisplayStrategy"
4809f (Text
4810uid 377,0
4811va (VaSet
4812)
4813xt "111000,41000,117500,42000"
4814st "sensor_cs : (3:0)"
4815blo "111000,41800"
4816tm "WireNameMgr"
4817)
4818)
4819on &76
4820)
4821*161 (Wire
4822uid 380,0
4823shape (OrthoPolyLine
4824uid 381,0
4825va (VaSet
4826vasetType 3
4827)
4828xt "109750,51000,122250,51000"
4829pts [
4830"109750,51000"
4831"122250,51000"
4832]
4833)
4834start &38
4835end &70
4836sat 32
4837eat 32
4838st 0
4839sf 1
4840si 0
4841tg (WTG
4842uid 382,0
4843ps "ConnStartEndStrategy"
4844stg "STSignalDisplayStrategy"
4845f (Text
4846uid 383,0
4847va (VaSet
4848)
4849xt "111000,50000,112700,51000"
4850st "sclk"
4851blo "111000,50800"
4852tm "WireNameMgr"
4853)
4854)
4855on &77
4856)
4857*162 (Wire
4858uid 386,0
4859shape (OrthoPolyLine
4860uid 387,0
4861va (VaSet
4862vasetType 3
4863)
4864xt "109750,52000,122250,52000"
4865pts [
4866"109750,52000"
4867"122250,52000"
4868]
4869)
4870start &39
4871end &71
4872sat 32
4873eat 32
4874st 0
4875sf 1
4876si 0
4877tg (WTG
4878uid 388,0
4879ps "ConnStartEndStrategy"
4880stg "STSignalDisplayStrategy"
4881f (Text
4882uid 389,0
4883va (VaSet
4884)
4885xt "111000,51000,112400,52000"
4886st "sio"
4887blo "111000,51800"
4888tm "WireNameMgr"
4889)
4890)
4891on &78
4892)
4893*163 (Wire
4894uid 426,0
4895shape (OrthoPolyLine
4896uid 427,0
4897va (VaSet
4898vasetType 3
4899)
4900xt "58750,32000,80250,32000"
4901pts [
4902"58750,32000"
4903"80250,32000"
4904]
4905)
4906start &80
4907end &15
4908sat 32
4909eat 32
4910st 0
4911sf 1
4912tg (WTG
4913uid 428,0
4914ps "ConnStartEndStrategy"
4915stg "STSignalDisplayStrategy"
4916f (Text
4917uid 429,0
4918va (VaSet
4919)
4920xt "71000,31000,73800,32000"
4921st "trigger"
4922blo "71000,31800"
4923tm "WireNameMgr"
4924)
4925)
4926on &84
4927)
4928*164 (Wire
4929uid 442,0
4930shape (OrthoPolyLine
4931uid 443,0
4932va (VaSet
4933vasetType 3
4934lineWidth 2
4935)
4936xt "58000,34000,80250,42000"
4937pts [
4938"80250,34000"
4939"64000,34000"
4940"64000,42000"
4941"58000,42000"
4942]
4943)
4944start &17
4945end &85
4946sat 32
4947eat 2
4948sty 1
4949st 0
4950sf 1
4951si 0
4952tg (WTG
4953uid 446,0
4954ps "ConnStartEndStrategy"
4955stg "STSignalDisplayStrategy"
4956f (Text
4957uid 447,0
4958va (VaSet
4959)
4960xt "71000,33000,76900,34000"
4961st "board_id : (3:0)"
4962blo "71000,33800"
4963tm "WireNameMgr"
4964)
4965)
4966on &89
4967)
4968*165 (Wire
4969uid 450,0
4970shape (OrthoPolyLine
4971uid 451,0
4972va (VaSet
4973vasetType 3
4974lineWidth 2
4975)
4976xt "58000,35000,80250,43000"
4977pts [
4978"80250,35000"
4979"65000,35000"
4980"65000,43000"
4981"58000,43000"
4982]
4983)
4984start &18
4985end &85
4986sat 32
4987eat 2
4988sty 1
4989st 0
4990sf 1
4991si 0
4992tg (WTG
4993uid 454,0
4994ps "ConnStartEndStrategy"
4995stg "STSignalDisplayStrategy"
4996f (Text
4997uid 455,0
4998va (VaSet
4999)
5000xt "71000,34000,76700,35000"
5001st "crate_id : (1:0)"
5002blo "71000,34800"
5003tm "WireNameMgr"
5004)
5005)
5006on &90
5007)
5008*166 (Wire
5009uid 530,0
5010shape (OrthoPolyLine
5011uid 531,0
5012va (VaSet
5013vasetType 3
5014lineWidth 2
5015)
5016xt "58000,42000,80250,53000"
5017pts [
5018"80250,42000"
5019"68000,42000"
5020"68000,53000"
5021"58000,53000"
5022]
5023)
5024start &28
5025end &99
5026sat 32
5027eat 2
5028sty 1
5029st 0
5030sf 1
5031si 0
5032tg (WTG
5033uid 534,0
5034ps "ConnStartEndStrategy"
5035stg "STSignalDisplayStrategy"
5036f (Text
5037uid 535,0
5038va (VaSet
5039)
5040xt "71000,41000,79000,42000"
5041st "adc_otr_array : (3:0)"
5042blo "71000,41800"
5043tm "WireNameMgr"
5044)
5045)
5046on &103
5047)
5048*167 (Wire
5049uid 538,0
5050shape (OrthoPolyLine
5051uid 539,0
5052va (VaSet
5053vasetType 3
5054lineWidth 2
5055)
5056xt "58000,48000,80250,55000"
5057pts [
5058"80250,48000"
5059"70000,48000"
5060"70000,55000"
5061"58000,55000"
5062]
5063)
5064start &29
5065end &99
5066sat 32
5067eat 2
5068sty 1
5069st 0
5070sf 1
5071si 0
5072tg (WTG
5073uid 542,0
5074ps "ConnStartEndStrategy"
5075stg "STSignalDisplayStrategy"
5076f (Text
5077uid 543,0
5078va (VaSet
5079)
5080xt "71000,47000,76900,48000"
5081st "adc_data_array"
5082blo "71000,47800"
5083tm "WireNameMgr"
5084)
5085)
5086on &104
5087)
5088*168 (Wire
5089uid 546,0
5090shape (OrthoPolyLine
5091uid 547,0
5092va (VaSet
5093vasetType 3
5094)
5095xt "58000,43000,80250,54000"
5096pts [
5097"80250,43000"
5098"69000,43000"
5099"69000,54000"
5100"58000,54000"
5101]
5102)
5103start &16
5104end &99
5105sat 32
5106eat 1
5107st 0
5108sf 1
5109si 0
5110tg (WTG
5111uid 550,0
5112ps "ConnStartEndStrategy"
5113stg "STSignalDisplayStrategy"
5114f (Text
5115uid 551,0
5116va (VaSet
5117)
5118xt "71000,42000,74200,43000"
5119st "adc_oeb"
5120blo "71000,42800"
5121tm "WireNameMgr"
5122)
5123)
5124on &105
5125)
5126*169 (Wire
5127uid 554,0
5128shape (OrthoPolyLine
5129uid 555,0
5130va (VaSet
5131vasetType 3
5132)
5133xt "40750,54000,50000,54000"
5134pts [
5135"50000,54000"
5136"40750,54000"
5137]
5138)
5139start &99
5140end &95
5141sat 2
5142eat 32
5143st 0
5144sf 1
5145tg (WTG
5146uid 558,0
5147ps "ConnStartEndStrategy"
5148stg "STSignalDisplayStrategy"
5149f (Text
5150uid 559,0
5151va (VaSet
5152)
5153xt "42000,53000,45200,54000"
5154st "adc_oeb"
5155blo "42000,53800"
5156tm "WireNameMgr"
5157)
5158)
5159on &105
5160)
5161*170 (Wire
5162uid 562,0
5163shape (OrthoPolyLine
5164uid 563,0
5165va (VaSet
5166vasetType 3
5167)
5168xt "40750,53000,50000,53000"
5169pts [
5170"40750,53000"
5171"50000,53000"
5172]
5173)
5174start &94
5175end &99
5176sat 32
5177eat 1
5178st 0
5179sf 1
5180tg (WTG
5181uid 566,0
5182ps "ConnStartEndStrategy"
5183stg "STSignalDisplayStrategy"
5184f (Text
5185uid 567,0
5186va (VaSet
5187)
5188xt "42000,52000,44900,53000"
5189st "adc_otr"
5190blo "42000,52800"
5191tm "WireNameMgr"
5192)
5193)
5194on &106
5195)
5196*171 (Wire
5197uid 570,0
5198shape (OrthoPolyLine
5199uid 571,0
5200va (VaSet
5201vasetType 3
5202lineWidth 2
5203)
5204xt "40750,55000,50000,55000"
5205pts [
5206"40750,55000"
5207"50000,55000"
5208]
5209)
5210start &93
5211end &99
5212sat 32
5213eat 1
5214sty 1
5215st 0
5216sf 1
5217tg (WTG
5218uid 574,0
5219ps "ConnStartEndStrategy"
5220stg "STSignalDisplayStrategy"
5221f (Text
5222uid 575,0
5223va (VaSet
5224)
5225xt "42000,54000,48400,55000"
5226st "adc_data : (11:0)"
5227blo "42000,54800"
5228tm "WireNameMgr"
5229)
5230)
5231on &107
5232)
5233*172 (Wire
5234uid 578,0
5235shape (OrthoPolyLine
5236uid 579,0
5237va (VaSet
5238vasetType 3
5239)
5240xt "24000,53000,29250,53000"
5241pts [
5242"29250,53000"
5243"24000,53000"
5244]
5245)
5246start &92
5247sat 32
5248eat 16
5249st 0
5250sf 1
5251tg (WTG
5252uid 582,0
5253ps "ConnStartEndStrategy"
5254stg "STSignalDisplayStrategy"
5255f (Text
5256uid 583,0
5257va (VaSet
5258)
5259xt "25000,52000,29000,53000"
5260st "ADC_CLK"
5261blo "25000,52800"
5262tm "WireNameMgr"
5263)
5264)
5265on &144
5266)
5267*173 (Wire
5268uid 769,0
5269shape (OrthoPolyLine
5270uid 770,0
5271va (VaSet
5272vasetType 3
5273)
5274xt "109750,24000,116000,24000"
5275pts [
5276"109750,24000"
5277"116000,24000"
5278]
5279)
5280start &13
5281sat 32
5282eat 16
5283st 0
5284sf 1
5285si 0
5286tg (WTG
5287uid 773,0
5288ps "ConnStartEndStrategy"
5289stg "STSignalDisplayStrategy"
5290f (Text
5291uid 774,0
5292va (VaSet
5293)
5294xt "111000,23000,114600,24000"
5295st "wiz_reset"
5296blo "111000,23800"
5297tm "WireNameMgr"
5298)
5299)
5300on &108
5301)
5302*174 (Wire
5303uid 777,0
5304shape (OrthoPolyLine
5305uid 778,0
5306va (VaSet
5307vasetType 3
5308lineWidth 2
5309)
5310xt "109750,70000,116000,70000"
5311pts [
5312"109750,70000"
5313"116000,70000"
5314]
5315)
5316start &14
5317sat 32
5318eat 16
5319sty 1
5320st 0
5321sf 1
5322si 0
5323tg (WTG
5324uid 781,0
5325ps "ConnStartEndStrategy"
5326stg "STSignalDisplayStrategy"
5327f (Text
5328uid 782,0
5329va (VaSet
5330)
5331xt "111000,69000,115000,70000"
5332st "led : (7:0)"
5333blo "111000,69800"
5334tm "WireNameMgr"
5335)
5336)
5337on &109
5338)
5339*175 (Wire
5340uid 785,0
5341shape (OrthoPolyLine
5342uid 786,0
5343va (VaSet
5344vasetType 3
5345)
5346xt "109750,28000,116000,28000"
5347pts [
5348"109750,28000"
5349"116000,28000"
5350]
5351)
5352start &21
5353sat 32
5354eat 16
5355st 0
5356sf 1
5357si 0
5358tg (WTG
5359uid 789,0
5360ps "ConnStartEndStrategy"
5361stg "STSignalDisplayStrategy"
5362f (Text
5363uid 790,0
5364va (VaSet
5365)
5366xt "111000,27000,113700,28000"
5367st "wiz_cs"
5368blo "111000,27800"
5369tm "WireNameMgr"
5370)
5371)
5372on &110
5373)
5374*176 (Wire
5375uid 793,0
5376shape (OrthoPolyLine
5377uid 794,0
5378va (VaSet
5379vasetType 3
5380)
5381xt "109750,27000,122250,27000"
5382pts [
5383"122250,27000"
5384"109750,27000"
5385]
5386)
5387start &151
5388end &24
5389sat 32
5390eat 32
5391st 0
5392sf 1
5393si 0
5394tg (WTG
5395uid 797,0
5396ps "ConnStartEndStrategy"
5397stg "STSignalDisplayStrategy"
5398f (Text
5399uid 798,0
5400va (VaSet
5401)
5402xt "111000,26000,113700,27000"
5403st "wiz_int"
5404blo "111000,26800"
5405tm "WireNameMgr"
5406)
5407)
5408on &111
5409)
5410*177 (Wire
5411uid 801,0
5412shape (OrthoPolyLine
5413uid 802,0
5414va (VaSet
5415vasetType 3
5416)
5417xt "109750,40000,116000,40000"
5418pts [
5419"109750,40000"
5420"116000,40000"
5421]
5422)
5423start &40
5424sat 32
5425eat 16
5426st 0
5427sf 1
5428si 0
5429tg (WTG
5430uid 805,0
5431ps "ConnStartEndStrategy"
5432stg "STSignalDisplayStrategy"
5433f (Text
5434uid 806,0
5435va (VaSet
5436)
5437xt "111000,39000,113800,40000"
5438st "dac_cs"
5439blo "111000,39800"
5440tm "WireNameMgr"
5441)
5442)
5443on &112
5444)
5445*178 (Wire
5446uid 809,0
5447shape (OrthoPolyLine
5448uid 810,0
5449va (VaSet
5450vasetType 3
5451)
5452xt "109750,53000,116000,53000"
5453pts [
5454"109750,53000"
5455"116000,53000"
5456]
5457)
5458start &42
5459sat 32
5460eat 16
5461st 0
5462sf 1
5463si 0
5464tg (WTG
5465uid 813,0
5466ps "ConnStartEndStrategy"
5467stg "STSignalDisplayStrategy"
5468f (Text
5469uid 814,0
5470va (VaSet
5471)
5472xt "111000,52000,113000,53000"
5473st "mosi"
5474blo "111000,52800"
5475tm "WireNameMgr"
5476)
5477)
5478on &113
5479)
5480*179 (Wire
5481uid 817,0
5482shape (OrthoPolyLine
5483uid 818,0
5484va (VaSet
5485vasetType 3
5486)
5487xt "70000,66000,80250,66000"
5488pts [
5489"80250,66000"
5490"70000,66000"
5491]
5492)
5493start &43
5494sat 32
5495eat 16
5496st 0
5497sf 1
5498si 0
5499tg (WTG
5500uid 821,0
5501ps "ConnStartEndStrategy"
5502stg "STSignalDisplayStrategy"
5503f (Text
5504uid 822,0
5505va (VaSet
5506)
5507xt "71000,65000,74000,66000"
5508st "denable"
5509blo "71000,65800"
5510tm "WireNameMgr"
5511)
5512)
5513on &114
5514)
5515*180 (Wire
5516uid 825,0
5517shape (OrthoPolyLine
5518uid 826,0
5519va (VaSet
5520vasetType 3
5521)
5522xt "70000,23000,80250,23000"
5523pts [
5524"80250,23000"
5525"70000,23000"
5526]
5527)
5528start &25
5529sat 32
5530eat 16
5531st 0
5532sf 1
5533si 0
5534tg (WTG
5535uid 829,0
5536ps "ConnStartEndStrategy"
5537stg "STSignalDisplayStrategy"
5538f (Text
5539uid 830,0
5540va (VaSet
5541)
5542xt "71000,22000,75500,23000"
5543st "CLK_25_PS"
5544blo "71000,22800"
5545tm "WireNameMgr"
5546)
5547)
5548on &115
5549)
5550*181 (Wire
5551uid 833,0
5552shape (OrthoPolyLine
5553uid 834,0
5554va (VaSet
5555vasetType 3
5556)
5557xt "70000,22000,80250,22000"
5558pts [
5559"80250,22000"
5560"70000,22000"
5561]
5562)
5563start &26
5564sat 32
5565eat 16
5566st 0
5567sf 1
5568si 0
5569tg (WTG
5570uid 837,0
5571ps "ConnStartEndStrategy"
5572stg "STSignalDisplayStrategy"
5573f (Text
5574uid 838,0
5575va (VaSet
5576)
5577xt "71000,21000,74100,22000"
5578st "CLK_50"
5579blo "71000,21800"
5580tm "WireNameMgr"
5581)
5582)
5583on &116
5584)
5585*182 (Wire
5586uid 841,0
5587shape (OrthoPolyLine
5588uid 842,0
5589va (VaSet
5590vasetType 3
5591lineWidth 2
5592)
5593xt "70000,62000,80250,62000"
5594pts [
5595"80250,62000"
5596"70000,62000"
5597]
5598)
5599start &30
5600sat 32
5601eat 16
5602sty 1
5603st 0
5604sf 1
5605si 0
5606tg (WTG
5607uid 845,0
5608ps "ConnStartEndStrategy"
5609stg "STSignalDisplayStrategy"
5610f (Text
5611uid 846,0
5612va (VaSet
5613)
5614xt "71000,61000,79500,62000"
5615st "drs_channel_id : (3:0)"
5616blo "71000,61800"
5617tm "WireNameMgr"
5618)
5619)
5620on &117
5621)
5622*183 (Wire
5623uid 849,0
5624shape (OrthoPolyLine
5625uid 850,0
5626va (VaSet
5627vasetType 3
5628)
5629xt "70000,67000,80250,67000"
5630pts [
5631"80250,67000"
5632"70000,67000"
5633]
5634)
5635start &31
5636ss 0
5637sat 32
5638eat 16
5639st 0
5640sf 1
5641si 0
5642tg (WTG
5643uid 853,0
5644ps "ConnStartEndStrategy"
5645stg "STSignalDisplayStrategy"
5646f (Text
5647uid 854,0
5648va (VaSet
5649)
5650xt "71000,66000,75300,67000"
5651st "drs_dwrite"
5652blo "71000,66800"
5653tm "WireNameMgr"
5654)
5655)
5656on &118
5657)
5658*184 (Wire
5659uid 857,0
5660shape (OrthoPolyLine
5661uid 858,0
5662va (VaSet
5663vasetType 3
5664)
5665xt "70000,64000,80250,64000"
5666pts [
5667"80250,64000"
5668"70000,64000"
5669]
5670)
5671start &36
5672sat 32
5673eat 16
5674st 0
5675sf 1
5676si 0
5677tg (WTG
5678uid 861,0
5679ps "ConnStartEndStrategy"
5680stg "STSignalDisplayStrategy"
5681f (Text
5682uid 862,0
5683va (VaSet
5684)
5685xt "71000,63000,75200,64000"
5686st "RSRLOAD"
5687blo "71000,63800"
5688tm "WireNameMgr"
5689)
5690)
5691on &119
5692)
5693*185 (Wire
5694uid 865,0
5695shape (OrthoPolyLine
5696uid 866,0
5697va (VaSet
5698vasetType 3
5699)
5700xt "70000,65000,80250,65000"
5701pts [
5702"80250,65000"
5703"70000,65000"
5704]
5705)
5706start &37
5707sat 32
5708eat 16
5709st 0
5710sf 1
5711si 0
5712tg (WTG
5713uid 869,0
5714ps "ConnStartEndStrategy"
5715stg "STSignalDisplayStrategy"
5716f (Text
5717uid 870,0
5718va (VaSet
5719)
5720xt "71000,64000,74000,65000"
5721st "SRCLK"
5722blo "71000,64800"
5723tm "WireNameMgr"
5724)
5725)
5726on &120
5727)
5728*186 (Wire
5729uid 873,0
5730shape (OrthoPolyLine
5731uid 874,0
5732va (VaSet
5733vasetType 3
5734)
5735xt "70000,58000,80250,58000"
5736pts [
5737"70000,58000"
5738"80250,58000"
5739]
5740)
5741end &32
5742sat 16
5743eat 32
5744st 0
5745sf 1
5746si 0
5747tg (WTG
5748uid 877,0
5749ps "ConnStartEndStrategy"
5750stg "STSignalDisplayStrategy"
5751f (Text
5752uid 878,0
5753va (VaSet
5754)
5755xt "71000,57000,76400,58000"
5756st "SROUT_in_0"
5757blo "71000,57800"
5758tm "WireNameMgr"
5759)
5760)
5761on &121
5762)
5763*187 (Wire
5764uid 881,0
5765shape (OrthoPolyLine
5766uid 882,0
5767va (VaSet
5768vasetType 3
5769)
5770xt "70000,59000,80250,59000"
5771pts [
5772"70000,59000"
5773"80250,59000"
5774]
5775)
5776end &33
5777sat 16
5778eat 32
5779st 0
5780sf 1
5781si 0
5782tg (WTG
5783uid 885,0
5784ps "ConnStartEndStrategy"
5785stg "STSignalDisplayStrategy"
5786f (Text
5787uid 886,0
5788va (VaSet
5789)
5790xt "71000,58000,76400,59000"
5791st "SROUT_in_1"
5792blo "71000,58800"
5793tm "WireNameMgr"
5794)
5795)
5796on &122
5797)
5798*188 (Wire
5799uid 889,0
5800shape (OrthoPolyLine
5801uid 890,0
5802va (VaSet
5803vasetType 3
5804)
5805xt "70000,60000,80250,60000"
5806pts [
5807"70000,60000"
5808"80250,60000"
5809]
5810)
5811end &34
5812sat 16
5813eat 32
5814st 0
5815sf 1
5816si 0
5817tg (WTG
5818uid 893,0
5819ps "ConnStartEndStrategy"
5820stg "STSignalDisplayStrategy"
5821f (Text
5822uid 894,0
5823va (VaSet
5824)
5825xt "71000,59000,76400,60000"
5826st "SROUT_in_2"
5827blo "71000,59800"
5828tm "WireNameMgr"
5829)
5830)
5831on &123
5832)
5833*189 (Wire
5834uid 897,0
5835shape (OrthoPolyLine
5836uid 898,0
5837va (VaSet
5838vasetType 3
5839)
5840xt "70000,61000,80250,61000"
5841pts [
5842"70000,61000"
5843"80250,61000"
5844]
5845)
5846end &35
5847sat 16
5848eat 32
5849st 0
5850sf 1
5851si 0
5852tg (WTG
5853uid 901,0
5854ps "ConnStartEndStrategy"
5855stg "STSignalDisplayStrategy"
5856f (Text
5857uid 902,0
5858va (VaSet
5859)
5860xt "71000,60000,76400,61000"
5861st "SROUT_in_3"
5862blo "71000,60800"
5863tm "WireNameMgr"
5864)
5865)
5866on &124
5867)
5868*190 (Wire
5869uid 1437,0
5870shape (OrthoPolyLine
5871uid 1438,0
5872va (VaSet
5873vasetType 3
5874)
5875xt "73000,72000,80250,72000"
5876pts [
5877"80250,72000"
5878"73000,72000"
5879]
5880)
5881start &53
5882sat 32
5883eat 16
5884st 0
5885sf 1
5886si 0
5887tg (WTG
5888uid 1441,0
5889ps "ConnStartEndStrategy"
5890stg "STSignalDisplayStrategy"
5891f (Text
5892uid 1442,0
5893va (VaSet
5894)
5895xt "76000,72000,79700,73000"
5896st "SRIN_out"
5897blo "76000,72800"
5898tm "WireNameMgr"
5899)
5900)
5901on &125
5902)
5903*191 (Wire
5904uid 1445,0
5905shape (OrthoPolyLine
5906uid 1446,0
5907va (VaSet
5908vasetType 3
5909)
5910xt "109750,80000,115000,80000"
5911pts [
5912"109750,80000"
5913"115000,80000"
5914]
5915)
5916start &46
5917sat 32
5918eat 16
5919st 0
5920sf 1
5921si 0
5922tg (WTG
5923uid 1449,0
5924ps "ConnStartEndStrategy"
5925stg "STSignalDisplayStrategy"
5926f (Text
5927uid 1450,0
5928va (VaSet
5929)
5930xt "111000,79000,113500,80000"
5931st "amber"
5932blo "111000,79800"
5933tm "WireNameMgr"
5934)
5935)
5936on &126
5937)
5938*192 (Wire
5939uid 1453,0
5940shape (OrthoPolyLine
5941uid 1454,0
5942va (VaSet
5943vasetType 3
5944)
5945xt "109750,79000,114000,79000"
5946pts [
5947"109750,79000"
5948"114000,79000"
5949]
5950)
5951start &52
5952sat 32
5953eat 16
5954st 0
5955sf 1
5956si 0
5957tg (WTG
5958uid 1457,0
5959ps "ConnStartEndStrategy"
5960stg "STSignalDisplayStrategy"
5961f (Text
5962uid 1458,0
5963va (VaSet
5964)
5965xt "111000,78000,112500,79000"
5966st "red"
5967blo "111000,78800"
5968tm "WireNameMgr"
5969)
5970)
5971on &127
5972)
5973*193 (Wire
5974uid 1461,0
5975shape (OrthoPolyLine
5976uid 1462,0
5977va (VaSet
5978vasetType 3
5979)
5980xt "109750,78000,114000,78000"
5981pts [
5982"109750,78000"
5983"114000,78000"
5984]
5985)
5986start &50
5987sat 32
5988eat 16
5989st 0
5990sf 1
5991si 0
5992tg (WTG
5993uid 1465,0
5994ps "ConnStartEndStrategy"
5995stg "STSignalDisplayStrategy"
5996f (Text
5997uid 1466,0
5998va (VaSet
5999)
6000xt "111000,77000,113400,78000"
6001st "green"
6002blo "111000,77800"
6003tm "WireNameMgr"
6004)
6005)
6006on &128
6007)
6008*194 (Wire
6009uid 1469,0
6010shape (OrthoPolyLine
6011uid 1470,0
6012va (VaSet
6013vasetType 3
6014lineWidth 2
6015)
6016xt "109750,77000,121000,77000"
6017pts [
6018"109750,77000"
6019"121000,77000"
6020]
6021)
6022start &47
6023sat 32
6024eat 16
6025sty 1
6026st 0
6027sf 1
6028si 0
6029tg (WTG
6030uid 1473,0
6031ps "ConnStartEndStrategy"
6032stg "STSignalDisplayStrategy"
6033f (Text
6034uid 1474,0
6035va (VaSet
6036)
6037xt "111000,76000,119600,77000"
6038st "counter_result : (11:0)"
6039blo "111000,76800"
6040tm "WireNameMgr"
6041)
6042)
6043on &129
6044)
6045*195 (Wire
6046uid 1477,0
6047shape (OrthoPolyLine
6048uid 1478,0
6049va (VaSet
6050vasetType 3
6051)
6052xt "109750,75000,120000,75000"
6053pts [
6054"109750,75000"
6055"120000,75000"
6056]
6057)
6058start &45
6059sat 32
6060eat 16
6061st 0
6062sf 1
6063si 0
6064tg (WTG
6065uid 1481,0
6066ps "ConnStartEndStrategy"
6067stg "STSignalDisplayStrategy"
6068f (Text
6069uid 1482,0
6070va (VaSet
6071)
6072xt "111000,74000,119200,75000"
6073st "alarm_refclk_too_low"
6074blo "111000,74800"
6075tm "WireNameMgr"
6076)
6077)
6078on &130
6079)
6080*196 (Wire
6081uid 1485,0
6082shape (OrthoPolyLine
6083uid 1486,0
6084va (VaSet
6085vasetType 3
6086)
6087xt "109750,74000,121000,74000"
6088pts [
6089"109750,74000"
6090"121000,74000"
6091]
6092)
6093start &44
6094sat 32
6095eat 16
6096st 0
6097sf 1
6098si 0
6099tg (WTG
6100uid 1489,0
6101ps "ConnStartEndStrategy"
6102stg "STSignalDisplayStrategy"
6103f (Text
6104uid 1490,0
6105va (VaSet
6106)
6107xt "111000,73000,119600,74000"
6108st "alarm_refclk_too_high"
6109blo "111000,73800"
6110tm "WireNameMgr"
6111)
6112)
6113on &131
6114)
6115*197 (Wire
6116uid 1503,0
6117shape (OrthoPolyLine
6118uid 1504,0
6119va (VaSet
6120vasetType 3
6121lineWidth 2
6122)
6123xt "73000,75000,80250,75000"
6124pts [
6125"73000,75000"
6126"80250,75000"
6127]
6128)
6129end &48
6130sat 16
6131eat 32
6132sty 1
6133st 0
6134sf 1
6135si 0
6136tg (WTG
6137uid 1507,0
6138ps "ConnStartEndStrategy"
6139stg "STSignalDisplayStrategy"
6140f (Text
6141uid 1508,0
6142va (VaSet
6143)
6144xt "74000,74000,79500,75000"
6145st "D_T_in : (1:0)"
6146blo "74000,74800"
6147tm "WireNameMgr"
6148)
6149)
6150on &136
6151)
6152*198 (Wire
6153uid 1529,0
6154shape (OrthoPolyLine
6155uid 1530,0
6156va (VaSet
6157vasetType 3
6158)
6159xt "66750,76000,80250,79000"
6160pts [
6161"66750,79000"
6162"70000,79000"
6163"70000,76000"
6164"80250,76000"
6165]
6166)
6167start &138
6168end &49
6169sat 32
6170eat 32
6171st 0
6172sf 1
6173si 0
6174tg (WTG
6175uid 1531,0
6176ps "ConnStartEndStrategy"
6177stg "STSignalDisplayStrategy"
6178f (Text
6179uid 1532,0
6180va (VaSet
6181)
6182xt "68750,78000,72650,79000"
6183st "REF_CLK"
6184blo "68750,78800"
6185tm "WireNameMgr"
6186)
6187)
6188on &145
6189)
6190*199 (Wire
6191uid 1533,0
6192shape (OrthoPolyLine
6193uid 1534,0
6194va (VaSet
6195vasetType 3
6196)
6197xt "35000,70000,45000,70000"
6198pts [
6199"35000,70000"
6200"45000,70000"
6201]
6202)
6203start &132
6204sat 2
6205eat 16
6206st 0
6207sf 1
6208si 0
6209tg (WTG
6210uid 1539,0
6211ps "ConnStartEndStrategy"
6212stg "STSignalDisplayStrategy"
6213f (Text
6214uid 1540,0
6215va (VaSet
6216)
6217xt "37000,69000,42500,70000"
6218st "D_T_in : (1:0)"
6219blo "37000,69800"
6220tm "WireNameMgr"
6221)
6222)
6223on &136
6224)
6225*200 (Wire
6226uid 1561,0
6227shape (OrthoPolyLine
6228uid 1562,0
6229va (VaSet
6230vasetType 3
6231lineWidth 2
6232)
6233xt "72000,77000,80250,77000"
6234pts [
6235"72000,77000"
6236"80250,77000"
6237]
6238)
6239end &51
6240sat 16
6241eat 32
6242sty 1
6243st 0
6244sf 1
6245si 0
6246tg (WTG
6247uid 1565,0
6248ps "ConnStartEndStrategy"
6249stg "STSignalDisplayStrategy"
6250f (Text
6251uid 1566,0
6252va (VaSet
6253)
6254xt "73000,76000,79100,77000"
6255st "plllock_in : (3:0)"
6256blo "73000,76800"
6257tm "WireNameMgr"
6258)
6259)
6260on &143
6261)
6262*201 (Wire
6263uid 1567,0
6264shape (OrthoPolyLine
6265uid 1568,0
6266va (VaSet
6267vasetType 3
6268)
6269xt "35000,71000,45000,71000"
6270pts [
6271"35000,71000"
6272"45000,71000"
6273]
6274)
6275start &132
6276sat 2
6277eat 16
6278st 0
6279sf 1
6280si 0
6281tg (WTG
6282uid 1573,0
6283ps "ConnStartEndStrategy"
6284stg "STSignalDisplayStrategy"
6285f (Text
6286uid 1574,0
6287va (VaSet
6288)
6289xt "37000,70000,43100,71000"
6290st "plllock_in : (3:0)"
6291blo "37000,70800"
6292tm "WireNameMgr"
6293)
6294)
6295on &143
6296)
6297*202 (Wire
6298uid 1684,0
6299shape (OrthoPolyLine
6300uid 1685,0
6301va (VaSet
6302vasetType 3
6303)
6304xt "70000,24000,80250,24000"
6305pts [
6306"80250,24000"
6307"70000,24000"
6308]
6309)
6310start &54
6311sat 32
6312eat 16
6313st 0
6314sf 1
6315si 0
6316tg (WTG
6317uid 1688,0
6318ps "ConnStartEndStrategy"
6319stg "STSignalDisplayStrategy"
6320f (Text
6321uid 1689,0
6322va (VaSet
6323)
6324xt "71000,23000,75000,24000"
6325st "ADC_CLK"
6326blo "71000,23800"
6327tm "WireNameMgr"
6328)
6329)
6330on &144
6331)
6332]
6333bg "65535,65535,65535"
6334grid (Grid
6335origin "0,0"
6336isVisible 1
6337isActive 1
6338xSpacing 1000
6339xySpacing 1000
6340xShown 1
6341yShown 1
6342color "26368,26368,26368"
6343)
6344packageList *203 (PackageList
6345uid 41,0
6346stg "VerticalLayoutStrategy"
6347textVec [
6348*204 (Text
6349uid 42,0
6350va (VaSet
6351font "arial,8,1"
6352)
6353xt "-87000,0,-81600,1000"
6354st "Package List"
6355blo "-87000,800"
6356)
6357*205 (MLText
6358uid 43,0
6359va (VaSet
6360)
6361xt "-87000,1000,-72500,11000"
6362st "LIBRARY ieee;
6363USE ieee.std_logic_1164.all;
6364USE ieee.std_logic_arith.all;
6365USE ieee.std_logic_unsigned.all;
6366
6367LIBRARY FACT_FAD_lib;
6368USE FACT_FAD_lib.fad_definitions.all;
6369USE ieee.std_logic_textio.all;
6370LIBRARY std;
6371USE std.textio.all;"
6372tm "PackageList"
6373)
6374]
6375)
6376compDirBlock (MlTextGroup
6377uid 44,0
6378stg "VerticalLayoutStrategy"
6379textVec [
6380*206 (Text
6381uid 45,0
6382va (VaSet
6383isHidden 1
6384font "Arial,8,1"
6385)
6386xt "20000,0,28100,1000"
6387st "Compiler Directives"
6388blo "20000,800"
6389)
6390*207 (Text
6391uid 46,0
6392va (VaSet
6393isHidden 1
6394font "Arial,8,1"
6395)
6396xt "20000,1000,29600,2000"
6397st "Pre-module directives:"
6398blo "20000,1800"
6399)
6400*208 (MLText
6401uid 47,0
6402va (VaSet
6403isHidden 1
6404)
6405xt "20000,2000,27500,4000"
6406st "`resetall
6407`timescale 1ns/10ps"
6408tm "BdCompilerDirectivesTextMgr"
6409)
6410*209 (Text
6411uid 48,0
6412va (VaSet
6413isHidden 1
6414font "Arial,8,1"
6415)
6416xt "20000,4000,30100,5000"
6417st "Post-module directives:"
6418blo "20000,4800"
6419)
6420*210 (MLText
6421uid 49,0
6422va (VaSet
6423isHidden 1
6424)
6425xt "20000,0,20000,0"
6426tm "BdCompilerDirectivesTextMgr"
6427)
6428*211 (Text
6429uid 50,0
6430va (VaSet
6431isHidden 1
6432font "Arial,8,1"
6433)
6434xt "20000,5000,29900,6000"
6435st "End-module directives:"
6436blo "20000,5800"
6437)
6438*212 (MLText
6439uid 51,0
6440va (VaSet
6441isHidden 1
6442)
6443xt "20000,6000,20000,6000"
6444tm "BdCompilerDirectivesTextMgr"
6445)
6446]
6447associable 1
6448)
6449windowSize "0,0,1681,1030"
6450viewArea "60000,4200,152106,60144"
6451cachedDiagramExtent "-92000,0,146000,98000"
6452pageSetupInfo (PageSetupInfo
6453ptrCmd ""
6454toPrinter 1
6455exportedDirectories [
6456"$HDS_PROJECT_DIR/HTMLExport"
6457]
6458exportStdIncludeRefs 1
6459exportStdPackageRefs 1
6460)
6461hasePageBreakOrigin 1
6462pageBreakOrigin "-146000,0"
6463lastUid 2446,0
6464defaultCommentText (CommentText
6465shape (Rectangle
6466layer 0
6467va (VaSet
6468vasetType 1
6469fg "65280,65280,46080"
6470lineColor "0,0,32768"
6471)
6472xt "0,0,15000,5000"
6473)
6474text (MLText
6475va (VaSet
6476fg "0,0,32768"
6477)
6478xt "200,200,2000,1200"
6479st "
6480Text
6481"
6482tm "CommentText"
6483wrapOption 3
6484visibleHeight 4600
6485visibleWidth 14600
6486)
6487)
6488defaultPanel (Panel
6489shape (RectFrame
6490va (VaSet
6491vasetType 1
6492fg "65535,65535,65535"
6493lineColor "32768,0,0"
6494lineWidth 2
6495)
6496xt "0,0,20000,20000"
6497)
6498title (TextAssociate
6499ps "TopLeftStrategy"
6500text (Text
6501va (VaSet
6502font "Arial,8,1"
6503)
6504xt "1000,1000,3800,2000"
6505st "Panel0"
6506blo "1000,1800"
6507tm "PanelText"
6508)
6509)
6510)
6511defaultBlk (Blk
6512shape (Rectangle
6513va (VaSet
6514vasetType 1
6515fg "39936,56832,65280"
6516lineColor "0,0,32768"
6517lineWidth 2
6518)
6519xt "0,0,8000,10000"
6520)
6521ttg (MlTextGroup
6522ps "CenterOffsetStrategy"
6523stg "VerticalLayoutStrategy"
6524textVec [
6525*213 (Text
6526va (VaSet
6527font "Arial,8,1"
6528)
6529xt "2200,3500,5800,4500"
6530st "<library>"
6531blo "2200,4300"
6532tm "BdLibraryNameMgr"
6533)
6534*214 (Text
6535va (VaSet
6536font "Arial,8,1"
6537)
6538xt "2200,4500,5600,5500"
6539st "<block>"
6540blo "2200,5300"
6541tm "BlkNameMgr"
6542)
6543*215 (Text
6544va (VaSet
6545font "Arial,8,1"
6546)
6547xt "2200,5500,3200,6500"
6548st "I0"
6549blo "2200,6300"
6550tm "InstanceNameMgr"
6551)
6552]
6553)
6554ga (GenericAssociation
6555ps "EdgeToEdgeStrategy"
6556matrix (Matrix
6557text (MLText
6558va (VaSet
6559font "Courier New,8,0"
6560)
6561xt "2200,13500,2200,13500"
6562)
6563header ""
6564)
6565elements [
6566]
6567)
6568viewicon (ZoomableIcon
6569sl 0
6570va (VaSet
6571vasetType 1
6572fg "49152,49152,49152"
6573)
6574xt "0,0,1500,1500"
6575iconName "UnknownFile.png"
6576iconMaskName "UnknownFile.msk"
6577)
6578viewiconposition 0
6579)
6580defaultMWComponent (MWC
6581shape (Rectangle
6582va (VaSet
6583vasetType 1
6584fg "0,65535,0"
6585lineColor "0,32896,0"
6586lineWidth 2
6587)
6588xt "0,0,8000,10000"
6589)
6590ttg (MlTextGroup
6591ps "CenterOffsetStrategy"
6592stg "VerticalLayoutStrategy"
6593textVec [
6594*216 (Text
6595va (VaSet
6596font "Arial,8,1"
6597)
6598xt "550,3500,3450,4500"
6599st "Library"
6600blo "550,4300"
6601)
6602*217 (Text
6603va (VaSet
6604font "Arial,8,1"
6605)
6606xt "550,4500,7450,5500"
6607st "MWComponent"
6608blo "550,5300"
6609)
6610*218 (Text
6611va (VaSet
6612font "Arial,8,1"
6613)
6614xt "550,5500,1550,6500"
6615st "I0"
6616blo "550,6300"
6617tm "InstanceNameMgr"
6618)
6619]
6620)
6621ga (GenericAssociation
6622ps "EdgeToEdgeStrategy"
6623matrix (Matrix
6624text (MLText
6625va (VaSet
6626font "Courier New,8,0"
6627)
6628xt "-6450,1500,-6450,1500"
6629)
6630header ""
6631)
6632elements [
6633]
6634)
6635portVis (PortSigDisplay
6636)
6637prms (Property
6638pclass "params"
6639pname "params"
6640ptn "String"
6641)
6642visOptions (mwParamsVisibilityOptions
6643)
6644)
6645defaultSaComponent (SaComponent
6646shape (Rectangle
6647va (VaSet
6648vasetType 1
6649fg "0,65535,0"
6650lineColor "0,32896,0"
6651lineWidth 2
6652)
6653xt "0,0,8000,10000"
6654)
6655ttg (MlTextGroup
6656ps "CenterOffsetStrategy"
6657stg "VerticalLayoutStrategy"
6658textVec [
6659*219 (Text
6660va (VaSet
6661font "Arial,8,1"
6662)
6663xt "900,3500,3800,4500"
6664st "Library"
6665blo "900,4300"
6666tm "BdLibraryNameMgr"
6667)
6668*220 (Text
6669va (VaSet
6670font "Arial,8,1"
6671)
6672xt "900,4500,7100,5500"
6673st "SaComponent"
6674blo "900,5300"
6675tm "CptNameMgr"
6676)
6677*221 (Text
6678va (VaSet
6679font "Arial,8,1"
6680)
6681xt "900,5500,1900,6500"
6682st "I0"
6683blo "900,6300"
6684tm "InstanceNameMgr"
6685)
6686]
6687)
6688ga (GenericAssociation
6689ps "EdgeToEdgeStrategy"
6690matrix (Matrix
6691text (MLText
6692va (VaSet
6693font "Courier New,8,0"
6694)
6695xt "-6100,1500,-6100,1500"
6696)
6697header ""
6698)
6699elements [
6700]
6701)
6702viewicon (ZoomableIcon
6703sl 0
6704va (VaSet
6705vasetType 1
6706fg "49152,49152,49152"
6707)
6708xt "0,0,1500,1500"
6709iconName "UnknownFile.png"
6710iconMaskName "UnknownFile.msk"
6711)
6712viewiconposition 0
6713portVis (PortSigDisplay
6714)
6715archFileType "UNKNOWN"
6716)
6717defaultVhdlComponent (VhdlComponent
6718shape (Rectangle
6719va (VaSet
6720vasetType 1
6721fg "0,65535,0"
6722lineColor "0,32896,0"
6723lineWidth 2
6724)
6725xt "0,0,8000,10000"
6726)
6727ttg (MlTextGroup
6728ps "CenterOffsetStrategy"
6729stg "VerticalLayoutStrategy"
6730textVec [
6731*222 (Text
6732va (VaSet
6733font "Arial,8,1"
6734)
6735xt "500,3500,3400,4500"
6736st "Library"
6737blo "500,4300"
6738)
6739*223 (Text
6740va (VaSet
6741font "Arial,8,1"
6742)
6743xt "500,4500,7500,5500"
6744st "VhdlComponent"
6745blo "500,5300"
6746)
6747*224 (Text
6748va (VaSet
6749font "Arial,8,1"
6750)
6751xt "500,5500,1500,6500"
6752st "I0"
6753blo "500,6300"
6754tm "InstanceNameMgr"
6755)
6756]
6757)
6758ga (GenericAssociation
6759ps "EdgeToEdgeStrategy"
6760matrix (Matrix
6761text (MLText
6762va (VaSet
6763font "Courier New,8,0"
6764)
6765xt "-6500,1500,-6500,1500"
6766)
6767header ""
6768)
6769elements [
6770]
6771)
6772portVis (PortSigDisplay
6773)
6774entityPath ""
6775archName ""
6776archPath ""
6777)
6778defaultVerilogComponent (VerilogComponent
6779shape (Rectangle
6780va (VaSet
6781vasetType 1
6782fg "0,65535,0"
6783lineColor "0,32896,0"
6784lineWidth 2
6785)
6786xt "-450,0,8450,10000"
6787)
6788ttg (MlTextGroup
6789ps "CenterOffsetStrategy"
6790stg "VerticalLayoutStrategy"
6791textVec [
6792*225 (Text
6793va (VaSet
6794font "Arial,8,1"
6795)
6796xt "50,3500,2950,4500"
6797st "Library"
6798blo "50,4300"
6799)
6800*226 (Text
6801va (VaSet
6802font "Arial,8,1"
6803)
6804xt "50,4500,7950,5500"
6805st "VerilogComponent"
6806blo "50,5300"
6807)
6808*227 (Text
6809va (VaSet
6810font "Arial,8,1"
6811)
6812xt "50,5500,1050,6500"
6813st "I0"
6814blo "50,6300"
6815tm "InstanceNameMgr"
6816)
6817]
6818)
6819ga (GenericAssociation
6820ps "EdgeToEdgeStrategy"
6821matrix (Matrix
6822text (MLText
6823va (VaSet
6824font "Courier New,8,0"
6825)
6826xt "-6950,1500,-6950,1500"
6827)
6828header ""
6829)
6830elements [
6831]
6832)
6833entityPath ""
6834)
6835defaultHdlText (HdlText
6836shape (Rectangle
6837va (VaSet
6838vasetType 1
6839fg "65535,65535,37120"
6840lineColor "0,0,32768"
6841lineWidth 2
6842)
6843xt "0,0,8000,10000"
6844)
6845ttg (MlTextGroup
6846ps "CenterOffsetStrategy"
6847stg "VerticalLayoutStrategy"
6848textVec [
6849*228 (Text
6850va (VaSet
6851font "Arial,8,1"
6852)
6853xt "3150,4000,4850,5000"
6854st "eb1"
6855blo "3150,4800"
6856tm "HdlTextNameMgr"
6857)
6858*229 (Text
6859va (VaSet
6860font "Arial,8,1"
6861)
6862xt "3150,5000,3950,6000"
6863st "1"
6864blo "3150,5800"
6865tm "HdlTextNumberMgr"
6866)
6867]
6868)
6869viewicon (ZoomableIcon
6870sl 0
6871va (VaSet
6872vasetType 1
6873fg "49152,49152,49152"
6874)
6875xt "0,0,1500,1500"
6876iconName "UnknownFile.png"
6877iconMaskName "UnknownFile.msk"
6878)
6879viewiconposition 0
6880)
6881defaultEmbeddedText (EmbeddedText
6882commentText (CommentText
6883ps "CenterOffsetStrategy"
6884shape (Rectangle
6885va (VaSet
6886vasetType 1
6887fg "65535,65535,65535"
6888lineColor "0,0,32768"
6889lineWidth 2
6890)
6891xt "0,0,18000,5000"
6892)
6893text (MLText
6894va (VaSet
6895)
6896xt "200,200,2000,1200"
6897st "
6898Text
6899"
6900tm "HdlTextMgr"
6901wrapOption 3
6902visibleHeight 4600
6903visibleWidth 17600
6904)
6905)
6906)
6907defaultGlobalConnector (GlobalConnector
6908shape (Circle
6909va (VaSet
6910vasetType 1
6911fg "65535,65535,0"
6912)
6913xt "-1000,-1000,1000,1000"
6914radius 1000
6915)
6916name (Text
6917va (VaSet
6918font "Arial,8,1"
6919)
6920xt "-500,-500,500,500"
6921st "G"
6922blo "-500,300"
6923)
6924)
6925defaultRipper (Ripper
6926ps "OnConnectorStrategy"
6927shape (Line2D
6928pts [
6929"0,0"
6930"1000,1000"
6931]
6932va (VaSet
6933vasetType 1
6934)
6935xt "0,0,1000,1000"
6936)
6937)
6938defaultBdJunction (BdJunction
6939ps "OnConnectorStrategy"
6940shape (Circle
6941va (VaSet
6942vasetType 1
6943)
6944xt "-400,-400,400,400"
6945radius 400
6946)
6947)
6948defaultPortIoIn (PortIoIn
6949shape (CompositeShape
6950va (VaSet
6951vasetType 1
6952fg "0,0,32768"
6953)
6954optionalChildren [
6955(Pentagon
6956sl 0
6957ro 270
6958xt "-2000,-375,-500,375"
6959)
6960(Line
6961sl 0
6962ro 270
6963xt "-500,0,0,0"
6964pts [
6965"-500,0"
6966"0,0"
6967]
6968)
6969]
6970)
6971stc 0
6972sf 1
6973tg (WTG
6974ps "PortIoTextPlaceStrategy"
6975stg "STSignalDisplayStrategy"
6976f (Text
6977va (VaSet
6978)
6979xt "-1375,-1000,-1375,-1000"
6980ju 2
6981blo "-1375,-1000"
6982tm "WireNameMgr"
6983)
6984)
6985)
6986defaultPortIoOut (PortIoOut
6987shape (CompositeShape
6988va (VaSet
6989vasetType 1
6990fg "0,0,32768"
6991)
6992optionalChildren [
6993(Pentagon
6994sl 0
6995ro 270
6996xt "500,-375,2000,375"
6997)
6998(Line
6999sl 0
7000ro 270
7001xt "0,0,500,0"
7002pts [
7003"0,0"
7004"500,0"
7005]
7006)
7007]
7008)
7009stc 0
7010sf 1
7011tg (WTG
7012ps "PortIoTextPlaceStrategy"
7013stg "STSignalDisplayStrategy"
7014f (Text
7015va (VaSet
7016)
7017xt "625,-1000,625,-1000"
7018blo "625,-1000"
7019tm "WireNameMgr"
7020)
7021)
7022)
7023defaultPortIoInOut (PortIoInOut
7024shape (CompositeShape
7025va (VaSet
7026vasetType 1
7027fg "0,0,32768"
7028)
7029optionalChildren [
7030(Hexagon
7031sl 0
7032xt "500,-375,2000,375"
7033)
7034(Line
7035sl 0
7036xt "0,0,500,0"
7037pts [
7038"0,0"
7039"500,0"
7040]
7041)
7042]
7043)
7044stc 0
7045sf 1
7046tg (WTG
7047ps "PortIoTextPlaceStrategy"
7048stg "STSignalDisplayStrategy"
7049f (Text
7050va (VaSet
7051)
7052xt "0,-375,0,-375"
7053blo "0,-375"
7054tm "WireNameMgr"
7055)
7056)
7057)
7058defaultPortIoBuffer (PortIoBuffer
7059shape (CompositeShape
7060va (VaSet
7061vasetType 1
7062fg "65535,65535,65535"
7063lineColor "0,0,32768"
7064)
7065optionalChildren [
7066(Hexagon
7067sl 0
7068xt "500,-375,2000,375"
7069)
7070(Line
7071sl 0
7072xt "0,0,500,0"
7073pts [
7074"0,0"
7075"500,0"
7076]
7077)
7078]
7079)
7080stc 0
7081sf 1
7082tg (WTG
7083ps "PortIoTextPlaceStrategy"
7084stg "STSignalDisplayStrategy"
7085f (Text
7086va (VaSet
7087)
7088xt "0,-375,0,-375"
7089blo "0,-375"
7090tm "WireNameMgr"
7091)
7092)
7093)
7094defaultSignal (Wire
7095shape (OrthoPolyLine
7096va (VaSet
7097vasetType 3
7098)
7099pts [
7100"0,0"
7101"0,0"
7102]
7103)
7104ss 0
7105es 0
7106sat 32
7107eat 32
7108st 0
7109sf 1
7110si 0
7111tg (WTG
7112ps "ConnStartEndStrategy"
7113stg "STSignalDisplayStrategy"
7114f (Text
7115va (VaSet
7116)
7117xt "0,0,1900,1000"
7118st "sig0"
7119blo "0,800"
7120tm "WireNameMgr"
7121)
7122)
7123)
7124defaultBus (Wire
7125shape (OrthoPolyLine
7126va (VaSet
7127vasetType 3
7128lineWidth 2
7129)
7130pts [
7131"0,0"
7132"0,0"
7133]
7134)
7135ss 0
7136es 0
7137sat 32
7138eat 32
7139sty 1
7140st 0
7141sf 1
7142si 0
7143tg (WTG
7144ps "ConnStartEndStrategy"
7145stg "STSignalDisplayStrategy"
7146f (Text
7147va (VaSet
7148)
7149xt "0,0,2400,1000"
7150st "dbus0"
7151blo "0,800"
7152tm "WireNameMgr"
7153)
7154)
7155)
7156defaultBundle (Bundle
7157shape (OrthoPolyLine
7158va (VaSet
7159vasetType 3
7160lineColor "32768,0,0"
7161lineWidth 2
7162)
7163pts [
7164"0,0"
7165"0,0"
7166]
7167)
7168ss 0
7169es 0
7170sat 32
7171eat 32
7172textGroup (BiTextGroup
7173ps "ConnStartEndStrategy"
7174stg "VerticalLayoutStrategy"
7175first (Text
7176va (VaSet
7177)
7178xt "0,0,3000,1000"
7179st "bundle0"
7180blo "0,800"
7181tm "BundleNameMgr"
7182)
7183second (MLText
7184va (VaSet
7185)
7186xt "0,1000,1000,2000"
7187st "()"
7188tm "BundleContentsMgr"
7189)
7190)
7191bundleNet &0
7192)
7193defaultPortMapFrame (PortMapFrame
7194ps "PortMapFrameStrategy"
7195shape (RectFrame
7196va (VaSet
7197vasetType 1
7198fg "65535,65535,65535"
7199lineColor "0,0,32768"
7200lineWidth 2
7201)
7202xt "0,0,10000,12000"
7203)
7204portMapText (BiTextGroup
7205ps "BottomRightOffsetStrategy"
7206stg "VerticalLayoutStrategy"
7207first (MLText
7208va (VaSet
7209)
7210)
7211second (MLText
7212va (VaSet
7213)
7214tm "PortMapTextMgr"
7215)
7216)
7217)
7218defaultGenFrame (Frame
7219shape (RectFrame
7220va (VaSet
7221vasetType 1
7222fg "65535,65535,65535"
7223lineColor "26368,26368,26368"
7224lineStyle 2
7225lineWidth 2
7226)
7227xt "0,0,20000,20000"
7228)
7229title (TextAssociate
7230ps "TopLeftStrategy"
7231text (MLText
7232va (VaSet
7233)
7234xt "0,-1100,12600,-100"
7235st "g0: FOR i IN 0 TO n GENERATE"
7236tm "FrameTitleTextMgr"
7237)
7238)
7239seqNum (FrameSequenceNumber
7240ps "TopLeftStrategy"
7241shape (Rectangle
7242va (VaSet
7243vasetType 1
7244fg "65535,65535,65535"
7245)
7246xt "50,50,1250,1450"
7247)
7248num (Text
7249va (VaSet
7250)
7251xt "250,250,1050,1250"
7252st "1"
7253blo "250,1050"
7254tm "FrameSeqNumMgr"
7255)
7256)
7257decls (MlTextGroup
7258ps "BottomRightOffsetStrategy"
7259stg "VerticalLayoutStrategy"
7260textVec [
7261*230 (Text
7262va (VaSet
7263font "Arial,8,1"
7264)
7265xt "14100,20000,22000,21000"
7266st "Frame Declarations"
7267blo "14100,20800"
7268)
7269*231 (MLText
7270va (VaSet
7271)
7272xt "14100,21000,14100,21000"
7273tm "BdFrameDeclTextMgr"
7274)
7275]
7276)
7277)
7278defaultBlockFrame (Frame
7279shape (RectFrame
7280va (VaSet
7281vasetType 1
7282fg "65535,65535,65535"
7283lineColor "26368,26368,26368"
7284lineStyle 1
7285lineWidth 2
7286)
7287xt "0,0,20000,20000"
7288)
7289title (TextAssociate
7290ps "TopLeftStrategy"
7291text (MLText
7292va (VaSet
7293)
7294xt "0,-1100,7400,-100"
7295st "b0: BLOCK (guard)"
7296tm "FrameTitleTextMgr"
7297)
7298)
7299seqNum (FrameSequenceNumber
7300ps "TopLeftStrategy"
7301shape (Rectangle
7302va (VaSet
7303vasetType 1
7304fg "65535,65535,65535"
7305)
7306xt "50,50,1250,1450"
7307)
7308num (Text
7309va (VaSet
7310)
7311xt "250,250,1050,1250"
7312st "1"
7313blo "250,1050"
7314tm "FrameSeqNumMgr"
7315)
7316)
7317decls (MlTextGroup
7318ps "BottomRightOffsetStrategy"
7319stg "VerticalLayoutStrategy"
7320textVec [
7321*232 (Text
7322va (VaSet
7323font "Arial,8,1"
7324)
7325xt "14100,20000,22000,21000"
7326st "Frame Declarations"
7327blo "14100,20800"
7328)
7329*233 (MLText
7330va (VaSet
7331)
7332xt "14100,21000,14100,21000"
7333tm "BdFrameDeclTextMgr"
7334)
7335]
7336)
7337style 3
7338)
7339defaultSaCptPort (CptPort
7340ps "OnEdgeStrategy"
7341shape (Triangle
7342ro 90
7343va (VaSet
7344vasetType 1
7345fg "0,65535,0"
7346)
7347xt "0,0,750,750"
7348)
7349tg (CPTG
7350ps "CptPortTextPlaceStrategy"
7351stg "VerticalLayoutStrategy"
7352f (Text
7353va (VaSet
7354)
7355xt "0,750,1800,1750"
7356st "Port"
7357blo "0,1550"
7358)
7359)
7360thePort (LogicalPort
7361decl (Decl
7362n "Port"
7363t ""
7364o 0
7365)
7366)
7367)
7368defaultSaCptPortBuffer (CptPort
7369ps "OnEdgeStrategy"
7370shape (Diamond
7371va (VaSet
7372vasetType 1
7373fg "65535,65535,65535"
7374)
7375xt "0,0,750,750"
7376)
7377tg (CPTG
7378ps "CptPortTextPlaceStrategy"
7379stg "VerticalLayoutStrategy"
7380f (Text
7381va (VaSet
7382)
7383xt "0,750,1800,1750"
7384st "Port"
7385blo "0,1550"
7386)
7387)
7388thePort (LogicalPort
7389m 3
7390decl (Decl
7391n "Port"
7392t ""
7393o 0
7394)
7395)
7396)
7397defaultDeclText (MLText
7398va (VaSet
7399font "Courier New,8,0"
7400)
7401)
7402archDeclarativeBlock (BdArchDeclBlock
7403uid 1,0
7404stg "BdArchDeclBlockLS"
7405declLabel (Text
7406uid 2,0
7407va (VaSet
7408font "Arial,8,1"
7409)
7410xt "-92000,21600,-86600,22600"
7411st "Declarations"
7412blo "-92000,22400"
7413)
7414portLabel (Text
7415uid 3,0
7416va (VaSet
7417font "Arial,8,1"
7418)
7419xt "-92000,22600,-89300,23600"
7420st "Ports:"
7421blo "-92000,23400"
7422)
7423preUserLabel (Text
7424uid 4,0
7425va (VaSet
7426isHidden 1
7427font "Arial,8,1"
7428)
7429xt "-92000,21600,-88200,22600"
7430st "Pre User:"
7431blo "-92000,22400"
7432)
7433preUserText (MLText
7434uid 5,0
7435va (VaSet
7436isHidden 1
7437font "Courier New,8,0"
7438)
7439xt "-92000,21600,-92000,21600"
7440tm "BdDeclarativeTextMgr"
7441)
7442diagSignalLabel (Text
7443uid 6,0
7444va (VaSet
7445font "Arial,8,1"
7446)
7447xt "-92000,23600,-84900,24600"
7448st "Diagram Signals:"
7449blo "-92000,24400"
7450)
7451postUserLabel (Text
7452uid 7,0
7453va (VaSet
7454isHidden 1
7455font "Arial,8,1"
7456)
7457xt "-92000,21600,-87300,22600"
7458st "Post User:"
7459blo "-92000,22400"
7460)
7461postUserText (MLText
7462uid 8,0
7463va (VaSet
7464isHidden 1
7465font "Courier New,8,0"
7466)
7467xt "-92000,21600,-92000,21600"
7468tm "BdDeclarativeTextMgr"
7469)
7470)
7471commonDM (CommonDM
7472ldm (LogicalDM
7473suid 51,0
7474usingSuid 1
7475emptyRow *234 (LEmptyRow
7476)
7477uid 54,0
7478optionalChildren [
7479*235 (RefLabelRowHdr
7480)
7481*236 (TitleRowHdr
7482)
7483*237 (FilterRowHdr
7484)
7485*238 (RefLabelColHdr
7486tm "RefLabelColHdrMgr"
7487)
7488*239 (RowExpandColHdr
7489tm "RowExpandColHdrMgr"
7490)
7491*240 (GroupColHdr
7492tm "GroupColHdrMgr"
7493)
7494*241 (NameColHdr
7495tm "BlockDiagramNameColHdrMgr"
7496)
7497*242 (ModeColHdr
7498tm "BlockDiagramModeColHdrMgr"
7499)
7500*243 (TypeColHdr
7501tm "BlockDiagramTypeColHdrMgr"
7502)
7503*244 (BoundsColHdr
7504tm "BlockDiagramBoundsColHdrMgr"
7505)
7506*245 (InitColHdr
7507tm "BlockDiagramInitColHdrMgr"
7508)
7509*246 (EolColHdr
7510tm "BlockDiagramEolColHdrMgr"
7511)
7512*247 (LeafLogPort
7513port (LogicalPort
7514m 4
7515decl (Decl
7516n "clk"
7517t "STD_LOGIC"
7518preAdd 0
7519posAdd 0
7520o 1
7521suid 1,0
7522)
7523)
7524uid 340,0
7525)
7526*248 (LeafLogPort
7527port (LogicalPort
7528m 4
7529decl (Decl
7530n "wiz_addr"
7531t "std_logic_vector"
7532b "(9 DOWNTO 0)"
7533o 2
7534suid 2,0
7535)
7536)
7537uid 342,0
7538)
7539*249 (LeafLogPort
7540port (LogicalPort
7541m 4
7542decl (Decl
7543n "wiz_data"
7544t "std_logic_vector"
7545b "(15 DOWNTO 0)"
7546o 3
7547suid 3,0
7548)
7549)
7550uid 344,0
7551)
7552*250 (LeafLogPort
7553port (LogicalPort
7554m 4
7555decl (Decl
7556n "wiz_rd"
7557t "std_logic"
7558o 4
7559suid 4,0
7560i "'1'"
7561)
7562)
7563uid 346,0
7564)
7565*251 (LeafLogPort
7566port (LogicalPort
7567m 4
7568decl (Decl
7569n "wiz_wr"
7570t "std_logic"
7571o 5
7572suid 5,0
7573i "'1'"
7574)
7575)
7576uid 348,0
7577)
7578*252 (LeafLogPort
7579port (LogicalPort
7580m 4
7581decl (Decl
7582n "sensor_cs"
7583t "std_logic_vector"
7584b "(3 DOWNTO 0)"
7585o 6
7586suid 6,0
7587)
7588)
7589uid 404,0
7590)
7591*253 (LeafLogPort
7592port (LogicalPort
7593m 4
7594decl (Decl
7595n "sclk"
7596t "std_logic"
7597o 7
7598suid 7,0
7599)
7600)
7601uid 406,0
7602)
7603*254 (LeafLogPort
7604port (LogicalPort
7605m 4
7606decl (Decl
7607n "sio"
7608t "std_logic"
7609preAdd 0
7610posAdd 0
7611o 8
7612suid 8,0
7613)
7614)
7615uid 408,0
7616)
7617*255 (LeafLogPort
7618port (LogicalPort
7619m 4
7620decl (Decl
7621n "trigger"
7622t "std_logic"
7623preAdd 0
7624posAdd 0
7625o 9
7626suid 9,0
7627)
7628)
7629uid 456,0
7630)
7631*256 (LeafLogPort
7632port (LogicalPort
7633m 4
7634decl (Decl
7635n "board_id"
7636t "std_logic_vector"
7637b "(3 downto 0)"
7638preAdd 0
7639posAdd 0
7640o 10
7641suid 10,0
7642)
7643)
7644uid 458,0
7645)
7646*257 (LeafLogPort
7647port (LogicalPort
7648m 4
7649decl (Decl
7650n "crate_id"
7651t "std_logic_vector"
7652b "(1 downto 0)"
7653o 11
7654suid 11,0
7655)
7656)
7657uid 460,0
7658)
7659*258 (LeafLogPort
7660port (LogicalPort
7661m 4
7662decl (Decl
7663n "adc_otr_array"
7664t "std_logic_vector"
7665b "(3 DOWNTO 0)"
7666o 12
7667suid 12,0
7668)
7669)
7670uid 584,0
7671)
7672*259 (LeafLogPort
7673port (LogicalPort
7674m 4
7675decl (Decl
7676n "adc_data_array"
7677t "adc_data_array_type"
7678o 13
7679suid 13,0
7680)
7681)
7682uid 586,0
7683)
7684*260 (LeafLogPort
7685port (LogicalPort
7686m 4
7687decl (Decl
7688n "adc_oeb"
7689t "std_logic"
7690preAdd 0
7691posAdd 0
7692o 14
7693suid 14,0
7694)
7695)
7696uid 588,0
7697)
7698*261 (LeafLogPort
7699port (LogicalPort
7700m 4
7701decl (Decl
7702n "adc_otr"
7703t "STD_LOGIC"
7704preAdd 0
7705posAdd 0
7706o 16
7707suid 16,0
7708)
7709)
7710uid 590,0
7711)
7712*262 (LeafLogPort
7713port (LogicalPort
7714m 4
7715decl (Decl
7716n "adc_data"
7717t "std_logic_vector"
7718b "(11 DOWNTO 0)"
7719preAdd 0
7720posAdd 0
7721o 17
7722suid 17,0
7723)
7724)
7725uid 592,0
7726)
7727*263 (LeafLogPort
7728port (LogicalPort
7729m 4
7730decl (Decl
7731n "wiz_reset"
7732t "std_logic"
7733o 21
7734suid 23,0
7735i "'1'"
7736)
7737)
7738uid 903,0
7739)
7740*264 (LeafLogPort
7741port (LogicalPort
7742m 4
7743decl (Decl
7744n "led"
7745t "std_logic_vector"
7746b "(7 DOWNTO 0)"
7747posAdd 0
7748o 22
7749suid 24,0
7750i "(OTHERS => '0')"
7751)
7752)
7753uid 905,0
7754)
7755*265 (LeafLogPort
7756port (LogicalPort
7757m 4
7758decl (Decl
7759n "wiz_cs"
7760t "std_logic"
7761o 23
7762suid 25,0
7763i "'1'"
7764)
7765)
7766uid 907,0
7767)
7768*266 (LeafLogPort
7769port (LogicalPort
7770m 4
7771decl (Decl
7772n "wiz_int"
7773t "std_logic"
7774o 24
7775suid 26,0
7776)
7777)
7778uid 909,0
7779)
7780*267 (LeafLogPort
7781port (LogicalPort
7782m 4
7783decl (Decl
7784n "dac_cs"
7785t "std_logic"
7786o 25
7787suid 27,0
7788)
7789)
7790uid 911,0
7791)
7792*268 (LeafLogPort
7793port (LogicalPort
7794m 4
7795decl (Decl
7796n "mosi"
7797t "std_logic"
7798o 26
7799suid 28,0
7800i "'0'"
7801)
7802)
7803uid 913,0
7804)
7805*269 (LeafLogPort
7806port (LogicalPort
7807m 4
7808decl (Decl
7809n "denable"
7810t "std_logic"
7811eolc "-- default domino wave off"
7812posAdd 0
7813o 27
7814suid 29,0
7815i "'0'"
7816)
7817)
7818uid 915,0
7819)
7820*270 (LeafLogPort
7821port (LogicalPort
7822m 4
7823decl (Decl
7824n "CLK_25_PS"
7825t "std_logic"
7826o 28
7827suid 30,0
7828)
7829)
7830uid 917,0
7831)
7832*271 (LeafLogPort
7833port (LogicalPort
7834m 4
7835decl (Decl
7836n "CLK_50"
7837t "std_logic"
7838o 29
7839suid 31,0
7840)
7841)
7842uid 919,0
7843)
7844*272 (LeafLogPort
7845port (LogicalPort
7846m 4
7847decl (Decl
7848n "drs_channel_id"
7849t "std_logic_vector"
7850b "(3 downto 0)"
7851o 30
7852suid 32,0
7853i "(others => '0')"
7854)
7855)
7856uid 921,0
7857)
7858*273 (LeafLogPort
7859port (LogicalPort
7860m 4
7861decl (Decl
7862n "drs_dwrite"
7863t "std_logic"
7864o 31
7865suid 33,0
7866i "'1'"
7867)
7868)
7869uid 923,0
7870)
7871*274 (LeafLogPort
7872port (LogicalPort
7873m 4
7874decl (Decl
7875n "RSRLOAD"
7876t "std_logic"
7877o 32
7878suid 34,0
7879i "'0'"
7880)
7881)
7882uid 925,0
7883)
7884*275 (LeafLogPort
7885port (LogicalPort
7886m 4
7887decl (Decl
7888n "SRCLK"
7889t "std_logic"
7890o 33
7891suid 35,0
7892i "'0'"
7893)
7894)
7895uid 927,0
7896)
7897*276 (LeafLogPort
7898port (LogicalPort
7899m 4
7900decl (Decl
7901n "SROUT_in_0"
7902t "std_logic"
7903o 30
7904suid 36,0
7905)
7906)
7907uid 929,0
7908)
7909*277 (LeafLogPort
7910port (LogicalPort
7911m 4
7912decl (Decl
7913n "SROUT_in_1"
7914t "std_logic"
7915o 31
7916suid 37,0
7917)
7918)
7919uid 931,0
7920)
7921*278 (LeafLogPort
7922port (LogicalPort
7923m 4
7924decl (Decl
7925n "SROUT_in_2"
7926t "std_logic"
7927o 32
7928suid 38,0
7929)
7930)
7931uid 933,0
7932)
7933*279 (LeafLogPort
7934port (LogicalPort
7935m 4
7936decl (Decl
7937n "SROUT_in_3"
7938t "std_logic"
7939o 33
7940suid 39,0
7941)
7942)
7943uid 935,0
7944)
7945*280 (LeafLogPort
7946port (LogicalPort
7947m 4
7948decl (Decl
7949n "SRIN_out"
7950t "std_logic"
7951o 34
7952suid 40,0
7953i "'0'"
7954)
7955)
7956uid 1541,0
7957)
7958*281 (LeafLogPort
7959port (LogicalPort
7960m 4
7961decl (Decl
7962n "amber"
7963t "std_logic"
7964o 35
7965suid 41,0
7966)
7967)
7968uid 1543,0
7969)
7970*282 (LeafLogPort
7971port (LogicalPort
7972m 4
7973decl (Decl
7974n "red"
7975t "std_logic"
7976o 36
7977suid 42,0
7978)
7979)
7980uid 1545,0
7981)
7982*283 (LeafLogPort
7983port (LogicalPort
7984m 4
7985decl (Decl
7986n "green"
7987t "std_logic"
7988o 37
7989suid 43,0
7990)
7991)
7992uid 1547,0
7993)
7994*284 (LeafLogPort
7995port (LogicalPort
7996m 4
7997decl (Decl
7998n "counter_result"
7999t "std_logic_vector"
8000b "(11 DOWNTO 0)"
8001o 38
8002suid 44,0
8003)
8004)
8005uid 1549,0
8006)
8007*285 (LeafLogPort
8008port (LogicalPort
8009m 4
8010decl (Decl
8011n "alarm_refclk_too_low"
8012t "std_logic"
8013posAdd 0
8014o 39
8015suid 45,0
8016)
8017)
8018uid 1551,0
8019)
8020*286 (LeafLogPort
8021port (LogicalPort
8022m 4
8023decl (Decl
8024n "alarm_refclk_too_high"
8025t "std_logic"
8026o 40
8027suid 46,0
8028)
8029)
8030uid 1553,0
8031)
8032*287 (LeafLogPort
8033port (LogicalPort
8034m 4
8035decl (Decl
8036n "D_T_in"
8037t "std_logic_vector"
8038b "(1 DOWNTO 0)"
8039o 41
8040suid 47,0
8041)
8042)
8043uid 1555,0
8044)
8045*288 (LeafLogPort
8046port (LogicalPort
8047m 4
8048decl (Decl
8049n "plllock_in"
8050t "std_logic_vector"
8051b "(3 DOWNTO 0)"
8052eolc "-- high level, if dominowave is running and DRS PLL locked"
8053o 43
8054suid 49,0
8055)
8056)
8057uid 1575,0
8058)
8059*289 (LeafLogPort
8060port (LogicalPort
8061lang 2
8062m 4
8063decl (Decl
8064n "ADC_CLK"
8065t "std_logic"
8066o 44
8067suid 50,0
8068)
8069)
8070uid 1690,0
8071)
8072*290 (LeafLogPort
8073port (LogicalPort
8074m 4
8075decl (Decl
8076n "REF_CLK"
8077t "STD_LOGIC"
8078o 42
8079suid 51,0
8080i "'0'"
8081)
8082)
8083uid 2003,0
8084)
8085]
8086)
8087pdm (PhysicalDM
8088displayShortBounds 1
8089editShortBounds 1
8090uid 67,0
8091optionalChildren [
8092*291 (Sheet
8093sheetRow (SheetRow
8094headerVa (MVa
8095cellColor "49152,49152,49152"
8096fontColor "0,0,0"
8097font "Tahoma,10,0"
8098)
8099cellVa (MVa
8100cellColor "65535,65535,65535"
8101fontColor "0,0,0"
8102font "Tahoma,10,0"
8103)
8104groupVa (MVa
8105cellColor "39936,56832,65280"
8106fontColor "0,0,0"
8107font "Tahoma,10,0"
8108)
8109emptyMRCItem *292 (MRCItem
8110litem &234
8111pos 44
8112dimension 20
8113)
8114uid 69,0
8115optionalChildren [
8116*293 (MRCItem
8117litem &235
8118pos 0
8119dimension 20
8120uid 70,0
8121)
8122*294 (MRCItem
8123litem &236
8124pos 1
8125dimension 23
8126uid 71,0
8127)
8128*295 (MRCItem
8129litem &237
8130pos 2
8131hidden 1
8132dimension 20
8133uid 72,0
8134)
8135*296 (MRCItem
8136litem &247
8137pos 0
8138dimension 20
8139uid 341,0
8140)
8141*297 (MRCItem
8142litem &248
8143pos 1
8144dimension 20
8145uid 343,0
8146)
8147*298 (MRCItem
8148litem &249
8149pos 2
8150dimension 20
8151uid 345,0
8152)
8153*299 (MRCItem
8154litem &250
8155pos 3
8156dimension 20
8157uid 347,0
8158)
8159*300 (MRCItem
8160litem &251
8161pos 4
8162dimension 20
8163uid 349,0
8164)
8165*301 (MRCItem
8166litem &252
8167pos 5
8168dimension 20
8169uid 405,0
8170)
8171*302 (MRCItem
8172litem &253
8173pos 6
8174dimension 20
8175uid 407,0
8176)
8177*303 (MRCItem
8178litem &254
8179pos 7
8180dimension 20
8181uid 409,0
8182)
8183*304 (MRCItem
8184litem &255
8185pos 8
8186dimension 20
8187uid 457,0
8188)
8189*305 (MRCItem
8190litem &256
8191pos 9
8192dimension 20
8193uid 459,0
8194)
8195*306 (MRCItem
8196litem &257
8197pos 10
8198dimension 20
8199uid 461,0
8200)
8201*307 (MRCItem
8202litem &258
8203pos 11
8204dimension 20
8205uid 585,0
8206)
8207*308 (MRCItem
8208litem &259
8209pos 12
8210dimension 20
8211uid 587,0
8212)
8213*309 (MRCItem
8214litem &260
8215pos 13
8216dimension 20
8217uid 589,0
8218)
8219*310 (MRCItem
8220litem &261
8221pos 14
8222dimension 20
8223uid 591,0
8224)
8225*311 (MRCItem
8226litem &262
8227pos 15
8228dimension 20
8229uid 593,0
8230)
8231*312 (MRCItem
8232litem &263
8233pos 16
8234dimension 20
8235uid 904,0
8236)
8237*313 (MRCItem
8238litem &264
8239pos 17
8240dimension 20
8241uid 906,0
8242)
8243*314 (MRCItem
8244litem &265
8245pos 18
8246dimension 20
8247uid 908,0
8248)
8249*315 (MRCItem
8250litem &266
8251pos 19
8252dimension 20
8253uid 910,0
8254)
8255*316 (MRCItem
8256litem &267
8257pos 20
8258dimension 20
8259uid 912,0
8260)
8261*317 (MRCItem
8262litem &268
8263pos 21
8264dimension 20
8265uid 914,0
8266)
8267*318 (MRCItem
8268litem &269
8269pos 22
8270dimension 20
8271uid 916,0
8272)
8273*319 (MRCItem
8274litem &270
8275pos 23
8276dimension 20
8277uid 918,0
8278)
8279*320 (MRCItem
8280litem &271
8281pos 24
8282dimension 20
8283uid 920,0
8284)
8285*321 (MRCItem
8286litem &272
8287pos 25
8288dimension 20
8289uid 922,0
8290)
8291*322 (MRCItem
8292litem &273
8293pos 26
8294dimension 20
8295uid 924,0
8296)
8297*323 (MRCItem
8298litem &274
8299pos 27
8300dimension 20
8301uid 926,0
8302)
8303*324 (MRCItem
8304litem &275
8305pos 28
8306dimension 20
8307uid 928,0
8308)
8309*325 (MRCItem
8310litem &276
8311pos 29
8312dimension 20
8313uid 930,0
8314)
8315*326 (MRCItem
8316litem &277
8317pos 30
8318dimension 20
8319uid 932,0
8320)
8321*327 (MRCItem
8322litem &278
8323pos 31
8324dimension 20
8325uid 934,0
8326)
8327*328 (MRCItem
8328litem &279
8329pos 32
8330dimension 20
8331uid 936,0
8332)
8333*329 (MRCItem
8334litem &280
8335pos 33
8336dimension 20
8337uid 1542,0
8338)
8339*330 (MRCItem
8340litem &281
8341pos 34
8342dimension 20
8343uid 1544,0
8344)
8345*331 (MRCItem
8346litem &282
8347pos 35
8348dimension 20
8349uid 1546,0
8350)
8351*332 (MRCItem
8352litem &283
8353pos 36
8354dimension 20
8355uid 1548,0
8356)
8357*333 (MRCItem
8358litem &284
8359pos 37
8360dimension 20
8361uid 1550,0
8362)
8363*334 (MRCItem
8364litem &285
8365pos 38
8366dimension 20
8367uid 1552,0
8368)
8369*335 (MRCItem
8370litem &286
8371pos 39
8372dimension 20
8373uid 1554,0
8374)
8375*336 (MRCItem
8376litem &287
8377pos 40
8378dimension 20
8379uid 1556,0
8380)
8381*337 (MRCItem
8382litem &288
8383pos 41
8384dimension 20
8385uid 1576,0
8386)
8387*338 (MRCItem
8388litem &289
8389pos 42
8390dimension 20
8391uid 1691,0
8392)
8393*339 (MRCItem
8394litem &290
8395pos 43
8396dimension 20
8397uid 2004,0
8398)
8399]
8400)
8401sheetCol (SheetCol
8402propVa (MVa
8403cellColor "0,49152,49152"
8404fontColor "0,0,0"
8405font "Tahoma,10,0"
8406textAngle 90
8407)
8408uid 73,0
8409optionalChildren [
8410*340 (MRCItem
8411litem &238
8412pos 0
8413dimension 20
8414uid 74,0
8415)
8416*341 (MRCItem
8417litem &240
8418pos 1
8419dimension 50
8420uid 75,0
8421)
8422*342 (MRCItem
8423litem &241
8424pos 2
8425dimension 100
8426uid 76,0
8427)
8428*343 (MRCItem
8429litem &242
8430pos 3
8431dimension 50
8432uid 77,0
8433)
8434*344 (MRCItem
8435litem &243
8436pos 4
8437dimension 100
8438uid 78,0
8439)
8440*345 (MRCItem
8441litem &244
8442pos 5
8443dimension 100
8444uid 79,0
8445)
8446*346 (MRCItem
8447litem &245
8448pos 6
8449dimension 50
8450uid 80,0
8451)
8452*347 (MRCItem
8453litem &246
8454pos 7
8455dimension 80
8456uid 81,0
8457)
8458]
8459)
8460fixedCol 4
8461fixedRow 2
8462name "Ports"
8463uid 68,0
8464vaOverrides [
8465]
8466)
8467]
8468)
8469uid 53,0
8470)
8471genericsCommonDM (CommonDM
8472ldm (LogicalDM
8473emptyRow *348 (LEmptyRow
8474)
8475uid 83,0
8476optionalChildren [
8477*349 (RefLabelRowHdr
8478)
8479*350 (TitleRowHdr
8480)
8481*351 (FilterRowHdr
8482)
8483*352 (RefLabelColHdr
8484tm "RefLabelColHdrMgr"
8485)
8486*353 (RowExpandColHdr
8487tm "RowExpandColHdrMgr"
8488)
8489*354 (GroupColHdr
8490tm "GroupColHdrMgr"
8491)
8492*355 (NameColHdr
8493tm "GenericNameColHdrMgr"
8494)
8495*356 (TypeColHdr
8496tm "GenericTypeColHdrMgr"
8497)
8498*357 (InitColHdr
8499tm "GenericValueColHdrMgr"
8500)
8501*358 (PragmaColHdr
8502tm "GenericPragmaColHdrMgr"
8503)
8504*359 (EolColHdr
8505tm "GenericEolColHdrMgr"
8506)
8507]
8508)
8509pdm (PhysicalDM
8510displayShortBounds 1
8511editShortBounds 1
8512uid 95,0
8513optionalChildren [
8514*360 (Sheet
8515sheetRow (SheetRow
8516headerVa (MVa
8517cellColor "49152,49152,49152"
8518fontColor "0,0,0"
8519font "Tahoma,10,0"
8520)
8521cellVa (MVa
8522cellColor "65535,65535,65535"
8523fontColor "0,0,0"
8524font "Tahoma,10,0"
8525)
8526groupVa (MVa
8527cellColor "39936,56832,65280"
8528fontColor "0,0,0"
8529font "Tahoma,10,0"
8530)
8531emptyMRCItem *361 (MRCItem
8532litem &348
8533pos 0
8534dimension 20
8535)
8536uid 97,0
8537optionalChildren [
8538*362 (MRCItem
8539litem &349
8540pos 0
8541dimension 20
8542uid 98,0
8543)
8544*363 (MRCItem
8545litem &350
8546pos 1
8547dimension 23
8548uid 99,0
8549)
8550*364 (MRCItem
8551litem &351
8552pos 2
8553hidden 1
8554dimension 20
8555uid 100,0
8556)
8557]
8558)
8559sheetCol (SheetCol
8560propVa (MVa
8561cellColor "0,49152,49152"
8562fontColor "0,0,0"
8563font "Tahoma,10,0"
8564textAngle 90
8565)
8566uid 101,0
8567optionalChildren [
8568*365 (MRCItem
8569litem &352
8570pos 0
8571dimension 20
8572uid 102,0
8573)
8574*366 (MRCItem
8575litem &354
8576pos 1
8577dimension 50
8578uid 103,0
8579)
8580*367 (MRCItem
8581litem &355
8582pos 2
8583dimension 100
8584uid 104,0
8585)
8586*368 (MRCItem
8587litem &356
8588pos 3
8589dimension 100
8590uid 105,0
8591)
8592*369 (MRCItem
8593litem &357
8594pos 4
8595dimension 50
8596uid 106,0
8597)
8598*370 (MRCItem
8599litem &358
8600pos 5
8601dimension 50
8602uid 107,0
8603)
8604*371 (MRCItem
8605litem &359
8606pos 6
8607dimension 80
8608uid 108,0
8609)
8610]
8611)
8612fixedCol 3
8613fixedRow 2
8614name "Ports"
8615uid 96,0
8616vaOverrides [
8617]
8618)
8619]
8620)
8621uid 82,0
8622type 1
8623)
8624activeModelName "BlockDiag"
8625)
Note: See TracBrowser for help on using the repository browser.