source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd @ 10240

Last change on this file since 10240 was 10240, checked in by neise, 9 years ago
File size: 110.6 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8)
9(DmPackageRef
10library "ieee"
11unitName "std_logic_arith"
12)
13(DmPackageRef
14library "ieee"
15unitName "std_logic_unsigned"
16)
17(DmPackageRef
18library "FACT_FAD_lib"
19unitName "fad_definitions"
20)
21(DmPackageRef
22library "ieee"
23unitName "std_logic_textio"
24)
25(DmPackageRef
26library "std"
27unitName "textio"
28)
29]
30instances [
31(Instance
32name "I_mainTB_FPGA"
33duLibraryName "FACT_FAD_lib"
34duName "FAD_main"
35elements [
36(GiElement
37name "RAMADDRWIDTH64b"
38type "integer"
39value "15"
40)
41]
42mwi 0
43uid 233,0
44)
45(Instance
46name "I_mainTB_clock"
47duLibraryName "FACT_FAD_TB_lib"
48duName "clock_generator"
49elements [
50(GiElement
51name "clock_period"
52type "time"
53value "20 ns"
54)
55(GiElement
56name "reset_time"
57type "time"
58value "50 ns"
59)
60]
61mwi 0
62uid 274,0
63)
64(Instance
65name "I_mainTB_max6662"
66duLibraryName "FACT_FAD_TB_lib"
67duName "max6662_emulator"
68elements [
69(GiElement
70name "DRS_TEMPERATURE"
71type "integer"
72value "51"
73)
74]
75mwi 0
76uid 362,0
77)
78(Instance
79name "I_mainTB_trigger"
80duLibraryName "FACT_FAD_TB_lib"
81duName "trigger_generator"
82elements [
83(GiElement
84name "TRIGGER_RATE"
85type "time"
86value "1 ms"
87)
88(GiElement
89name "PULSE_WIDTH"
90type "time"
91value "20 ns"
92)
93]
94mwi 0
95uid 414,0
96)
97(Instance
98name "I_mainTB_adc"
99duLibraryName "FACT_FAD_TB_lib"
100duName "adc_emulator"
101elements [
102(GiElement
103name "INPUT_FILE"
104type "string"
105value "\"../memory_files/analog_input_ch0.txt\""
106)
107]
108mwi 0
109uid 508,0
110)
111(Instance
112name "I_mainTB_clock1"
113duLibraryName "FACT_FAD_TB_lib"
114duName "clock_generator"
115elements [
116(GiElement
117name "clock_period"
118type "time"
119value "1 us"
120)
121(GiElement
122name "reset_time"
123type "time"
124value "1 us"
125)
126]
127mwi 0
128uid 1509,0
129)
130(Instance
131name "I_mainTB_w5300"
132duLibraryName "FACT_FAD_TB_lib"
133duName "w5300_emulator"
134elements [
135]
136mwi 0
137uid 2336,0
138)
139]
140embeddedInstances [
141(EmbeddedInstance
142name "eb_mainTB_ID"
143number "1"
144)
145(EmbeddedInstance
146name "eb_mainTB_adc"
147number "2"
148)
149(EmbeddedInstance
150name "eb_mainTB_adc1"
151number "3"
152)
153]
154libraryRefs [
155"ieee"
156"FACT_FAD_lib"
157"std"
158]
159)
160version "29.1"
161appVersion "2009.1 (Build 12)"
162noEmbeddedEditors 1
163model (BlockDiag
164VExpander (VariableExpander
165vvMap [
166(vvPair
167variable "HDLDir"
168value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
169)
170(vvPair
171variable "HDSDir"
172value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
173)
174(vvPair
175variable "SideDataDesignDir"
176value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
177)
178(vvPair
179variable "SideDataUserDir"
180value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
181)
182(vvPair
183variable "SourceDir"
184value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
185)
186(vvPair
187variable "appl"
188value "HDL Designer"
189)
190(vvPair
191variable "arch_name"
192value "struct"
193)
194(vvPair
195variable "config"
196value "%(unit)_%(view)_config"
197)
198(vvPair
199variable "d"
200value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
201)
202(vvPair
203variable "d_logical"
204value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
205)
206(vvPair
207variable "date"
208value "04.03.2011"
209)
210(vvPair
211variable "day"
212value "Fr"
213)
214(vvPair
215variable "day_long"
216value "Freitag"
217)
218(vvPair
219variable "dd"
220value "04"
221)
222(vvPair
223variable "entity_name"
224value "fad_main_tb"
225)
226(vvPair
227variable "ext"
228value "<TBD>"
229)
230(vvPair
231variable "f"
232value "struct.bd"
233)
234(vvPair
235variable "f_logical"
236value "struct.bd"
237)
238(vvPair
239variable "f_noext"
240value "struct"
241)
242(vvPair
243variable "group"
244value "UNKNOWN"
245)
246(vvPair
247variable "host"
248value "IHP110"
249)
250(vvPair
251variable "language"
252value "VHDL"
253)
254(vvPair
255variable "library"
256value "FACT_FAD_TB_lib"
257)
258(vvPair
259variable "library_downstream_HdsLintPlugin"
260value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
261)
262(vvPair
263variable "library_downstream_ISEPARInvoke"
264value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
265)
266(vvPair
267variable "library_downstream_ImpactInvoke"
268value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
269)
270(vvPair
271variable "library_downstream_ModelSimCompiler"
272value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
273)
274(vvPair
275variable "library_downstream_XSTDataPrep"
276value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
277)
278(vvPair
279variable "mm"
280value "03"
281)
282(vvPair
283variable "module_name"
284value "fad_main_tb"
285)
286(vvPair
287variable "month"
288value "Mrz"
289)
290(vvPair
291variable "month_long"
292value "März"
293)
294(vvPair
295variable "p"
296value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
297)
298(vvPair
299variable "p_logical"
300value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
301)
302(vvPair
303variable "package_name"
304value "<Undefined Variable>"
305)
306(vvPair
307variable "project_name"
308value "FACT_FAD"
309)
310(vvPair
311variable "series"
312value "HDL Designer Series"
313)
314(vvPair
315variable "task_DesignCompilerPath"
316value "<TBD>"
317)
318(vvPair
319variable "task_LeonardoPath"
320value "<TBD>"
321)
322(vvPair
323variable "task_ModelSimPath"
324value "D:\\modeltech_6.5e\\win32"
325)
326(vvPair
327variable "task_NC-SimPath"
328value "<TBD>"
329)
330(vvPair
331variable "task_PrecisionRTLPath"
332value "<TBD>"
333)
334(vvPair
335variable "task_QuestaSimPath"
336value "<TBD>"
337)
338(vvPair
339variable "task_VCSPath"
340value "<TBD>"
341)
342(vvPair
343variable "this_ext"
344value "bd"
345)
346(vvPair
347variable "this_file"
348value "struct"
349)
350(vvPair
351variable "this_file_logical"
352value "struct"
353)
354(vvPair
355variable "time"
356value "11:37:19"
357)
358(vvPair
359variable "unit"
360value "fad_main_tb"
361)
362(vvPair
363variable "user"
364value "daqct3"
365)
366(vvPair
367variable "version"
368value "2009.1 (Build 12)"
369)
370(vvPair
371variable "view"
372value "struct"
373)
374(vvPair
375variable "year"
376value "2011"
377)
378(vvPair
379variable "yy"
380value "11"
381)
382]
383)
384LanguageMgr "VhdlLangMgr"
385uid 52,0
386optionalChildren [
387*1 (Grouping
388uid 9,0
389optionalChildren [
390*2 (CommentText
391uid 11,0
392shape (Rectangle
393uid 12,0
394sl 0
395va (VaSet
396vasetType 1
397fg "65280,65280,46080"
398)
399xt "109000,97000,126000,98000"
400)
401oxt "18000,70000,35000,71000"
402text (MLText
403uid 13,0
404va (VaSet
405fg "0,0,32768"
406bg "0,0,32768"
407)
408xt "109200,97000,120300,98000"
409st "
410by %user on %dd %month %year
411"
412tm "CommentText"
413wrapOption 3
414visibleHeight 1000
415visibleWidth 17000
416)
417position 1
418ignorePrefs 1
419titleBlock 1
420)
421*3 (CommentText
422uid 14,0
423shape (Rectangle
424uid 15,0
425sl 0
426va (VaSet
427vasetType 1
428fg "65280,65280,46080"
429)
430xt "126000,93000,130000,94000"
431)
432oxt "35000,66000,39000,67000"
433text (MLText
434uid 16,0
435va (VaSet
436fg "0,0,32768"
437bg "0,0,32768"
438)
439xt "126200,93000,129500,94000"
440st "
441Project:
442"
443tm "CommentText"
444wrapOption 3
445visibleHeight 1000
446visibleWidth 4000
447)
448position 1
449ignorePrefs 1
450titleBlock 1
451)
452*4 (CommentText
453uid 17,0
454shape (Rectangle
455uid 18,0
456sl 0
457va (VaSet
458vasetType 1
459fg "65280,65280,46080"
460)
461xt "109000,95000,126000,96000"
462)
463oxt "18000,68000,35000,69000"
464text (MLText
465uid 19,0
466va (VaSet
467fg "0,0,32768"
468bg "0,0,32768"
469)
470xt "109200,95000,120100,96000"
471st "
472<enter diagram title here>
473"
474tm "CommentText"
475wrapOption 3
476visibleHeight 1000
477visibleWidth 17000
478)
479position 1
480ignorePrefs 1
481titleBlock 1
482)
483*5 (CommentText
484uid 20,0
485shape (Rectangle
486uid 21,0
487sl 0
488va (VaSet
489vasetType 1
490fg "65280,65280,46080"
491)
492xt "105000,95000,109000,96000"
493)
494oxt "14000,68000,18000,69000"
495text (MLText
496uid 22,0
497va (VaSet
498fg "0,0,32768"
499bg "0,0,32768"
500)
501xt "105200,95000,107500,96000"
502st "
503Title:
504"
505tm "CommentText"
506wrapOption 3
507visibleHeight 1000
508visibleWidth 4000
509)
510position 1
511ignorePrefs 1
512titleBlock 1
513)
514*6 (CommentText
515uid 23,0
516shape (Rectangle
517uid 24,0
518sl 0
519va (VaSet
520vasetType 1
521fg "65280,65280,46080"
522)
523xt "126000,94000,146000,98000"
524)
525oxt "35000,67000,55000,71000"
526text (MLText
527uid 25,0
528va (VaSet
529fg "0,0,32768"
530bg "0,0,32768"
531)
532xt "126200,94200,136000,95200"
533st "
534<enter comments here>
535"
536tm "CommentText"
537wrapOption 3
538visibleHeight 4000
539visibleWidth 20000
540)
541ignorePrefs 1
542titleBlock 1
543)
544*7 (CommentText
545uid 26,0
546shape (Rectangle
547uid 27,0
548sl 0
549va (VaSet
550vasetType 1
551fg "65280,65280,46080"
552)
553xt "130000,93000,146000,94000"
554)
555oxt "39000,66000,55000,67000"
556text (MLText
557uid 28,0
558va (VaSet
559fg "0,0,32768"
560bg "0,0,32768"
561)
562xt "130200,93000,134900,94000"
563st "
564%project_name
565"
566tm "CommentText"
567wrapOption 3
568visibleHeight 1000
569visibleWidth 16000
570)
571position 1
572ignorePrefs 1
573titleBlock 1
574)
575*8 (CommentText
576uid 29,0
577shape (Rectangle
578uid 30,0
579sl 0
580va (VaSet
581vasetType 1
582fg "65280,65280,46080"
583)
584xt "105000,93000,126000,95000"
585)
586oxt "14000,66000,35000,68000"
587text (MLText
588uid 31,0
589va (VaSet
590fg "32768,0,0"
591)
592xt "112450,93000,118550,95000"
593st "
594TU Dortmund
595Physik / EE
596"
597ju 0
598tm "CommentText"
599wrapOption 3
600visibleHeight 2000
601visibleWidth 21000
602)
603position 1
604ignorePrefs 1
605titleBlock 1
606)
607*9 (CommentText
608uid 32,0
609shape (Rectangle
610uid 33,0
611sl 0
612va (VaSet
613vasetType 1
614fg "65280,65280,46080"
615)
616xt "105000,96000,109000,97000"
617)
618oxt "14000,69000,18000,70000"
619text (MLText
620uid 34,0
621va (VaSet
622fg "0,0,32768"
623bg "0,0,32768"
624)
625xt "105200,96000,107500,97000"
626st "
627Path:
628"
629tm "CommentText"
630wrapOption 3
631visibleHeight 1000
632visibleWidth 4000
633)
634position 1
635ignorePrefs 1
636titleBlock 1
637)
638*10 (CommentText
639uid 35,0
640shape (Rectangle
641uid 36,0
642sl 0
643va (VaSet
644vasetType 1
645fg "65280,65280,46080"
646)
647xt "105000,97000,109000,98000"
648)
649oxt "14000,70000,18000,71000"
650text (MLText
651uid 37,0
652va (VaSet
653fg "0,0,32768"
654bg "0,0,32768"
655)
656xt "105200,97000,108300,98000"
657st "
658Edited:
659"
660tm "CommentText"
661wrapOption 3
662visibleHeight 1000
663visibleWidth 4000
664)
665position 1
666ignorePrefs 1
667titleBlock 1
668)
669*11 (CommentText
670uid 38,0
671shape (Rectangle
672uid 39,0
673sl 0
674va (VaSet
675vasetType 1
676fg "65280,65280,46080"
677)
678xt "109000,96000,126000,97000"
679)
680oxt "18000,69000,35000,70000"
681text (MLText
682uid 40,0
683va (VaSet
684fg "0,0,32768"
685bg "0,0,32768"
686)
687xt "109200,96000,125800,97000"
688st "
689%library/%unit/%view
690"
691tm "CommentText"
692wrapOption 3
693visibleHeight 1000
694visibleWidth 17000
695)
696position 1
697ignorePrefs 1
698titleBlock 1
699)
700]
701shape (GroupingShape
702uid 10,0
703va (VaSet
704vasetType 1
705fg "65535,65535,65535"
706lineStyle 2
707lineWidth 2
708)
709xt "105000,93000,146000,98000"
710)
711oxt "14000,66000,55000,71000"
712)
713*12 (SaComponent
714uid 233,0
715optionalChildren [
716*13 (CptPort
717uid 109,0
718ps "OnEdgeStrategy"
719shape (Triangle
720uid 110,0
721ro 90
722va (VaSet
723vasetType 1
724fg "0,65535,0"
725)
726xt "109000,23625,109750,24375"
727)
728tg (CPTG
729uid 111,0
730ps "CptPortTextPlaceStrategy"
731stg "RightVerticalLayoutStrategy"
732f (Text
733uid 112,0
734va (VaSet
735)
736xt "104400,23500,108000,24500"
737st "wiz_reset"
738ju 2
739blo "108000,24300"
740)
741)
742thePort (LogicalPort
743m 1
744decl (Decl
745n "wiz_reset"
746t "std_logic"
747o 39
748suid 2,0
749i "'1'"
750)
751)
752)
753*14 (CptPort
754uid 113,0
755ps "OnEdgeStrategy"
756shape (Triangle
757uid 114,0
758ro 90
759va (VaSet
760vasetType 1
761fg "0,65535,0"
762)
763xt "109000,69625,109750,70375"
764)
765tg (CPTG
766uid 115,0
767ps "CptPortTextPlaceStrategy"
768stg "RightVerticalLayoutStrategy"
769f (Text
770uid 116,0
771va (VaSet
772)
773xt "104000,69500,108000,70500"
774st "led : (7:0)"
775ju 2
776blo "108000,70300"
777)
778)
779thePort (LogicalPort
780m 1
781decl (Decl
782n "led"
783t "std_logic_vector"
784b "(7 DOWNTO 0)"
785posAdd 0
786o 31
787suid 7,0
788i "(OTHERS => '0')"
789)
790)
791)
792*15 (CptPort
793uid 117,0
794ps "OnEdgeStrategy"
795shape (Triangle
796uid 118,0
797ro 90
798va (VaSet
799vasetType 1
800fg "0,65535,0"
801)
802xt "80250,31625,81000,32375"
803)
804tg (CPTG
805uid 119,0
806ps "CptPortTextPlaceStrategy"
807stg "VerticalLayoutStrategy"
808f (Text
809uid 120,0
810va (VaSet
811)
812xt "82000,31500,84800,32500"
813st "trigger"
814blo "82000,32300"
815)
816)
817thePort (LogicalPort
818decl (Decl
819n "trigger"
820t "std_logic"
821preAdd 0
822posAdd 0
823o 13
824suid 18,0
825)
826)
827)
828*16 (CptPort
829uid 121,0
830ps "OnEdgeStrategy"
831shape (Triangle
832uid 122,0
833ro 270
834va (VaSet
835vasetType 1
836fg "0,65535,0"
837)
838xt "80250,42625,81000,43375"
839)
840tg (CPTG
841uid 123,0
842ps "CptPortTextPlaceStrategy"
843stg "VerticalLayoutStrategy"
844f (Text
845uid 124,0
846va (VaSet
847)
848xt "82000,42500,85200,43500"
849st "adc_oeb"
850blo "82000,43300"
851)
852)
853thePort (LogicalPort
854m 1
855decl (Decl
856n "adc_oeb"
857t "std_logic"
858o 21
859suid 21,0
860i "'1'"
861)
862)
863)
864*17 (CptPort
865uid 125,0
866ps "OnEdgeStrategy"
867shape (Triangle
868uid 126,0
869ro 90
870va (VaSet
871vasetType 1
872fg "0,65535,0"
873)
874xt "80250,33625,81000,34375"
875)
876tg (CPTG
877uid 127,0
878ps "CptPortTextPlaceStrategy"
879stg "VerticalLayoutStrategy"
880f (Text
881uid 128,0
882va (VaSet
883)
884xt "82000,33500,87900,34500"
885st "board_id : (3:0)"
886blo "82000,34300"
887)
888)
889thePort (LogicalPort
890decl (Decl
891n "board_id"
892t "std_logic_vector"
893b "(3 DOWNTO 0)"
894o 9
895suid 24,0
896)
897)
898)
899*18 (CptPort
900uid 129,0
901ps "OnEdgeStrategy"
902shape (Triangle
903uid 130,0
904ro 90
905va (VaSet
906vasetType 1
907fg "0,65535,0"
908)
909xt "80250,34625,81000,35375"
910)
911tg (CPTG
912uid 131,0
913ps "CptPortTextPlaceStrategy"
914stg "VerticalLayoutStrategy"
915f (Text
916uid 132,0
917va (VaSet
918)
919xt "82000,34500,87700,35500"
920st "crate_id : (1:0)"
921blo "82000,35300"
922)
923)
924thePort (LogicalPort
925decl (Decl
926n "crate_id"
927t "std_logic_vector"
928b "(1 DOWNTO 0)"
929o 10
930suid 25,0
931)
932)
933)
934*19 (CptPort
935uid 133,0
936ps "OnEdgeStrategy"
937shape (Triangle
938uid 134,0
939ro 90
940va (VaSet
941vasetType 1
942fg "0,65535,0"
943)
944xt "109000,20625,109750,21375"
945)
946tg (CPTG
947uid 135,0
948ps "CptPortTextPlaceStrategy"
949stg "RightVerticalLayoutStrategy"
950f (Text
951uid 136,0
952va (VaSet
953)
954xt "102000,20500,108000,21500"
955st "wiz_addr : (9:0)"
956ju 2
957blo "108000,21300"
958)
959)
960thePort (LogicalPort
961m 1
962decl (Decl
963n "wiz_addr"
964t "std_logic_vector"
965b "(9 DOWNTO 0)"
966o 36
967suid 26,0
968)
969)
970)
971*20 (CptPort
972uid 137,0
973ps "OnEdgeStrategy"
974shape (Diamond
975uid 138,0
976ro 90
977va (VaSet
978vasetType 1
979fg "0,65535,0"
980)
981xt "109000,21625,109750,22375"
982)
983tg (CPTG
984uid 139,0
985ps "CptPortTextPlaceStrategy"
986stg "RightVerticalLayoutStrategy"
987f (Text
988uid 140,0
989va (VaSet
990)
991xt "101700,21500,108000,22500"
992st "wiz_data : (15:0)"
993ju 2
994blo "108000,22300"
995)
996)
997thePort (LogicalPort
998m 2
999decl (Decl
1000n "wiz_data"
1001t "std_logic_vector"
1002b "(15 DOWNTO 0)"
1003o 42
1004suid 27,0
1005)
1006)
1007)
1008*21 (CptPort
1009uid 141,0
1010ps "OnEdgeStrategy"
1011shape (Triangle
1012uid 142,0
1013ro 90
1014va (VaSet
1015vasetType 1
1016fg "0,65535,0"
1017)
1018xt "109000,27625,109750,28375"
1019)
1020tg (CPTG
1021uid 143,0
1022ps "CptPortTextPlaceStrategy"
1023stg "RightVerticalLayoutStrategy"
1024f (Text
1025uid 144,0
1026va (VaSet
1027)
1028xt "105300,27500,108000,28500"
1029st "wiz_cs"
1030ju 2
1031blo "108000,28300"
1032)
1033)
1034thePort (LogicalPort
1035m 1
1036decl (Decl
1037n "wiz_cs"
1038t "std_logic"
1039o 37
1040suid 28,0
1041i "'1'"
1042)
1043)
1044)
1045*22 (CptPort
1046uid 145,0
1047ps "OnEdgeStrategy"
1048shape (Triangle
1049uid 146,0
1050ro 90
1051va (VaSet
1052vasetType 1
1053fg "0,65535,0"
1054)
1055xt "109000,25625,109750,26375"
1056)
1057tg (CPTG
1058uid 147,0
1059ps "CptPortTextPlaceStrategy"
1060stg "RightVerticalLayoutStrategy"
1061f (Text
1062uid 148,0
1063va (VaSet
1064)
1065xt "105300,25500,108000,26500"
1066st "wiz_wr"
1067ju 2
1068blo "108000,26300"
1069)
1070)
1071thePort (LogicalPort
1072m 1
1073decl (Decl
1074n "wiz_wr"
1075t "std_logic"
1076o 40
1077suid 29,0
1078i "'1'"
1079)
1080)
1081)
1082*23 (CptPort
1083uid 149,0
1084ps "OnEdgeStrategy"
1085shape (Triangle
1086uid 150,0
1087ro 90
1088va (VaSet
1089vasetType 1
1090fg "0,65535,0"
1091)
1092xt "109000,24625,109750,25375"
1093)
1094tg (CPTG
1095uid 151,0
1096ps "CptPortTextPlaceStrategy"
1097stg "RightVerticalLayoutStrategy"
1098f (Text
1099uid 152,0
1100va (VaSet
1101)
1102xt "105400,24500,108000,25500"
1103st "wiz_rd"
1104ju 2
1105blo "108000,25300"
1106)
1107)
1108thePort (LogicalPort
1109m 1
1110decl (Decl
1111n "wiz_rd"
1112t "std_logic"
1113o 38
1114suid 30,0
1115i "'1'"
1116)
1117)
1118)
1119*24 (CptPort
1120uid 153,0
1121ps "OnEdgeStrategy"
1122shape (Triangle
1123uid 154,0
1124ro 270
1125va (VaSet
1126vasetType 1
1127fg "0,65535,0"
1128)
1129xt "109000,26625,109750,27375"
1130)
1131tg (CPTG
1132uid 155,0
1133ps "CptPortTextPlaceStrategy"
1134stg "RightVerticalLayoutStrategy"
1135f (Text
1136uid 156,0
1137va (VaSet
1138)
1139xt "105300,26500,108000,27500"
1140st "wiz_int"
1141ju 2
1142blo "108000,27300"
1143)
1144)
1145thePort (LogicalPort
1146decl (Decl
1147n "wiz_int"
1148t "std_logic"
1149o 14
1150suid 31,0
1151)
1152)
1153)
1154*25 (CptPort
1155uid 157,0
1156ps "OnEdgeStrategy"
1157shape (Triangle
1158uid 158,0
1159ro 270
1160va (VaSet
1161vasetType 1
1162fg "0,65535,0"
1163)
1164xt "80250,22625,81000,23375"
1165)
1166tg (CPTG
1167uid 159,0
1168ps "CptPortTextPlaceStrategy"
1169stg "VerticalLayoutStrategy"
1170f (Text
1171uid 160,0
1172va (VaSet
1173)
1174xt "82000,22500,86500,23500"
1175st "CLK_25_PS"
1176blo "82000,23300"
1177)
1178)
1179thePort (LogicalPort
1180m 1
1181decl (Decl
1182n "CLK_25_PS"
1183t "std_logic"
1184o 16
1185suid 35,0
1186)
1187)
1188)
1189*26 (CptPort
1190uid 161,0
1191ps "OnEdgeStrategy"
1192shape (Triangle
1193uid 162,0
1194ro 270
1195va (VaSet
1196vasetType 1
1197fg "0,65535,0"
1198)
1199xt "80250,21625,81000,22375"
1200)
1201tg (CPTG
1202uid 163,0
1203ps "CptPortTextPlaceStrategy"
1204stg "VerticalLayoutStrategy"
1205f (Text
1206uid 164,0
1207va (VaSet
1208)
1209xt "82000,21500,85100,22500"
1210st "CLK_50"
1211blo "82000,22300"
1212)
1213)
1214thePort (LogicalPort
1215m 1
1216decl (Decl
1217n "CLK_50"
1218t "std_logic"
1219preAdd 0
1220posAdd 0
1221o 17
1222suid 37,0
1223)
1224)
1225)
1226*27 (CptPort
1227uid 165,0
1228ps "OnEdgeStrategy"
1229shape (Triangle
1230uid 166,0
1231ro 90
1232va (VaSet
1233vasetType 1
1234fg "0,65535,0"
1235)
1236xt "80250,20625,81000,21375"
1237)
1238tg (CPTG
1239uid 167,0
1240ps "CptPortTextPlaceStrategy"
1241stg "VerticalLayoutStrategy"
1242f (Text
1243uid 168,0
1244va (VaSet
1245)
1246xt "82000,20500,83900,21500"
1247st "CLK"
1248blo "82000,21300"
1249)
1250)
1251thePort (LogicalPort
1252decl (Decl
1253n "CLK"
1254t "std_logic"
1255o 1
1256suid 38,0
1257)
1258)
1259)
1260*28 (CptPort
1261uid 169,0
1262ps "OnEdgeStrategy"
1263shape (Triangle
1264uid 170,0
1265ro 90
1266va (VaSet
1267vasetType 1
1268fg "0,65535,0"
1269)
1270xt "80250,41625,81000,42375"
1271)
1272tg (CPTG
1273uid 171,0
1274ps "CptPortTextPlaceStrategy"
1275stg "VerticalLayoutStrategy"
1276f (Text
1277uid 172,0
1278va (VaSet
1279)
1280xt "82000,41500,90000,42500"
1281st "adc_otr_array : (3:0)"
1282blo "82000,42300"
1283)
1284)
1285thePort (LogicalPort
1286decl (Decl
1287n "adc_otr_array"
1288t "std_logic_vector"
1289b "(3 DOWNTO 0)"
1290o 8
1291suid 40,0
1292)
1293)
1294)
1295*29 (CptPort
1296uid 173,0
1297ps "OnEdgeStrategy"
1298shape (Triangle
1299uid 174,0
1300ro 90
1301va (VaSet
1302vasetType 1
1303fg "0,65535,0"
1304)
1305xt "80250,47625,81000,48375"
1306)
1307tg (CPTG
1308uid 175,0
1309ps "CptPortTextPlaceStrategy"
1310stg "VerticalLayoutStrategy"
1311f (Text
1312uid 176,0
1313va (VaSet
1314)
1315xt "82000,47500,87900,48500"
1316st "adc_data_array"
1317blo "82000,48300"
1318)
1319)
1320thePort (LogicalPort
1321decl (Decl
1322n "adc_data_array"
1323t "adc_data_array_type"
1324o 7
1325suid 41,0
1326)
1327)
1328)
1329*30 (CptPort
1330uid 177,0
1331ps "OnEdgeStrategy"
1332shape (Triangle
1333uid 178,0
1334ro 270
1335va (VaSet
1336vasetType 1
1337fg "0,65535,0"
1338)
1339xt "80250,61625,81000,62375"
1340)
1341tg (CPTG
1342uid 179,0
1343ps "CptPortTextPlaceStrategy"
1344stg "VerticalLayoutStrategy"
1345f (Text
1346uid 180,0
1347va (VaSet
1348)
1349xt "82000,61500,90500,62500"
1350st "drs_channel_id : (3:0)"
1351blo "82000,62300"
1352)
1353)
1354thePort (LogicalPort
1355m 1
1356decl (Decl
1357n "drs_channel_id"
1358t "std_logic_vector"
1359b "(3 downto 0)"
1360o 28
1361suid 48,0
1362i "(others => '0')"
1363)
1364)
1365)
1366*31 (CptPort
1367uid 181,0
1368ps "OnEdgeStrategy"
1369shape (Triangle
1370uid 182,0
1371ro 270
1372va (VaSet
1373vasetType 1
1374fg "0,65535,0"
1375)
1376xt "80250,66625,81000,67375"
1377)
1378tg (CPTG
1379uid 183,0
1380ps "CptPortTextPlaceStrategy"
1381stg "VerticalLayoutStrategy"
1382f (Text
1383uid 184,0
1384va (VaSet
1385)
1386xt "82000,66500,86300,67500"
1387st "drs_dwrite"
1388blo "82000,67300"
1389)
1390)
1391thePort (LogicalPort
1392m 1
1393decl (Decl
1394n "drs_dwrite"
1395t "std_logic"
1396o 29
1397suid 49,0
1398i "'1'"
1399)
1400)
1401)
1402*32 (CptPort
1403uid 185,0
1404ps "OnEdgeStrategy"
1405shape (Triangle
1406uid 186,0
1407ro 90
1408va (VaSet
1409vasetType 1
1410fg "0,65535,0"
1411)
1412xt "80250,57625,81000,58375"
1413)
1414tg (CPTG
1415uid 187,0
1416ps "CptPortTextPlaceStrategy"
1417stg "VerticalLayoutStrategy"
1418f (Text
1419uid 188,0
1420va (VaSet
1421)
1422xt "82000,57500,87400,58500"
1423st "SROUT_in_0"
1424blo "82000,58300"
1425)
1426)
1427thePort (LogicalPort
1428decl (Decl
1429n "SROUT_in_0"
1430t "std_logic"
1431o 3
1432suid 52,0
1433)
1434)
1435)
1436*33 (CptPort
1437uid 189,0
1438ps "OnEdgeStrategy"
1439shape (Triangle
1440uid 190,0
1441ro 90
1442va (VaSet
1443vasetType 1
1444fg "0,65535,0"
1445)
1446xt "80250,58625,81000,59375"
1447)
1448tg (CPTG
1449uid 191,0
1450ps "CptPortTextPlaceStrategy"
1451stg "VerticalLayoutStrategy"
1452f (Text
1453uid 192,0
1454va (VaSet
1455)
1456xt "82000,58500,87400,59500"
1457st "SROUT_in_1"
1458blo "82000,59300"
1459)
1460)
1461thePort (LogicalPort
1462decl (Decl
1463n "SROUT_in_1"
1464t "std_logic"
1465o 4
1466suid 53,0
1467)
1468)
1469)
1470*34 (CptPort
1471uid 193,0
1472ps "OnEdgeStrategy"
1473shape (Triangle
1474uid 194,0
1475ro 90
1476va (VaSet
1477vasetType 1
1478fg "0,65535,0"
1479)
1480xt "80250,59625,81000,60375"
1481)
1482tg (CPTG
1483uid 195,0
1484ps "CptPortTextPlaceStrategy"
1485stg "VerticalLayoutStrategy"
1486f (Text
1487uid 196,0
1488va (VaSet
1489)
1490xt "82000,59500,87400,60500"
1491st "SROUT_in_2"
1492blo "82000,60300"
1493)
1494)
1495thePort (LogicalPort
1496decl (Decl
1497n "SROUT_in_2"
1498t "std_logic"
1499o 5
1500suid 54,0
1501)
1502)
1503)
1504*35 (CptPort
1505uid 197,0
1506ps "OnEdgeStrategy"
1507shape (Triangle
1508uid 198,0
1509ro 90
1510va (VaSet
1511vasetType 1
1512fg "0,65535,0"
1513)
1514xt "80250,60625,81000,61375"
1515)
1516tg (CPTG
1517uid 199,0
1518ps "CptPortTextPlaceStrategy"
1519stg "VerticalLayoutStrategy"
1520f (Text
1521uid 200,0
1522va (VaSet
1523)
1524xt "82000,60500,87400,61500"
1525st "SROUT_in_3"
1526blo "82000,61300"
1527)
1528)
1529thePort (LogicalPort
1530decl (Decl
1531n "SROUT_in_3"
1532t "std_logic"
1533o 6
1534suid 55,0
1535)
1536)
1537)
1538*36 (CptPort
1539uid 201,0
1540ps "OnEdgeStrategy"
1541shape (Triangle
1542uid 202,0
1543ro 270
1544va (VaSet
1545vasetType 1
1546fg "0,65535,0"
1547)
1548xt "80250,63625,81000,64375"
1549)
1550tg (CPTG
1551uid 203,0
1552ps "CptPortTextPlaceStrategy"
1553stg "VerticalLayoutStrategy"
1554f (Text
1555uid 204,0
1556va (VaSet
1557)
1558xt "82000,63500,86200,64500"
1559st "RSRLOAD"
1560blo "82000,64300"
1561)
1562)
1563thePort (LogicalPort
1564m 1
1565decl (Decl
1566n "RSRLOAD"
1567t "std_logic"
1568o 18
1569suid 56,0
1570i "'0'"
1571)
1572)
1573)
1574*37 (CptPort
1575uid 205,0
1576ps "OnEdgeStrategy"
1577shape (Triangle
1578uid 206,0
1579ro 270
1580va (VaSet
1581vasetType 1
1582fg "0,65535,0"
1583)
1584xt "80250,64625,81000,65375"
1585)
1586tg (CPTG
1587uid 207,0
1588ps "CptPortTextPlaceStrategy"
1589stg "VerticalLayoutStrategy"
1590f (Text
1591uid 208,0
1592va (VaSet
1593)
1594xt "82000,64500,85000,65500"
1595st "SRCLK"
1596blo "82000,65300"
1597)
1598)
1599thePort (LogicalPort
1600m 1
1601decl (Decl
1602n "SRCLK"
1603t "std_logic"
1604o 19
1605suid 57,0
1606i "'0'"
1607)
1608)
1609)
1610*38 (CptPort
1611uid 209,0
1612ps "OnEdgeStrategy"
1613shape (Triangle
1614uid 210,0
1615ro 90
1616va (VaSet
1617vasetType 1
1618fg "0,65535,0"
1619)
1620xt "109000,50625,109750,51375"
1621)
1622tg (CPTG
1623uid 211,0
1624ps "CptPortTextPlaceStrategy"
1625stg "RightVerticalLayoutStrategy"
1626f (Text
1627uid 212,0
1628va (VaSet
1629)
1630xt "106300,50500,108000,51500"
1631st "sclk"
1632ju 2
1633blo "108000,51300"
1634)
1635)
1636thePort (LogicalPort
1637m 1
1638decl (Decl
1639n "sclk"
1640t "std_logic"
1641o 34
1642suid 62,0
1643)
1644)
1645)
1646*39 (CptPort
1647uid 213,0
1648ps "OnEdgeStrategy"
1649shape (Diamond
1650uid 214,0
1651ro 90
1652va (VaSet
1653vasetType 1
1654fg "0,65535,0"
1655)
1656xt "109000,51625,109750,52375"
1657)
1658tg (CPTG
1659uid 215,0
1660ps "CptPortTextPlaceStrategy"
1661stg "RightVerticalLayoutStrategy"
1662f (Text
1663uid 216,0
1664va (VaSet
1665)
1666xt "106600,51500,108000,52500"
1667st "sio"
1668ju 2
1669blo "108000,52300"
1670)
1671)
1672thePort (LogicalPort
1673m 2
1674decl (Decl
1675n "sio"
1676t "std_logic"
1677preAdd 0
1678posAdd 0
1679o 41
1680suid 63,0
1681)
1682)
1683)
1684*40 (CptPort
1685uid 217,0
1686ps "OnEdgeStrategy"
1687shape (Triangle
1688uid 218,0
1689ro 90
1690va (VaSet
1691vasetType 1
1692fg "0,65535,0"
1693)
1694xt "109000,39625,109750,40375"
1695)
1696tg (CPTG
1697uid 219,0
1698ps "CptPortTextPlaceStrategy"
1699stg "RightVerticalLayoutStrategy"
1700f (Text
1701uid 220,0
1702va (VaSet
1703)
1704xt "105200,39500,108000,40500"
1705st "dac_cs"
1706ju 2
1707blo "108000,40300"
1708)
1709)
1710thePort (LogicalPort
1711m 1
1712decl (Decl
1713n "dac_cs"
1714t "std_logic"
1715o 26
1716suid 64,0
1717)
1718)
1719)
1720*41 (CptPort
1721uid 221,0
1722ps "OnEdgeStrategy"
1723shape (Triangle
1724uid 222,0
1725ro 90
1726va (VaSet
1727vasetType 1
1728fg "0,65535,0"
1729)
1730xt "109000,41625,109750,42375"
1731)
1732tg (CPTG
1733uid 223,0
1734ps "CptPortTextPlaceStrategy"
1735stg "RightVerticalLayoutStrategy"
1736f (Text
1737uid 224,0
1738va (VaSet
1739)
1740xt "101500,41500,108000,42500"
1741st "sensor_cs : (3:0)"
1742ju 2
1743blo "108000,42300"
1744)
1745)
1746thePort (LogicalPort
1747m 1
1748decl (Decl
1749n "sensor_cs"
1750t "std_logic_vector"
1751b "(3 DOWNTO 0)"
1752o 35
1753suid 65,0
1754)
1755)
1756)
1757*42 (CptPort
1758uid 225,0
1759ps "OnEdgeStrategy"
1760shape (Triangle
1761uid 226,0
1762ro 90
1763va (VaSet
1764vasetType 1
1765fg "0,65535,0"
1766)
1767xt "109000,52625,109750,53375"
1768)
1769tg (CPTG
1770uid 227,0
1771ps "CptPortTextPlaceStrategy"
1772stg "RightVerticalLayoutStrategy"
1773f (Text
1774uid 228,0
1775va (VaSet
1776)
1777xt "106000,52500,108000,53500"
1778st "mosi"
1779ju 2
1780blo "108000,53300"
1781)
1782)
1783thePort (LogicalPort
1784m 1
1785decl (Decl
1786n "mosi"
1787t "std_logic"
1788o 32
1789suid 66,0
1790i "'0'"
1791)
1792)
1793)
1794*43 (CptPort
1795uid 229,0
1796ps "OnEdgeStrategy"
1797shape (Triangle
1798uid 230,0
1799ro 270
1800va (VaSet
1801vasetType 1
1802fg "0,65535,0"
1803)
1804xt "80250,65625,81000,66375"
1805)
1806tg (CPTG
1807uid 231,0
1808ps "CptPortTextPlaceStrategy"
1809stg "VerticalLayoutStrategy"
1810f (Text
1811uid 232,0
1812va (VaSet
1813)
1814xt "82000,65500,85000,66500"
1815st "denable"
1816blo "82000,66300"
1817)
1818)
1819thePort (LogicalPort
1820m 1
1821decl (Decl
1822n "denable"
1823t "std_logic"
1824eolc "-- default domino wave off"
1825posAdd 0
1826o 27
1827suid 67,0
1828i "'0'"
1829)
1830)
1831)
1832*44 (CptPort
1833uid 1395,0
1834ps "OnEdgeStrategy"
1835shape (Triangle
1836uid 1396,0
1837ro 90
1838va (VaSet
1839vasetType 1
1840fg "0,65535,0"
1841)
1842xt "109000,73625,109750,74375"
1843)
1844tg (CPTG
1845uid 1397,0
1846ps "CptPortTextPlaceStrategy"
1847stg "RightVerticalLayoutStrategy"
1848f (Text
1849uid 1398,0
1850va (VaSet
1851)
1852xt "99400,73500,108000,74500"
1853st "alarm_refclk_too_high"
1854ju 2
1855blo "108000,74300"
1856)
1857)
1858thePort (LogicalPort
1859m 1
1860decl (Decl
1861n "alarm_refclk_too_high"
1862t "std_logic"
1863o 22
1864suid 95,0
1865)
1866)
1867)
1868*45 (CptPort
1869uid 1399,0
1870ps "OnEdgeStrategy"
1871shape (Triangle
1872uid 1400,0
1873ro 90
1874va (VaSet
1875vasetType 1
1876fg "0,65535,0"
1877)
1878xt "109000,74625,109750,75375"
1879)
1880tg (CPTG
1881uid 1401,0
1882ps "CptPortTextPlaceStrategy"
1883stg "RightVerticalLayoutStrategy"
1884f (Text
1885uid 1402,0
1886va (VaSet
1887)
1888xt "99800,74500,108000,75500"
1889st "alarm_refclk_too_low"
1890ju 2
1891blo "108000,75300"
1892)
1893)
1894thePort (LogicalPort
1895m 1
1896decl (Decl
1897n "alarm_refclk_too_low"
1898t "std_logic"
1899posAdd 0
1900o 23
1901suid 96,0
1902)
1903)
1904)
1905*46 (CptPort
1906uid 1403,0
1907ps "OnEdgeStrategy"
1908shape (Triangle
1909uid 1404,0
1910ro 90
1911va (VaSet
1912vasetType 1
1913fg "0,65535,0"
1914)
1915xt "109000,79625,109750,80375"
1916)
1917tg (CPTG
1918uid 1405,0
1919ps "CptPortTextPlaceStrategy"
1920stg "RightVerticalLayoutStrategy"
1921f (Text
1922uid 1406,0
1923va (VaSet
1924)
1925xt "105500,79500,108000,80500"
1926st "amber"
1927ju 2
1928blo "108000,80300"
1929)
1930)
1931thePort (LogicalPort
1932m 1
1933decl (Decl
1934n "amber"
1935t "std_logic"
1936o 24
1937suid 87,0
1938)
1939)
1940)
1941*47 (CptPort
1942uid 1407,0
1943ps "OnEdgeStrategy"
1944shape (Triangle
1945uid 1408,0
1946ro 90
1947va (VaSet
1948vasetType 1
1949fg "0,65535,0"
1950)
1951xt "109000,76625,109750,77375"
1952)
1953tg (CPTG
1954uid 1409,0
1955ps "CptPortTextPlaceStrategy"
1956stg "RightVerticalLayoutStrategy"
1957f (Text
1958uid 1410,0
1959va (VaSet
1960)
1961xt "99400,76500,108000,77500"
1962st "counter_result : (11:0)"
1963ju 2
1964blo "108000,77300"
1965)
1966)
1967thePort (LogicalPort
1968m 1
1969decl (Decl
1970n "counter_result"
1971t "std_logic_vector"
1972b "(11 DOWNTO 0)"
1973o 25
1974suid 94,0
1975)
1976)
1977)
1978*48 (CptPort
1979uid 1411,0
1980ps "OnEdgeStrategy"
1981shape (Triangle
1982uid 1412,0
1983ro 90
1984va (VaSet
1985vasetType 1
1986fg "0,65535,0"
1987)
1988xt "80250,74625,81000,75375"
1989)
1990tg (CPTG
1991uid 1413,0
1992ps "CptPortTextPlaceStrategy"
1993stg "VerticalLayoutStrategy"
1994f (Text
1995uid 1414,0
1996va (VaSet
1997)
1998xt "82000,74500,87500,75500"
1999st "D_T_in : (1:0)"
2000blo "82000,75300"
2001)
2002)
2003thePort (LogicalPort
2004decl (Decl
2005n "D_T_in"
2006t "std_logic_vector"
2007b "(1 DOWNTO 0)"
2008o 2
2009suid 91,0
2010)
2011)
2012)
2013*49 (CptPort
2014uid 1415,0
2015ps "OnEdgeStrategy"
2016shape (Triangle
2017uid 1416,0
2018ro 90
2019va (VaSet
2020vasetType 1
2021fg "0,65535,0"
2022)
2023xt "80250,75625,81000,76375"
2024)
2025tg (CPTG
2026uid 1417,0
2027ps "CptPortTextPlaceStrategy"
2028stg "VerticalLayoutStrategy"
2029f (Text
2030uid 1418,0
2031va (VaSet
2032)
2033xt "82000,75500,87100,76500"
2034st "drs_refclk_in"
2035blo "82000,76300"
2036)
2037)
2038thePort (LogicalPort
2039decl (Decl
2040n "drs_refclk_in"
2041t "std_logic"
2042eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
2043o 11
2044suid 92,0
2045)
2046)
2047)
2048*50 (CptPort
2049uid 1419,0
2050ps "OnEdgeStrategy"
2051shape (Triangle
2052uid 1420,0
2053ro 90
2054va (VaSet
2055vasetType 1
2056fg "0,65535,0"
2057)
2058xt "109000,77625,109750,78375"
2059)
2060tg (CPTG
2061uid 1421,0
2062ps "CptPortTextPlaceStrategy"
2063stg "RightVerticalLayoutStrategy"
2064f (Text
2065uid 1422,0
2066va (VaSet
2067)
2068xt "105600,77500,108000,78500"
2069st "green"
2070ju 2
2071blo "108000,78300"
2072)
2073)
2074thePort (LogicalPort
2075m 1
2076decl (Decl
2077n "green"
2078t "std_logic"
2079o 30
2080suid 86,0
2081)
2082)
2083)
2084*51 (CptPort
2085uid 1423,0
2086ps "OnEdgeStrategy"
2087shape (Triangle
2088uid 1424,0
2089ro 90
2090va (VaSet
2091vasetType 1
2092fg "0,65535,0"
2093)
2094xt "80250,76625,81000,77375"
2095)
2096tg (CPTG
2097uid 1425,0
2098ps "CptPortTextPlaceStrategy"
2099stg "VerticalLayoutStrategy"
2100f (Text
2101uid 1426,0
2102va (VaSet
2103)
2104xt "82000,76500,88100,77500"
2105st "plllock_in : (3:0)"
2106blo "82000,77300"
2107)
2108)
2109thePort (LogicalPort
2110decl (Decl
2111n "plllock_in"
2112t "std_logic_vector"
2113b "(3 DOWNTO 0)"
2114eolc "-- high level, if dominowave is running and DRS PLL locked"
2115o 12
2116suid 93,0
2117)
2118)
2119)
2120*52 (CptPort
2121uid 1427,0
2122ps "OnEdgeStrategy"
2123shape (Triangle
2124uid 1428,0
2125ro 90
2126va (VaSet
2127vasetType 1
2128fg "0,65535,0"
2129)
2130xt "109000,78625,109750,79375"
2131)
2132tg (CPTG
2133uid 1429,0
2134ps "CptPortTextPlaceStrategy"
2135stg "RightVerticalLayoutStrategy"
2136f (Text
2137uid 1430,0
2138va (VaSet
2139)
2140xt "106500,78500,108000,79500"
2141st "red"
2142ju 2
2143blo "108000,79300"
2144)
2145)
2146thePort (LogicalPort
2147m 1
2148decl (Decl
2149n "red"
2150t "std_logic"
2151o 33
2152suid 88,0
2153)
2154)
2155)
2156*53 (CptPort
2157uid 1431,0
2158ps "OnEdgeStrategy"
2159shape (Triangle
2160uid 1432,0
2161ro 270
2162va (VaSet
2163vasetType 1
2164fg "0,65535,0"
2165)
2166xt "80250,71625,81000,72375"
2167)
2168tg (CPTG
2169uid 1433,0
2170ps "CptPortTextPlaceStrategy"
2171stg "VerticalLayoutStrategy"
2172f (Text
2173uid 1434,0
2174va (VaSet
2175)
2176xt "82000,71500,85700,72500"
2177st "SRIN_out"
2178blo "82000,72300"
2179)
2180)
2181thePort (LogicalPort
2182m 1
2183decl (Decl
2184n "SRIN_out"
2185t "std_logic"
2186o 20
2187suid 85,0
2188i "'0'"
2189)
2190)
2191)
2192*54 (CptPort
2193uid 1678,0
2194ps "OnEdgeStrategy"
2195shape (Triangle
2196uid 1679,0
2197ro 270
2198va (VaSet
2199vasetType 1
2200fg "0,65535,0"
2201)
2202xt "80250,23625,81000,24375"
2203)
2204tg (CPTG
2205uid 1680,0
2206ps "CptPortTextPlaceStrategy"
2207stg "VerticalLayoutStrategy"
2208f (Text
2209uid 1681,0
2210va (VaSet
2211)
2212xt "82000,23500,86000,24500"
2213st "ADC_CLK"
2214blo "82000,24300"
2215)
2216)
2217thePort (LogicalPort
2218lang 2
2219m 1
2220decl (Decl
2221n "ADC_CLK"
2222t "std_logic"
2223o 15
2224suid 97,0
2225)
2226)
2227)
2228]
2229shape (Rectangle
2230uid 234,0
2231va (VaSet
2232vasetType 1
2233fg "0,65535,0"
2234lineColor "0,32896,0"
2235lineWidth 2
2236)
2237xt "81000,19000,109000,81000"
2238)
2239oxt "15000,-8000,43000,46000"
2240ttg (MlTextGroup
2241uid 235,0
2242ps "CenterOffsetStrategy"
2243stg "VerticalLayoutStrategy"
2244textVec [
2245*55 (Text
2246uid 236,0
2247va (VaSet
2248font "Arial,8,1"
2249)
2250xt "83200,81000,89400,82000"
2251st "FACT_FAD_lib"
2252blo "83200,81800"
2253tm "BdLibraryNameMgr"
2254)
2255*56 (Text
2256uid 237,0
2257va (VaSet
2258font "Arial,8,1"
2259)
2260xt "83200,82000,87400,83000"
2261st "FAD_main"
2262blo "83200,82800"
2263tm "CptNameMgr"
2264)
2265*57 (Text
2266uid 238,0
2267va (VaSet
2268font "Arial,8,1"
2269)
2270xt "83200,83000,90000,84000"
2271st "I_mainTB_FPGA"
2272blo "83200,83800"
2273tm "InstanceNameMgr"
2274)
2275]
2276)
2277ga (GenericAssociation
2278uid 239,0
2279ps "EdgeToEdgeStrategy"
2280matrix (Matrix
2281uid 240,0
2282text (MLText
2283uid 241,0
2284va (VaSet
2285font "Courier New,8,0"
2286)
2287xt "81000,18200,101000,19000"
2288st "RAMADDRWIDTH64b = 15    ( integer )  "
2289)
2290header ""
2291)
2292elements [
2293(GiElement
2294name "RAMADDRWIDTH64b"
2295type "integer"
2296value "15"
2297)
2298]
2299)
2300viewicon (ZoomableIcon
2301uid 242,0
2302sl 0
2303va (VaSet
2304vasetType 1
2305fg "49152,49152,49152"
2306)
2307xt "81250,79250,82750,80750"
2308iconName "BlockDiagram.png"
2309iconMaskName "BlockDiagram.msk"
2310ftype 1
2311)
2312viewiconposition 0
2313portVis (PortSigDisplay
2314)
2315archFileType "UNKNOWN"
2316)
2317*58 (SaComponent
2318uid 274,0
2319optionalChildren [
2320*59 (CptPort
2321uid 266,0
2322ps "OnEdgeStrategy"
2323shape (Triangle
2324uid 267,0
2325ro 90
2326va (VaSet
2327vasetType 1
2328fg "0,65535,0"
2329)
2330xt "58000,20625,58750,21375"
2331)
2332tg (CPTG
2333uid 268,0
2334ps "CptPortTextPlaceStrategy"
2335stg "RightVerticalLayoutStrategy"
2336f (Text
2337uid 269,0
2338va (VaSet
2339)
2340xt "55700,20500,57000,21500"
2341st "clk"
2342ju 2
2343blo "57000,21300"
2344)
2345)
2346thePort (LogicalPort
2347m 1
2348decl (Decl
2349n "clk"
2350t "STD_LOGIC"
2351o 1
2352i "'0'"
2353)
2354)
2355)
2356*60 (CptPort
2357uid 270,0
2358ps "OnEdgeStrategy"
2359shape (Triangle
2360uid 271,0
2361ro 90
2362va (VaSet
2363vasetType 1
2364fg "0,65535,0"
2365)
2366xt "58000,21625,58750,22375"
2367)
2368tg (CPTG
2369uid 272,0
2370ps "CptPortTextPlaceStrategy"
2371stg "RightVerticalLayoutStrategy"
2372f (Text
2373uid 273,0
2374va (VaSet
2375)
2376xt "55700,21500,57000,22500"
2377st "rst"
2378ju 2
2379blo "57000,22300"
2380)
2381)
2382thePort (LogicalPort
2383m 1
2384decl (Decl
2385n "rst"
2386t "STD_LOGIC"
2387o 2
2388i "'0'"
2389)
2390)
2391)
2392]
2393shape (Rectangle
2394uid 275,0
2395va (VaSet
2396vasetType 1
2397fg "0,49152,49152"
2398lineColor "0,0,50000"
2399lineWidth 2
2400)
2401xt "50000,19000,58000,24000"
2402)
2403oxt "0,0,8000,10000"
2404ttg (MlTextGroup
2405uid 276,0
2406ps "CenterOffsetStrategy"
2407stg "VerticalLayoutStrategy"
2408textVec [
2409*61 (Text
2410uid 277,0
2411va (VaSet
2412font "Arial,8,1"
2413)
2414xt "50150,24000,57850,25000"
2415st "FACT_FAD_TB_lib"
2416blo "50150,24800"
2417tm "BdLibraryNameMgr"
2418)
2419*62 (Text
2420uid 278,0
2421va (VaSet
2422font "Arial,8,1"
2423)
2424xt "50150,25000,56850,26000"
2425st "clock_generator"
2426blo "50150,25800"
2427tm "CptNameMgr"
2428)
2429*63 (Text
2430uid 279,0
2431va (VaSet
2432font "Arial,8,1"
2433)
2434xt "50150,26000,56750,27000"
2435st "I_mainTB_clock"
2436blo "50150,26800"
2437tm "InstanceNameMgr"
2438)
2439]
2440)
2441ga (GenericAssociation
2442uid 280,0
2443ps "EdgeToEdgeStrategy"
2444matrix (Matrix
2445uid 281,0
2446text (MLText
2447uid 282,0
2448va (VaSet
2449font "Courier New,8,0"
2450)
2451xt "50000,17400,68500,19000"
2452st "clock_period = 20 ns    ( time ) 
2453reset_time   = 50 ns    ( time )  "
2454)
2455header ""
2456)
2457elements [
2458(GiElement
2459name "clock_period"
2460type "time"
2461value "20 ns"
2462)
2463(GiElement
2464name "reset_time"
2465type "time"
2466value "50 ns"
2467)
2468]
2469)
2470viewicon (ZoomableIcon
2471uid 283,0
2472sl 0
2473va (VaSet
2474vasetType 1
2475fg "49152,49152,49152"
2476)
2477xt "50250,22250,51750,23750"
2478iconName "VhdlFileViewIcon.png"
2479iconMaskName "VhdlFileViewIcon.msk"
2480ftype 10
2481)
2482ordering 1
2483viewiconposition 0
2484portVis (PortSigDisplay
2485)
2486archFileType "UNKNOWN"
2487)
2488*64 (Net
2489uid 284,0
2490decl (Decl
2491n "clk"
2492t "STD_LOGIC"
2493preAdd 0
2494posAdd 0
2495o 1
2496suid 1,0
2497)
2498declText (MLText
2499uid 285,0
2500va (VaSet
2501font "Courier New,8,0"
2502)
2503xt "-90000,41400,-68000,42200"
2504st "SIGNAL clk                   : STD_LOGIC"
2505)
2506)
2507*65 (Net
2508uid 316,0
2509decl (Decl
2510n "wiz_addr"
2511t "std_logic_vector"
2512b "(9 DOWNTO 0)"
2513o 2
2514suid 2,0
2515)
2516declText (MLText
2517uid 317,0
2518va (VaSet
2519font "Courier New,8,0"
2520)
2521xt "-90000,54200,-58500,55000"
2522st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)"
2523)
2524)
2525*66 (Net
2526uid 322,0
2527decl (Decl
2528n "wiz_data"
2529t "std_logic_vector"
2530b "(15 DOWNTO 0)"
2531o 3
2532suid 3,0
2533)
2534declText (MLText
2535uid 323,0
2536va (VaSet
2537font "Courier New,8,0"
2538)
2539xt "-90000,55800,-58000,56600"
2540st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)"
2541)
2542)
2543*67 (Net
2544uid 328,0
2545decl (Decl
2546n "wiz_rd"
2547t "std_logic"
2548o 4
2549suid 4,0
2550i "'1'"
2551)
2552declText (MLText
2553uid 329,0
2554va (VaSet
2555font "Courier New,8,0"
2556)
2557xt "-90000,57400,-55000,58200"
2558st "SIGNAL wiz_rd                : std_logic                    := '1'"
2559)
2560)
2561*68 (Net
2562uid 334,0
2563decl (Decl
2564n "wiz_wr"
2565t "std_logic"
2566o 5
2567suid 5,0
2568i "'1'"
2569)
2570declText (MLText
2571uid 335,0
2572va (VaSet
2573font "Courier New,8,0"
2574)
2575xt "-90000,59000,-55000,59800"
2576st "SIGNAL wiz_wr                : std_logic                    := '1'"
2577)
2578)
2579*69 (SaComponent
2580uid 362,0
2581optionalChildren [
2582*70 (CptPort
2583uid 350,0
2584ps "OnEdgeStrategy"
2585shape (Triangle
2586uid 351,0
2587ro 90
2588va (VaSet
2589vasetType 1
2590fg "0,65535,0"
2591)
2592xt "122250,50625,123000,51375"
2593)
2594tg (CPTG
2595uid 352,0
2596ps "CptPortTextPlaceStrategy"
2597stg "VerticalLayoutStrategy"
2598f (Text
2599uid 353,0
2600va (VaSet
2601)
2602xt "124000,50500,125700,51500"
2603st "sclk"
2604blo "124000,51300"
2605)
2606)
2607thePort (LogicalPort
2608decl (Decl
2609n "sclk"
2610t "std_logic"
2611preAdd 0
2612posAdd 0
2613o 1
2614suid 1,0
2615)
2616)
2617)
2618*71 (CptPort
2619uid 354,0
2620ps "OnEdgeStrategy"
2621shape (Diamond
2622uid 355,0
2623ro 270
2624va (VaSet
2625vasetType 1
2626fg "0,65535,0"
2627)
2628xt "122250,51625,123000,52375"
2629)
2630tg (CPTG
2631uid 356,0
2632ps "CptPortTextPlaceStrategy"
2633stg "VerticalLayoutStrategy"
2634f (Text
2635uid 357,0
2636va (VaSet
2637)
2638xt "124000,51500,125400,52500"
2639st "sio"
2640blo "124000,52300"
2641)
2642)
2643thePort (LogicalPort
2644m 2
2645decl (Decl
2646n "sio"
2647t "std_logic"
2648preAdd 0
2649posAdd 0
2650o 2
2651suid 2,0
2652)
2653)
2654)
2655*72 (CptPort
2656uid 358,0
2657ps "OnEdgeStrategy"
2658shape (Triangle
2659uid 359,0
2660ro 90
2661va (VaSet
2662vasetType 1
2663fg "0,65535,0"
2664)
2665xt "122250,47625,123000,48375"
2666)
2667tg (CPTG
2668uid 360,0
2669ps "CptPortTextPlaceStrategy"
2670stg "VerticalLayoutStrategy"
2671f (Text
2672uid 361,0
2673va (VaSet
2674)
2675xt "124000,47500,130500,48500"
2676st "sensor_cs : (3:0)"
2677blo "124000,48300"
2678)
2679)
2680thePort (LogicalPort
2681decl (Decl
2682n "sensor_cs"
2683t "std_logic_vector"
2684b "(3 downto 0)"
2685preAdd 0
2686posAdd 0
2687o 3
2688suid 3,0
2689)
2690)
2691)
2692]
2693shape (Rectangle
2694uid 363,0
2695va (VaSet
2696vasetType 1
2697fg "0,49152,49152"
2698lineColor "0,0,50000"
2699lineWidth 2
2700)
2701xt "123000,46000,133000,56000"
2702)
2703oxt "30000,3000,40000,13000"
2704ttg (MlTextGroup
2705uid 364,0
2706ps "CenterOffsetStrategy"
2707stg "VerticalLayoutStrategy"
2708textVec [
2709*73 (Text
2710uid 365,0
2711va (VaSet
2712font "Arial,8,1"
2713)
2714xt "123200,56000,130900,57000"
2715st "FACT_FAD_TB_lib"
2716blo "123200,56800"
2717tm "BdLibraryNameMgr"
2718)
2719*74 (Text
2720uid 366,0
2721va (VaSet
2722font "Arial,8,1"
2723)
2724xt "123200,57000,130800,58000"
2725st "max6662_emulator"
2726blo "123200,57800"
2727tm "CptNameMgr"
2728)
2729*75 (Text
2730uid 367,0
2731va (VaSet
2732font "Arial,8,1"
2733)
2734xt "123200,58000,131000,59000"
2735st "I_mainTB_max6662"
2736blo "123200,58800"
2737tm "InstanceNameMgr"
2738)
2739]
2740)
2741ga (GenericAssociation
2742uid 368,0
2743ps "EdgeToEdgeStrategy"
2744matrix (Matrix
2745uid 369,0
2746text (MLText
2747uid 370,0
2748va (VaSet
2749font "Courier New,8,0"
2750)
2751xt "123000,45200,143000,46000"
2752st "DRS_TEMPERATURE = 51    ( integer )  "
2753)
2754header ""
2755)
2756elements [
2757(GiElement
2758name "DRS_TEMPERATURE"
2759type "integer"
2760value "51"
2761)
2762]
2763)
2764viewicon (ZoomableIcon
2765uid 371,0
2766sl 0
2767va (VaSet
2768vasetType 1
2769fg "49152,49152,49152"
2770)
2771xt "123250,54250,124750,55750"
2772iconName "VhdlFileViewIcon.png"
2773iconMaskName "VhdlFileViewIcon.msk"
2774ftype 10
2775)
2776ordering 1
2777viewiconposition 0
2778portVis (PortSigDisplay
2779sIVOD 1
2780)
2781archFileType "UNKNOWN"
2782)
2783*76 (Net
2784uid 372,0
2785decl (Decl
2786n "sensor_cs"
2787t "std_logic_vector"
2788b "(3 DOWNTO 0)"
2789o 6
2790suid 6,0
2791)
2792declText (MLText
2793uid 373,0
2794va (VaSet
2795font "Courier New,8,0"
2796)
2797xt "-90000,51800,-58500,52600"
2798st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
2799)
2800)
2801*77 (Net
2802uid 378,0
2803decl (Decl
2804n "sclk"
2805t "std_logic"
2806o 7
2807suid 7,0
2808)
2809declText (MLText
2810uid 379,0
2811va (VaSet
2812font "Courier New,8,0"
2813)
2814xt "-90000,51000,-68000,51800"
2815st "SIGNAL sclk                  : std_logic"
2816)
2817)
2818*78 (Net
2819uid 384,0
2820decl (Decl
2821n "sio"
2822t "std_logic"
2823preAdd 0
2824posAdd 0
2825o 8
2826suid 8,0
2827)
2828declText (MLText
2829uid 385,0
2830va (VaSet
2831font "Courier New,8,0"
2832)
2833xt "-90000,52600,-68000,53400"
2834st "SIGNAL sio                   : std_logic"
2835)
2836)
2837*79 (SaComponent
2838uid 414,0
2839optionalChildren [
2840*80 (CptPort
2841uid 410,0
2842ps "OnEdgeStrategy"
2843shape (Triangle
2844uid 411,0
2845ro 90
2846va (VaSet
2847vasetType 1
2848fg "0,65535,0"
2849)
2850xt "58000,31625,58750,32375"
2851)
2852tg (CPTG
2853uid 412,0
2854ps "CptPortTextPlaceStrategy"
2855stg "RightVerticalLayoutStrategy"
2856f (Text
2857uid 413,0
2858va (VaSet
2859)
2860xt "54200,31500,57000,32500"
2861st "trigger"
2862ju 2
2863blo "57000,32300"
2864)
2865)
2866thePort (LogicalPort
2867m 1
2868decl (Decl
2869n "trigger"
2870t "std_logic"
2871preAdd 0
2872posAdd 0
2873o 1
2874suid 1,0
2875)
2876)
2877)
2878]
2879shape (Rectangle
2880uid 415,0
2881va (VaSet
2882vasetType 1
2883fg "0,49152,49152"
2884lineColor "0,0,50000"
2885lineWidth 2
2886)
2887xt "50000,30000,58000,36000"
2888)
2889oxt "19000,4000,29000,14000"
2890ttg (MlTextGroup
2891uid 416,0
2892ps "CenterOffsetStrategy"
2893stg "VerticalLayoutStrategy"
2894textVec [
2895*81 (Text
2896uid 417,0
2897va (VaSet
2898font "Arial,8,1"
2899)
2900xt "50200,36000,57900,37000"
2901st "FACT_FAD_TB_lib"
2902blo "50200,36800"
2903tm "BdLibraryNameMgr"
2904)
2905*82 (Text
2906uid 418,0
2907va (VaSet
2908font "Arial,8,1"
2909)
2910xt "50200,37000,57500,38000"
2911st "trigger_generator"
2912blo "50200,37800"
2913tm "CptNameMgr"
2914)
2915*83 (Text
2916uid 419,0
2917va (VaSet
2918font "Arial,8,1"
2919)
2920xt "50200,38000,57400,39000"
2921st "I_mainTB_trigger"
2922blo "50200,38800"
2923tm "InstanceNameMgr"
2924)
2925]
2926)
2927ga (GenericAssociation
2928uid 420,0
2929ps "EdgeToEdgeStrategy"
2930matrix (Matrix
2931uid 421,0
2932text (MLText
2933uid 422,0
2934va (VaSet
2935font "Courier New,8,0"
2936)
2937xt "50000,28400,68500,30000"
2938st "TRIGGER_RATE = 1 ms     ( time ) 
2939PULSE_WIDTH  = 20 ns    ( time )  "
2940)
2941header ""
2942)
2943elements [
2944(GiElement
2945name "TRIGGER_RATE"
2946type "time"
2947value "1 ms"
2948)
2949(GiElement
2950name "PULSE_WIDTH"
2951type "time"
2952value "20 ns"
2953)
2954]
2955)
2956viewicon (ZoomableIcon
2957uid 423,0
2958sl 0
2959va (VaSet
2960vasetType 1
2961fg "49152,49152,49152"
2962)
2963xt "50250,34250,51750,35750"
2964iconName "VhdlFileViewIcon.png"
2965iconMaskName "VhdlFileViewIcon.msk"
2966ftype 10
2967)
2968ordering 1
2969viewiconposition 0
2970portVis (PortSigDisplay
2971sIVOD 1
2972)
2973archFileType "UNKNOWN"
2974)
2975*84 (Net
2976uid 424,0
2977decl (Decl
2978n "trigger"
2979t "std_logic"
2980preAdd 0
2981posAdd 0
2982o 9
2983suid 9,0
2984)
2985declText (MLText
2986uid 425,0
2987va (VaSet
2988font "Courier New,8,0"
2989)
2990xt "-90000,53400,-68000,54200"
2991st "SIGNAL trigger               : std_logic"
2992)
2993)
2994*85 (HdlText
2995uid 430,0
2996optionalChildren [
2997*86 (EmbeddedText
2998uid 436,0
2999commentText (CommentText
3000uid 437,0
3001ps "CenterOffsetStrategy"
3002shape (Rectangle
3003uid 438,0
3004va (VaSet
3005vasetType 1
3006fg "65535,65535,65535"
3007lineColor "0,0,32768"
3008lineWidth 2
3009)
3010xt "50000,45000,60000,49000"
3011)
3012oxt "0,0,18000,5000"
3013text (MLText
3014uid 439,0
3015va (VaSet
3016)
3017xt "50200,45200,58200,49200"
3018st "
3019-- eb_ID 1: hard-wired IDs
3020board_id <= \"0101\";
3021crate_id <= \"01\";
3022
3023"
3024tm "HdlTextMgr"
3025wrapOption 3
3026visibleHeight 4000
3027visibleWidth 10000
3028)
3029)
3030)
3031]
3032shape (Rectangle
3033uid 431,0
3034va (VaSet
3035vasetType 1
3036fg "65535,65535,37120"
3037lineColor "0,0,32768"
3038lineWidth 2
3039)
3040xt "50000,40000,58000,45000"
3041)
3042oxt "0,0,8000,10000"
3043ttg (MlTextGroup
3044uid 432,0
3045ps "CenterOffsetStrategy"
3046stg "VerticalLayoutStrategy"
3047textVec [
3048*87 (Text
3049uid 433,0
3050va (VaSet
3051font "Arial,8,1"
3052)
3053xt "51150,41000,57350,42000"
3054st "eb_mainTB_ID"
3055blo "51150,41800"
3056tm "HdlTextNameMgr"
3057)
3058*88 (Text
3059uid 434,0
3060va (VaSet
3061font "Arial,8,1"
3062)
3063xt "51150,42000,51950,43000"
3064st "1"
3065blo "51150,42800"
3066tm "HdlTextNumberMgr"
3067)
3068]
3069)
3070viewicon (ZoomableIcon
3071uid 435,0
3072sl 0
3073va (VaSet
3074vasetType 1
3075fg "49152,49152,49152"
3076)
3077xt "50250,43250,51750,44750"
3078iconName "TextFile.png"
3079iconMaskName "TextFile.msk"
3080ftype 21
3081)
3082viewiconposition 0
3083)
3084*89 (Net
3085uid 440,0
3086decl (Decl
3087n "board_id"
3088t "std_logic_vector"
3089b "(3 downto 0)"
3090preAdd 0
3091posAdd 0
3092o 10
3093suid 10,0
3094)
3095declText (MLText
3096uid 441,0
3097va (VaSet
3098font "Courier New,8,0"
3099)
3100xt "-90000,40600,-58500,41400"
3101st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
3102)
3103)
3104*90 (Net
3105uid 448,0
3106decl (Decl
3107n "crate_id"
3108t "std_logic_vector"
3109b "(1 downto 0)"
3110o 11
3111suid 11,0
3112)
3113declText (MLText
3114uid 449,0
3115va (VaSet
3116font "Courier New,8,0"
3117)
3118xt "-90000,43000,-58500,43800"
3119st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
3120)
3121)
3122*91 (SaComponent
3123uid 508,0
3124optionalChildren [
3125*92 (CptPort
3126uid 489,0
3127ps "OnEdgeStrategy"
3128shape (Triangle
3129uid 490,0
3130ro 90
3131va (VaSet
3132vasetType 1
3133fg "0,65535,0"
3134)
3135xt "29250,52625,30000,53375"
3136)
3137tg (CPTG
3138uid 491,0
3139ps "CptPortTextPlaceStrategy"
3140stg "VerticalLayoutStrategy"
3141f (Text
3142uid 492,0
3143va (VaSet
3144)
3145xt "31000,52500,32300,53500"
3146st "clk"
3147blo "31000,53300"
3148)
3149)
3150thePort (LogicalPort
3151decl (Decl
3152n "clk"
3153t "STD_LOGIC"
3154preAdd 0
3155posAdd 0
3156o 1
3157suid 1,0
3158)
3159)
3160)
3161*93 (CptPort
3162uid 493,0
3163ps "OnEdgeStrategy"
3164shape (Triangle
3165uid 494,0
3166ro 90
3167va (VaSet
3168vasetType 1
3169fg "0,65535,0"
3170)
3171xt "40000,54625,40750,55375"
3172)
3173tg (CPTG
3174uid 495,0
3175ps "CptPortTextPlaceStrategy"
3176stg "RightVerticalLayoutStrategy"
3177f (Text
3178uid 496,0
3179va (VaSet
3180)
3181xt "34200,54500,39000,55500"
3182st "data : (11:0)"
3183ju 2
3184blo "39000,55300"
3185)
3186)
3187thePort (LogicalPort
3188m 1
3189decl (Decl
3190n "data"
3191t "STD_LOGIC_VECTOR"
3192b "(11 DOWNTO 0)"
3193preAdd 0
3194posAdd 0
3195o 2
3196suid 2,0
3197)
3198)
3199)
3200*94 (CptPort
3201uid 497,0
3202ps "OnEdgeStrategy"
3203shape (Triangle
3204uid 498,0
3205ro 90
3206va (VaSet
3207vasetType 1
3208fg "0,65535,0"
3209)
3210xt "40000,52625,40750,53375"
3211)
3212tg (CPTG
3213uid 499,0
3214ps "CptPortTextPlaceStrategy"
3215stg "RightVerticalLayoutStrategy"
3216f (Text
3217uid 500,0
3218va (VaSet
3219)
3220xt "37700,52500,39000,53500"
3221st "otr"
3222ju 2
3223blo "39000,53300"
3224)
3225)
3226thePort (LogicalPort
3227m 1
3228decl (Decl
3229n "otr"
3230t "STD_LOGIC"
3231preAdd 0
3232posAdd 0
3233o 3
3234suid 3,0
3235)
3236)
3237)
3238*95 (CptPort
3239uid 501,0
3240ps "OnEdgeStrategy"
3241shape (Triangle
3242uid 502,0
3243ro 270
3244va (VaSet
3245vasetType 1
3246fg "0,65535,0"
3247)
3248xt "40000,53625,40750,54375"
3249)
3250tg (CPTG
3251uid 503,0
3252ps "CptPortTextPlaceStrategy"
3253stg "RightVerticalLayoutStrategy"
3254f (Text
3255uid 504,0
3256va (VaSet
3257)
3258xt "37400,53500,39000,54500"
3259st "oeb"
3260ju 2
3261blo "39000,54300"
3262)
3263)
3264thePort (LogicalPort
3265decl (Decl
3266n "oeb"
3267t "STD_LOGIC"
3268preAdd 0
3269posAdd 0
3270o 4
3271suid 4,0
3272)
3273)
3274)
3275]
3276shape (Rectangle
3277uid 509,0
3278va (VaSet
3279vasetType 1
3280fg "0,49152,49152"
3281lineColor "0,0,50000"
3282lineWidth 2
3283)
3284xt "30000,51000,40000,58000"
3285)
3286oxt "29000,7000,39000,17000"
3287ttg (MlTextGroup
3288uid 510,0
3289ps "CenterOffsetStrategy"
3290stg "VerticalLayoutStrategy"
3291textVec [
3292*96 (Text
3293uid 511,0
3294va (VaSet
3295font "Arial,8,1"
3296)
3297xt "30200,58000,37900,59000"
3298st "FACT_FAD_TB_lib"
3299blo "30200,58800"
3300tm "BdLibraryNameMgr"
3301)
3302*97 (Text
3303uid 512,0
3304va (VaSet
3305font "Arial,8,1"
3306)
3307xt "30200,59000,36000,60000"
3308st "adc_emulator"
3309blo "30200,59800"
3310tm "CptNameMgr"
3311)
3312*98 (Text
3313uid 513,0
3314va (VaSet
3315font "Arial,8,1"
3316)
3317xt "30200,60000,36200,61000"
3318st "I_mainTB_adc"
3319blo "30200,60800"
3320tm "InstanceNameMgr"
3321)
3322]
3323)
3324ga (GenericAssociation
3325uid 514,0
3326ps "EdgeToEdgeStrategy"
3327matrix (Matrix
3328uid 515,0
3329text (MLText
3330uid 516,0
3331va (VaSet
3332font "Courier New,8,0"
3333)
3334xt "30000,50200,65500,51000"
3335st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\"    ( string )  "
3336)
3337header ""
3338)
3339elements [
3340(GiElement
3341name "INPUT_FILE"
3342type "string"
3343value "\"../memory_files/analog_input_ch0.txt\""
3344)
3345]
3346)
3347viewicon (ZoomableIcon
3348uid 517,0
3349sl 0
3350va (VaSet
3351vasetType 1
3352fg "49152,49152,49152"
3353)
3354xt "30250,56250,31750,57750"
3355iconName "VhdlFileViewIcon.png"
3356iconMaskName "VhdlFileViewIcon.msk"
3357ftype 10
3358)
3359ordering 1
3360viewiconposition 0
3361portVis (PortSigDisplay
3362sIVOD 1
3363)
3364archFileType "UNKNOWN"
3365)
3366*99 (HdlText
3367uid 518,0
3368optionalChildren [
3369*100 (EmbeddedText
3370uid 524,0
3371commentText (CommentText
3372uid 525,0
3373ps "CenterOffsetStrategy"
3374shape (Rectangle
3375uid 526,0
3376va (VaSet
3377vasetType 1
3378fg "65535,65535,65535"
3379lineColor "0,0,32768"
3380lineWidth 2
3381)
3382xt "50000,57000,62000,67000"
3383)
3384oxt "0,0,18000,5000"
3385text (MLText
3386uid 527,0
3387va (VaSet
3388)
3389xt "50200,57200,60900,67200"
3390st "
3391-- eb_adc 2: ADC routing
3392adc_data_array(0) <= adc_data;
3393adc_data_array(1) <= adc_data;
3394adc_data_array(2) <= adc_data;
3395adc_data_array(3) <= adc_data;
3396adc_otr_array(0) <= adc_otr;
3397adc_otr_array(1) <= adc_otr;
3398adc_otr_array(2) <= adc_otr;
3399adc_otr_array(3) <= adc_otr;
3400
3401"
3402tm "HdlTextMgr"
3403wrapOption 3
3404visibleHeight 10000
3405visibleWidth 12000
3406)
3407)
3408)
3409]
3410shape (Rectangle
3411uid 519,0
3412va (VaSet
3413vasetType 1
3414fg "65535,65535,37120"
3415lineColor "0,0,32768"
3416lineWidth 2
3417)
3418xt "50000,51000,58000,57000"
3419)
3420oxt "0,0,8000,10000"
3421ttg (MlTextGroup
3422uid 520,0
3423ps "CenterOffsetStrategy"
3424stg "VerticalLayoutStrategy"
3425textVec [
3426*101 (Text
3427uid 521,0
3428va (VaSet
3429font "Arial,8,1"
3430)
3431xt "51150,52000,57850,53000"
3432st "eb_mainTB_adc"
3433blo "51150,52800"
3434tm "HdlTextNameMgr"
3435)
3436*102 (Text
3437uid 522,0
3438va (VaSet
3439font "Arial,8,1"
3440)
3441xt "51150,53000,51950,54000"
3442st "2"
3443blo "51150,53800"
3444tm "HdlTextNumberMgr"
3445)
3446]
3447)
3448viewicon (ZoomableIcon
3449uid 523,0
3450sl 0
3451va (VaSet
3452vasetType 1
3453fg "49152,49152,49152"
3454)
3455xt "50250,55250,51750,56750"
3456iconName "TextFile.png"
3457iconMaskName "TextFile.msk"
3458ftype 21
3459)
3460viewiconposition 0
3461)
3462*103 (Net
3463uid 528,0
3464decl (Decl
3465n "adc_otr_array"
3466t "std_logic_vector"
3467b "(3 DOWNTO 0)"
3468o 12
3469suid 12,0
3470)
3471declText (MLText
3472uid 529,0
3473va (VaSet
3474font "Courier New,8,0"
3475)
3476xt "-90000,37400,-58500,38200"
3477st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)"
3478)
3479)
3480*104 (Net
3481uid 536,0
3482decl (Decl
3483n "adc_data_array"
3484t "adc_data_array_type"
3485o 13
3486suid 13,0
3487)
3488declText (MLText
3489uid 537,0
3490va (VaSet
3491font "Courier New,8,0"
3492)
3493xt "-90000,35000,-63000,35800"
3494st "SIGNAL adc_data_array        : adc_data_array_type"
3495)
3496)
3497*105 (Net
3498uid 544,0
3499decl (Decl
3500n "adc_oeb"
3501t "std_logic"
3502preAdd 0
3503posAdd 0
3504o 14
3505suid 14,0
3506)
3507declText (MLText
3508uid 545,0
3509va (VaSet
3510font "Courier New,8,0"
3511)
3512xt "-90000,35800,-68000,36600"
3513st "SIGNAL adc_oeb               : std_logic"
3514)
3515)
3516*106 (Net
3517uid 560,0
3518decl (Decl
3519n "adc_otr"
3520t "STD_LOGIC"
3521preAdd 0
3522posAdd 0
3523o 16
3524suid 16,0
3525)
3526declText (MLText
3527uid 561,0
3528va (VaSet
3529font "Courier New,8,0"
3530)
3531xt "-90000,36600,-68000,37400"
3532st "SIGNAL adc_otr               : STD_LOGIC"
3533)
3534)
3535*107 (Net
3536uid 568,0
3537decl (Decl
3538n "adc_data"
3539t "std_logic_vector"
3540b "(11 DOWNTO 0)"
3541preAdd 0
3542posAdd 0
3543o 17
3544suid 17,0
3545)
3546declText (MLText
3547uid 569,0
3548va (VaSet
3549font "Courier New,8,0"
3550)
3551xt "-90000,34200,-58000,35000"
3552st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)"
3553)
3554)
3555*108 (Net
3556uid 767,0
3557decl (Decl
3558n "wiz_reset"
3559t "std_logic"
3560o 21
3561suid 23,0
3562i "'1'"
3563)
3564declText (MLText
3565uid 768,0
3566va (VaSet
3567font "Courier New,8,0"
3568)
3569xt "-90000,58200,-55000,59000"
3570st "SIGNAL wiz_reset             : std_logic                    := '1'"
3571)
3572)
3573*109 (Net
3574uid 775,0
3575decl (Decl
3576n "led"
3577t "std_logic_vector"
3578b "(7 DOWNTO 0)"
3579posAdd 0
3580o 22
3581suid 24,0
3582i "(OTHERS => '0')"
3583)
3584declText (MLText
3585uid 776,0
3586va (VaSet
3587font "Courier New,8,0"
3588)
3589xt "-90000,47800,-49000,48600"
3590st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
3591)
3592)
3593*110 (Net
3594uid 783,0
3595decl (Decl
3596n "wiz_cs"
3597t "std_logic"
3598o 23
3599suid 25,0
3600i "'1'"
3601)
3602declText (MLText
3603uid 784,0
3604va (VaSet
3605font "Courier New,8,0"
3606)
3607xt "-90000,55000,-55000,55800"
3608st "SIGNAL wiz_cs                : std_logic                    := '1'"
3609)
3610)
3611*111 (Net
3612uid 791,0
3613decl (Decl
3614n "wiz_int"
3615t "std_logic"
3616o 24
3617suid 26,0
3618)
3619declText (MLText
3620uid 792,0
3621va (VaSet
3622font "Courier New,8,0"
3623)
3624xt "-90000,56600,-68000,57400"
3625st "SIGNAL wiz_int               : std_logic"
3626)
3627)
3628*112 (Net
3629uid 799,0
3630decl (Decl
3631n "dac_cs"
3632t "std_logic"
3633o 25
3634suid 27,0
3635)
3636declText (MLText
3637uid 800,0
3638va (VaSet
3639font "Courier New,8,0"
3640)
3641xt "-90000,43800,-68000,44600"
3642st "SIGNAL dac_cs                : std_logic"
3643)
3644)
3645*113 (Net
3646uid 807,0
3647decl (Decl
3648n "mosi"
3649t "std_logic"
3650o 26
3651suid 28,0
3652i "'0'"
3653)
3654declText (MLText
3655uid 808,0
3656va (VaSet
3657font "Courier New,8,0"
3658)
3659xt "-90000,48600,-55000,49400"
3660st "SIGNAL mosi                  : std_logic                    := '0'"
3661)
3662)
3663*114 (Net
3664uid 815,0
3665decl (Decl
3666n "denable"
3667t "std_logic"
3668eolc "-- default domino wave off"
3669posAdd 0
3670o 27
3671suid 29,0
3672i "'0'"
3673)
3674declText (MLText
3675uid 816,0
3676va (VaSet
3677font "Courier New,8,0"
3678)
3679xt "-90000,44600,-41500,45400"
3680st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off"
3681)
3682)
3683*115 (Net
3684uid 823,0
3685decl (Decl
3686n "CLK_25_PS"
3687t "std_logic"
3688o 28
3689suid 30,0
3690)
3691declText (MLText
3692uid 824,0
3693va (VaSet
3694font "Courier New,8,0"
3695)
3696xt "-90000,25400,-68000,26200"
3697st "SIGNAL CLK_25_PS             : std_logic"
3698)
3699)
3700*116 (Net
3701uid 831,0
3702decl (Decl
3703n "CLK_50"
3704t "std_logic"
3705o 29
3706suid 31,0
3707)
3708declText (MLText
3709uid 832,0
3710va (VaSet
3711font "Courier New,8,0"
3712)
3713xt "-90000,26200,-68000,27000"
3714st "SIGNAL CLK_50                : std_logic"
3715)
3716)
3717*117 (Net
3718uid 839,0
3719decl (Decl
3720n "drs_channel_id"
3721t "std_logic_vector"
3722b "(3 downto 0)"
3723o 30
3724suid 32,0
3725i "(others => '0')"
3726)
3727declText (MLText
3728uid 840,0
3729va (VaSet
3730font "Courier New,8,0"
3731)
3732xt "-90000,45400,-49000,46200"
3733st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')"
3734)
3735)
3736*118 (Net
3737uid 847,0
3738decl (Decl
3739n "drs_dwrite"
3740t "std_logic"
3741o 31
3742suid 33,0
3743i "'1'"
3744)
3745declText (MLText
3746uid 848,0
3747va (VaSet
3748font "Courier New,8,0"
3749)
3750xt "-90000,46200,-55000,47000"
3751st "SIGNAL drs_dwrite            : std_logic                    := '1'"
3752)
3753)
3754*119 (Net
3755uid 855,0
3756decl (Decl
3757n "RSRLOAD"
3758t "std_logic"
3759o 32
3760suid 34,0
3761i "'0'"
3762)
3763declText (MLText
3764uid 856,0
3765va (VaSet
3766font "Courier New,8,0"
3767)
3768xt "-90000,28600,-55000,29400"
3769st "SIGNAL RSRLOAD               : std_logic                    := '0'"
3770)
3771)
3772*120 (Net
3773uid 863,0
3774decl (Decl
3775n "SRCLK"
3776t "std_logic"
3777o 33
3778suid 35,0
3779i "'0'"
3780)
3781declText (MLText
3782uid 864,0
3783va (VaSet
3784font "Courier New,8,0"
3785)
3786xt "-90000,29400,-55000,30200"
3787st "SIGNAL SRCLK                 : std_logic                    := '0'"
3788)
3789)
3790*121 (Net
3791uid 871,0
3792decl (Decl
3793n "SROUT_in_0"
3794t "std_logic"
3795o 30
3796suid 36,0
3797)
3798declText (MLText
3799uid 872,0
3800va (VaSet
3801font "Courier New,8,0"
3802)
3803xt "-90000,31000,-68000,31800"
3804st "SIGNAL SROUT_in_0            : std_logic"
3805)
3806)
3807*122 (Net
3808uid 879,0
3809decl (Decl
3810n "SROUT_in_1"
3811t "std_logic"
3812o 31
3813suid 37,0
3814)
3815declText (MLText
3816uid 880,0
3817va (VaSet
3818font "Courier New,8,0"
3819)
3820xt "-90000,31800,-68000,32600"
3821st "SIGNAL SROUT_in_1            : std_logic"
3822)
3823)
3824*123 (Net
3825uid 887,0
3826decl (Decl
3827n "SROUT_in_2"
3828t "std_logic"
3829o 32
3830suid 38,0
3831)
3832declText (MLText
3833uid 888,0
3834va (VaSet
3835font "Courier New,8,0"
3836)
3837xt "-90000,32600,-68000,33400"
3838st "SIGNAL SROUT_in_2            : std_logic"
3839)
3840)
3841*124 (Net
3842uid 895,0
3843decl (Decl
3844n "SROUT_in_3"
3845t "std_logic"
3846o 33
3847suid 39,0
3848)
3849declText (MLText
3850uid 896,0
3851va (VaSet
3852font "Courier New,8,0"
3853)
3854xt "-90000,33400,-68000,34200"
3855st "SIGNAL SROUT_in_3            : std_logic"
3856)
3857)
3858*125 (Net
3859uid 1435,0
3860decl (Decl
3861n "SRIN_out"
3862t "std_logic"
3863o 34
3864suid 40,0
3865i "'0'"
3866)
3867declText (MLText
3868uid 1436,0
3869va (VaSet
3870font "Courier New,8,0"
3871)
3872xt "-90000,30200,-55000,31000"
3873st "SIGNAL SRIN_out              : std_logic                    := '0'"
3874)
3875)
3876*126 (Net
3877uid 1443,0
3878decl (Decl
3879n "amber"
3880t "std_logic"
3881o 35
3882suid 41,0
3883)
3884declText (MLText
3885uid 1444,0
3886va (VaSet
3887font "Courier New,8,0"
3888)
3889xt "-90000,39800,-68000,40600"
3890st "SIGNAL amber                 : std_logic"
3891)
3892)
3893*127 (Net
3894uid 1451,0
3895decl (Decl
3896n "red"
3897t "std_logic"
3898o 36
3899suid 42,0
3900)
3901declText (MLText
3902uid 1452,0
3903va (VaSet
3904font "Courier New,8,0"
3905)
3906xt "-90000,50200,-68000,51000"
3907st "SIGNAL red                   : std_logic"
3908)
3909)
3910*128 (Net
3911uid 1459,0
3912decl (Decl
3913n "green"
3914t "std_logic"
3915o 37
3916suid 43,0
3917)
3918declText (MLText
3919uid 1460,0
3920va (VaSet
3921font "Courier New,8,0"
3922)
3923xt "-90000,47000,-68000,47800"
3924st "SIGNAL green                 : std_logic"
3925)
3926)
3927*129 (Net
3928uid 1467,0
3929decl (Decl
3930n "counter_result"
3931t "std_logic_vector"
3932b "(11 DOWNTO 0)"
3933o 38
3934suid 44,0
3935)
3936declText (MLText
3937uid 1468,0
3938va (VaSet
3939font "Courier New,8,0"
3940)
3941xt "-90000,42200,-58000,43000"
3942st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
3943)
3944)
3945*130 (Net
3946uid 1475,0
3947decl (Decl
3948n "alarm_refclk_too_low"
3949t "std_logic"
3950posAdd 0
3951o 39
3952suid 45,0
3953)
3954declText (MLText
3955uid 1476,0
3956va (VaSet
3957font "Courier New,8,0"
3958)
3959xt "-90000,39000,-68000,39800"
3960st "SIGNAL alarm_refclk_too_low  : std_logic"
3961)
3962)
3963*131 (Net
3964uid 1483,0
3965decl (Decl
3966n "alarm_refclk_too_high"
3967t "std_logic"
3968o 40
3969suid 46,0
3970)
3971declText (MLText
3972uid 1484,0
3973va (VaSet
3974font "Courier New,8,0"
3975)
3976xt "-90000,38200,-68000,39000"
3977st "SIGNAL alarm_refclk_too_high : std_logic"
3978)
3979)
3980*132 (HdlText
3981uid 1491,0
3982optionalChildren [
3983*133 (EmbeddedText
3984uid 1497,0
3985commentText (CommentText
3986uid 1498,0
3987ps "CenterOffsetStrategy"
3988shape (Rectangle
3989uid 1499,0
3990va (VaSet
3991vasetType 1
3992fg "65535,65535,65535"
3993lineColor "0,0,32768"
3994lineWidth 2
3995)
3996xt "27000,72000,41000,77000"
3997)
3998oxt "0,0,18000,5000"
3999text (MLText
4000uid 1500,0
4001va (VaSet
4002)
4003xt "27200,72200,40200,77200"
4004st "
4005
4006D_T_in(1 downto 0) <= \"00\";
4007plllock_in(3 downto 0) <= \"1111\";
4008SROUT_in_0 <= '1';
4009SROUT_in_1 <= '0';
4010SROUT_in_2 <= '1';
4011SROUT_in_3 <= '0';
4012
4013"
4014tm "HdlTextMgr"
4015wrapOption 3
4016visibleHeight 5000
4017visibleWidth 14000
4018)
4019)
4020)
4021]
4022shape (Rectangle
4023uid 1492,0
4024va (VaSet
4025vasetType 1
4026fg "65535,65535,37120"
4027lineColor "0,0,32768"
4028lineWidth 2
4029)
4030xt "27000,69000,35000,72000"
4031)
4032oxt "0,0,8000,10000"
4033ttg (MlTextGroup
4034uid 1493,0
4035ps "CenterOffsetStrategy"
4036stg "VerticalLayoutStrategy"
4037textVec [
4038*134 (Text
4039uid 1494,0
4040va (VaSet
4041font "Arial,8,1"
4042)
4043xt "28150,69000,35250,70000"
4044st "eb_mainTB_adc1"
4045blo "28150,69800"
4046tm "HdlTextNameMgr"
4047)
4048*135 (Text
4049uid 1495,0
4050va (VaSet
4051font "Arial,8,1"
4052)
4053xt "28150,70000,28950,71000"
4054st "3"
4055blo "28150,70800"
4056tm "HdlTextNumberMgr"
4057)
4058]
4059)
4060viewicon (ZoomableIcon
4061uid 1496,0
4062sl 0
4063va (VaSet
4064vasetType 1
4065fg "49152,49152,49152"
4066)
4067xt "27250,70250,28750,71750"
4068iconName "TextFile.png"
4069iconMaskName "TextFile.msk"
4070ftype 21
4071)
4072viewiconposition 0
4073)
4074*136 (Net
4075uid 1501,0
4076decl (Decl
4077n "D_T_in"
4078t "std_logic_vector"
4079b "(1 DOWNTO 0)"
4080o 41
4081suid 47,0
4082)
4083declText (MLText
4084uid 1502,0
4085va (VaSet
4086font "Courier New,8,0"
4087)
4088xt "-90000,27000,-58500,27800"
4089st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
4090)
4091)
4092*137 (SaComponent
4093uid 1509,0
4094optionalChildren [
4095*138 (CptPort
4096uid 1519,0
4097ps "OnEdgeStrategy"
4098shape (Triangle
4099uid 1520,0
4100ro 90
4101va (VaSet
4102vasetType 1
4103fg "0,65535,0"
4104)
4105xt "66000,78625,66750,79375"
4106)
4107tg (CPTG
4108uid 1521,0
4109ps "CptPortTextPlaceStrategy"
4110stg "RightVerticalLayoutStrategy"
4111f (Text
4112uid 1522,0
4113va (VaSet
4114)
4115xt "63700,78500,65000,79500"
4116st "clk"
4117ju 2
4118blo "65000,79300"
4119)
4120)
4121thePort (LogicalPort
4122m 1
4123decl (Decl
4124n "clk"
4125t "STD_LOGIC"
4126o 1
4127i "'0'"
4128)
4129)
4130)
4131*139 (CptPort
4132uid 1523,0
4133ps "OnEdgeStrategy"
4134shape (Triangle
4135uid 1524,0
4136ro 90
4137va (VaSet
4138vasetType 1
4139fg "0,65535,0"
4140)
4141xt "66000,79625,66750,80375"
4142)
4143tg (CPTG
4144uid 1525,0
4145ps "CptPortTextPlaceStrategy"
4146stg "RightVerticalLayoutStrategy"
4147f (Text
4148uid 1526,0
4149va (VaSet
4150)
4151xt "63700,79500,65000,80500"
4152st "rst"
4153ju 2
4154blo "65000,80300"
4155)
4156)
4157thePort (LogicalPort
4158m 1
4159decl (Decl
4160n "rst"
4161t "STD_LOGIC"
4162o 2
4163i "'0'"
4164)
4165)
4166)
4167]
4168shape (Rectangle
4169uid 1510,0
4170va (VaSet
4171vasetType 1
4172fg "0,49152,49152"
4173lineColor "0,0,50000"
4174lineWidth 2
4175)
4176xt "55000,77000,66000,82000"
4177)
4178oxt "0,0,8000,10000"
4179ttg (MlTextGroup
4180uid 1511,0
4181ps "CenterOffsetStrategy"
4182stg "VerticalLayoutStrategy"
4183textVec [
4184*140 (Text
4185uid 1512,0
4186va (VaSet
4187font "Arial,8,1"
4188)
4189xt "56150,78000,63850,79000"
4190st "FACT_FAD_TB_lib"
4191blo "56150,78800"
4192tm "BdLibraryNameMgr"
4193)
4194*141 (Text
4195uid 1513,0
4196va (VaSet
4197font "Arial,8,1"
4198)
4199xt "56150,79000,62850,80000"
4200st "clock_generator"
4201blo "56150,79800"
4202tm "CptNameMgr"
4203)
4204*142 (Text
4205uid 1514,0
4206va (VaSet
4207font "Arial,8,1"
4208)
4209xt "56150,80000,63150,81000"
4210st "I_mainTB_clock1"
4211blo "56150,80800"
4212tm "InstanceNameMgr"
4213)
4214]
4215)
4216ga (GenericAssociation
4217uid 1515,0
4218ps "EdgeToEdgeStrategy"
4219matrix (Matrix
4220uid 1516,0
4221text (MLText
4222uid 1517,0
4223va (VaSet
4224font "Courier New,8,0"
4225)
4226xt "55000,82400,73000,84000"
4227st "clock_period = 1 us    ( time ) 
4228reset_time   = 1 us    ( time )  "
4229)
4230header ""
4231)
4232elements [
4233(GiElement
4234name "clock_period"
4235type "time"
4236value "1 us"
4237)
4238(GiElement
4239name "reset_time"
4240type "time"
4241value "1 us"
4242)
4243]
4244)
4245viewicon (ZoomableIcon
4246uid 1518,0
4247sl 0
4248va (VaSet
4249vasetType 1
4250fg "49152,49152,49152"
4251)
4252xt "55250,80250,56750,81750"
4253iconName "VhdlFileViewIcon.png"
4254iconMaskName "VhdlFileViewIcon.msk"
4255ftype 10
4256)
4257ordering 1
4258viewiconposition 0
4259portVis (PortSigDisplay
4260)
4261archFileType "UNKNOWN"
4262)
4263*143 (Net
4264uid 1559,0
4265decl (Decl
4266n "plllock_in"
4267t "std_logic_vector"
4268b "(3 DOWNTO 0)"
4269eolc "-- high level, if dominowave is running and DRS PLL locked"
4270o 43
4271suid 49,0
4272)
4273declText (MLText
4274uid 1560,0
4275va (VaSet
4276font "Courier New,8,0"
4277)
4278xt "-90000,49400,-29000,50200"
4279st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
4280)
4281)
4282*144 (Net
4283uid 1682,0
4284lang 2
4285decl (Decl
4286n "ADC_CLK"
4287t "std_logic"
4288o 44
4289suid 50,0
4290)
4291declText (MLText
4292uid 1683,0
4293va (VaSet
4294font "Courier New,8,0"
4295)
4296xt "-90000,24600,-68000,25400"
4297st "SIGNAL ADC_CLK               : std_logic"
4298)
4299)
4300*145 (Net
4301uid 2001,0
4302decl (Decl
4303n "REF_CLK"
4304t "STD_LOGIC"
4305o 42
4306suid 51,0
4307i "'0'"
4308)
4309declText (MLText
4310uid 2002,0
4311va (VaSet
4312font "Courier New,8,0"
4313)
4314xt "-90000,27800,-55000,28600"
4315st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'"
4316)
4317)
4318*146 (SaComponent
4319uid 2336,0
4320optionalChildren [
4321*147 (CptPort
4322uid 2315,0
4323ps "OnEdgeStrategy"
4324shape (Triangle
4325uid 2316,0
4326ro 90
4327va (VaSet
4328vasetType 1
4329fg "0,65535,0"
4330)
4331xt "122250,20625,123000,21375"
4332)
4333tg (CPTG
4334uid 2317,0
4335ps "CptPortTextPlaceStrategy"
4336stg "VerticalLayoutStrategy"
4337f (Text
4338uid 2318,0
4339va (VaSet
4340)
4341xt "124000,20500,129100,21500"
4342st "addr : (9:0)"
4343blo "124000,21300"
4344)
4345)
4346thePort (LogicalPort
4347decl (Decl
4348n "addr"
4349t "std_logic_vector"
4350b "(9 DOWNTO 0)"
4351preAdd 0
4352posAdd 0
4353o 2
4354suid 1,0
4355)
4356)
4357)
4358*148 (CptPort
4359uid 2319,0
4360ps "OnEdgeStrategy"
4361shape (Diamond
4362uid 2320,0
4363ro 270
4364va (VaSet
4365vasetType 1
4366fg "0,65535,0"
4367)
4368xt "122250,21625,123000,22375"
4369)
4370tg (CPTG
4371uid 2321,0
4372ps "CptPortTextPlaceStrategy"
4373stg "VerticalLayoutStrategy"
4374f (Text
4375uid 2322,0
4376va (VaSet
4377)
4378xt "124000,21500,129400,22500"
4379st "data : (15:0)"
4380blo "124000,22300"
4381)
4382)
4383thePort (LogicalPort
4384m 2
4385decl (Decl
4386n "data"
4387t "std_logic_vector"
4388b "(15 DOWNTO 0)"
4389preAdd 0
4390posAdd 0
4391o 3
4392suid 2,0
4393)
4394)
4395)
4396*149 (CptPort
4397uid 2323,0
4398ps "OnEdgeStrategy"
4399shape (Triangle
4400uid 2324,0
4401ro 90
4402va (VaSet
4403vasetType 1
4404fg "0,65535,0"
4405)
4406xt "122250,24625,123000,25375"
4407)
4408tg (CPTG
4409uid 2325,0
4410ps "CptPortTextPlaceStrategy"
4411stg "VerticalLayoutStrategy"
4412f (Text
4413uid 2326,0
4414va (VaSet
4415)
4416xt "124000,24500,125300,25500"
4417st "rd"
4418blo "124000,25300"
4419)
4420)
4421thePort (LogicalPort
4422decl (Decl
4423n "rd"
4424t "std_logic"
4425preAdd 0
4426posAdd 0
4427o 4
4428suid 3,0
4429)
4430)
4431)
4432*150 (CptPort
4433uid 2327,0
4434ps "OnEdgeStrategy"
4435shape (Triangle
4436uid 2328,0
4437ro 90
4438va (VaSet
4439vasetType 1
4440fg "0,65535,0"
4441)
4442xt "122250,25625,123000,26375"
4443)
4444tg (CPTG
4445uid 2329,0
4446ps "CptPortTextPlaceStrategy"
4447stg "VerticalLayoutStrategy"
4448f (Text
4449uid 2330,0
4450va (VaSet
4451)
4452xt "124000,25500,125400,26500"
4453st "wr"
4454blo "124000,26300"
4455)
4456)
4457thePort (LogicalPort
4458decl (Decl
4459n "wr"
4460t "std_logic"
4461preAdd 0
4462posAdd 0
4463o 6
4464suid 4,0
4465)
4466)
4467)
4468*151 (CptPort
4469uid 2331,0
4470ps "OnEdgeStrategy"
4471shape (Triangle
4472uid 2332,0
4473ro 270
4474va (VaSet
4475vasetType 1
4476fg "0,65535,0"
4477)
4478xt "122250,26625,123000,27375"
4479)
4480tg (CPTG
4481uid 2333,0
4482ps "CptPortTextPlaceStrategy"
4483stg "VerticalLayoutStrategy"
4484f (Text
4485uid 2334,0
4486va (VaSet
4487)
4488xt "124000,26500,125400,27500"
4489st "int"
4490blo "124000,27300"
4491)
4492)
4493thePort (LogicalPort
4494m 1
4495decl (Decl
4496n "int"
4497t "std_logic"
4498o 1
4499suid 5,0
4500i "'1'"
4501)
4502)
4503)
4504*152 (CptPort
4505uid 2548,0
4506ps "OnEdgeStrategy"
4507shape (Triangle
4508uid 2549,0
4509ro 90
4510va (VaSet
4511vasetType 1
4512fg "0,65535,0"
4513)
4514xt "122250,27625,123000,28375"
4515)
4516tg (CPTG
4517uid 2550,0
4518ps "CptPortTextPlaceStrategy"
4519stg "VerticalLayoutStrategy"
4520f (Text
4521uid 2551,0
4522va (VaSet
4523)
4524xt "124000,27500,125200,28500"
4525st "cs"
4526blo "124000,28300"
4527)
4528)
4529thePort (LogicalPort
4530decl (Decl
4531n "cs"
4532t "std_logic"
4533o 5
4534suid 6,0
4535)
4536)
4537)
4538]
4539shape (Rectangle
4540uid 2337,0
4541va (VaSet
4542vasetType 1
4543fg "0,49152,49152"
4544lineColor "0,0,50000"
4545lineWidth 2
4546)
4547xt "123000,19000,133000,31000"
4548)
4549oxt "29000,0,39000,12000"
4550ttg (MlTextGroup
4551uid 2338,0
4552ps "CenterOffsetStrategy"
4553stg "VerticalLayoutStrategy"
4554textVec [
4555*153 (Text
4556uid 2339,0
4557va (VaSet
4558font "Arial,8,1"
4559)
4560xt "123200,31000,130900,32000"
4561st "FACT_FAD_TB_lib"
4562blo "123200,31800"
4563tm "BdLibraryNameMgr"
4564)
4565*154 (Text
4566uid 2340,0
4567va (VaSet
4568font "Arial,8,1"
4569)
4570xt "123200,32000,129800,33000"
4571st "w5300_emulator"
4572blo "123200,32800"
4573tm "CptNameMgr"
4574)
4575*155 (Text
4576uid 2341,0
4577va (VaSet
4578font "Arial,8,1"
4579)
4580xt "123200,33000,130000,34000"
4581st "I_mainTB_w5300"
4582blo "123200,33800"
4583tm "InstanceNameMgr"
4584)
4585]
4586)
4587ga (GenericAssociation
4588uid 2342,0
4589ps "EdgeToEdgeStrategy"
4590matrix (Matrix
4591uid 2343,0
4592text (MLText
4593uid 2344,0
4594va (VaSet
4595font "Courier New,8,0"
4596)
4597xt "123000,18000,123000,18000"
4598)
4599header ""
4600)
4601elements [
4602]
4603)
4604viewicon (ZoomableIcon
4605uid 2345,0
4606sl 0
4607va (VaSet
4608vasetType 1
4609fg "49152,49152,49152"
4610)
4611xt "123250,29250,124750,30750"
4612iconName "VhdlFileViewIcon.png"
4613iconMaskName "VhdlFileViewIcon.msk"
4614ftype 10
4615)
4616ordering 1
4617viewiconposition 0
4618portVis (PortSigDisplay
4619)
4620archFileType "UNKNOWN"
4621)
4622*156 (Wire
4623uid 286,0
4624shape (OrthoPolyLine
4625uid 287,0
4626va (VaSet
4627vasetType 3
4628)
4629xt "58750,21000,80250,21000"
4630pts [
4631"58750,21000"
4632"80250,21000"
4633]
4634)
4635start &59
4636end &27
4637sat 32
4638eat 32
4639st 0
4640sf 1
4641si 0
4642tg (WTG
4643uid 288,0
4644ps "ConnStartEndStrategy"
4645stg "STSignalDisplayStrategy"
4646f (Text
4647uid 289,0
4648va (VaSet
4649)
4650xt "71000,20000,72300,21000"
4651st "clk"
4652blo "71000,20800"
4653tm "WireNameMgr"
4654)
4655)
4656on &64
4657)
4658*157 (Wire
4659uid 318,0
4660shape (OrthoPolyLine
4661uid 319,0
4662va (VaSet
4663vasetType 3
4664lineWidth 2
4665)
4666xt "109750,21000,122250,21000"
4667pts [
4668"109750,21000"
4669"122250,21000"
4670]
4671)
4672start &19
4673end &147
4674sat 32
4675eat 32
4676sty 1
4677st 0
4678sf 1
4679si 0
4680tg (WTG
4681uid 320,0
4682ps "ConnStartEndStrategy"
4683stg "STSignalDisplayStrategy"
4684f (Text
4685uid 321,0
4686va (VaSet
4687)
4688xt "111000,20000,117000,21000"
4689st "wiz_addr : (9:0)"
4690blo "111000,20800"
4691tm "WireNameMgr"
4692)
4693)
4694on &65
4695)
4696*158 (Wire
4697uid 324,0
4698shape (OrthoPolyLine
4699uid 325,0
4700va (VaSet
4701vasetType 3
4702lineWidth 2
4703)
4704xt "109750,22000,122250,22000"
4705pts [
4706"109750,22000"
4707"122250,22000"
4708]
4709)
4710start &20
4711end &148
4712sat 32
4713eat 32
4714sty 1
4715st 0
4716sf 1
4717si 0
4718tg (WTG
4719uid 326,0
4720ps "ConnStartEndStrategy"
4721stg "STSignalDisplayStrategy"
4722f (Text
4723uid 327,0
4724va (VaSet
4725)
4726xt "111000,21000,117300,22000"
4727st "wiz_data : (15:0)"
4728blo "111000,21800"
4729tm "WireNameMgr"
4730)
4731)
4732on &66
4733)
4734*159 (Wire
4735uid 330,0
4736shape (OrthoPolyLine
4737uid 331,0
4738va (VaSet
4739vasetType 3
4740)
4741xt "109750,25000,122250,25000"
4742pts [
4743"109750,25000"
4744"122250,25000"
4745]
4746)
4747start &23
4748end &149
4749sat 32
4750eat 32
4751st 0
4752sf 1
4753si 0
4754tg (WTG
4755uid 332,0
4756ps "ConnStartEndStrategy"
4757stg "STSignalDisplayStrategy"
4758f (Text
4759uid 333,0
4760va (VaSet
4761)
4762xt "111000,24000,113600,25000"
4763st "wiz_rd"
4764blo "111000,24800"
4765tm "WireNameMgr"
4766)
4767)
4768on &67
4769)
4770*160 (Wire
4771uid 336,0
4772shape (OrthoPolyLine
4773uid 337,0
4774va (VaSet
4775vasetType 3
4776)
4777xt "109750,26000,122250,26000"
4778pts [
4779"109750,26000"
4780"122250,26000"
4781]
4782)
4783start &22
4784end &150
4785sat 32
4786eat 32
4787st 0
4788sf 1
4789si 0
4790tg (WTG
4791uid 338,0
4792ps "ConnStartEndStrategy"
4793stg "STSignalDisplayStrategy"
4794f (Text
4795uid 339,0
4796va (VaSet
4797)
4798xt "111000,25000,113700,26000"
4799st "wiz_wr"
4800blo "111000,25800"
4801tm "WireNameMgr"
4802)
4803)
4804on &68
4805)
4806*161 (Wire
4807uid 374,0
4808shape (OrthoPolyLine
4809uid 375,0
4810va (VaSet
4811vasetType 3
4812lineWidth 2
4813)
4814xt "109750,42000,122250,48000"
4815pts [
4816"109750,42000"
4817"120000,42000"
4818"120000,48000"
4819"122250,48000"
4820]
4821)
4822start &41
4823end &72
4824sat 32
4825eat 32
4826sty 1
4827st 0
4828sf 1
4829si 0
4830tg (WTG
4831uid 376,0
4832ps "ConnStartEndStrategy"
4833stg "STSignalDisplayStrategy"
4834f (Text
4835uid 377,0
4836va (VaSet
4837)
4838xt "111000,41000,117500,42000"
4839st "sensor_cs : (3:0)"
4840blo "111000,41800"
4841tm "WireNameMgr"
4842)
4843)
4844on &76
4845)
4846*162 (Wire
4847uid 380,0
4848shape (OrthoPolyLine
4849uid 381,0
4850va (VaSet
4851vasetType 3
4852)
4853xt "109750,51000,122250,51000"
4854pts [
4855"109750,51000"
4856"122250,51000"
4857]
4858)
4859start &38
4860end &70
4861sat 32
4862eat 32
4863st 0
4864sf 1
4865si 0
4866tg (WTG
4867uid 382,0
4868ps "ConnStartEndStrategy"
4869stg "STSignalDisplayStrategy"
4870f (Text
4871uid 383,0
4872va (VaSet
4873)
4874xt "111000,50000,112700,51000"
4875st "sclk"
4876blo "111000,50800"
4877tm "WireNameMgr"
4878)
4879)
4880on &77
4881)
4882*163 (Wire
4883uid 386,0
4884shape (OrthoPolyLine
4885uid 387,0
4886va (VaSet
4887vasetType 3
4888)
4889xt "109750,52000,122250,52000"
4890pts [
4891"109750,52000"
4892"122250,52000"
4893]
4894)
4895start &39
4896end &71
4897sat 32
4898eat 32
4899st 0
4900sf 1
4901si 0
4902tg (WTG
4903uid 388,0
4904ps "ConnStartEndStrategy"
4905stg "STSignalDisplayStrategy"
4906f (Text
4907uid 389,0
4908va (VaSet
4909)
4910xt "111000,51000,112400,52000"
4911st "sio"
4912blo "111000,51800"
4913tm "WireNameMgr"
4914)
4915)
4916on &78
4917)
4918*164 (Wire
4919uid 426,0
4920shape (OrthoPolyLine
4921uid 427,0
4922va (VaSet
4923vasetType 3
4924)
4925xt "58750,32000,80250,32000"
4926pts [
4927"58750,32000"
4928"80250,32000"
4929]
4930)
4931start &80
4932end &15
4933sat 32
4934eat 32
4935st 0
4936sf 1
4937tg (WTG
4938uid 428,0
4939ps "ConnStartEndStrategy"
4940stg "STSignalDisplayStrategy"
4941f (Text
4942uid 429,0
4943va (VaSet
4944)
4945xt "71000,31000,73800,32000"
4946st "trigger"
4947blo "71000,31800"
4948tm "WireNameMgr"
4949)
4950)
4951on &84
4952)
4953*165 (Wire
4954uid 442,0
4955shape (OrthoPolyLine
4956uid 443,0
4957va (VaSet
4958vasetType 3
4959lineWidth 2
4960)
4961xt "58000,34000,80250,42000"
4962pts [
4963"80250,34000"
4964"64000,34000"
4965"64000,42000"
4966"58000,42000"
4967]
4968)
4969start &17
4970end &85
4971sat 32
4972eat 2
4973sty 1
4974st 0
4975sf 1
4976si 0
4977tg (WTG
4978uid 446,0
4979ps "ConnStartEndStrategy"
4980stg "STSignalDisplayStrategy"
4981f (Text
4982uid 447,0
4983va (VaSet
4984)
4985xt "71000,33000,76900,34000"
4986st "board_id : (3:0)"
4987blo "71000,33800"
4988tm "WireNameMgr"
4989)
4990)
4991on &89
4992)
4993*166 (Wire
4994uid 450,0
4995shape (OrthoPolyLine
4996uid 451,0
4997va (VaSet
4998vasetType 3
4999lineWidth 2
5000)
5001xt "58000,35000,80250,43000"
5002pts [
5003"80250,35000"
5004"65000,35000"
5005"65000,43000"
5006"58000,43000"
5007]
5008)
5009start &18
5010end &85
5011sat 32
5012eat 2
5013sty 1
5014st 0
5015sf 1
5016si 0
5017tg (WTG
5018uid 454,0
5019ps "ConnStartEndStrategy"
5020stg "STSignalDisplayStrategy"
5021f (Text
5022uid 455,0
5023va (VaSet
5024)
5025xt "71000,34000,76700,35000"
5026st "crate_id : (1:0)"
5027blo "71000,34800"
5028tm "WireNameMgr"
5029)
5030)
5031on &90
5032)
5033*167 (Wire
5034uid 530,0
5035shape (OrthoPolyLine
5036uid 531,0
5037va (VaSet
5038vasetType 3
5039lineWidth 2
5040)
5041xt "58000,42000,80250,53000"
5042pts [
5043"80250,42000"
5044"68000,42000"
5045"68000,53000"
5046"58000,53000"
5047]
5048)
5049start &28
5050end &99
5051sat 32
5052eat 2
5053sty 1
5054st 0
5055sf 1
5056si 0
5057tg (WTG
5058uid 534,0
5059ps "ConnStartEndStrategy"
5060stg "STSignalDisplayStrategy"
5061f (Text
5062uid 535,0
5063va (VaSet
5064)
5065xt "71000,41000,79000,42000"
5066st "adc_otr_array : (3:0)"
5067blo "71000,41800"
5068tm "WireNameMgr"
5069)
5070)
5071on &103
5072)
5073*168 (Wire
5074uid 538,0
5075shape (OrthoPolyLine
5076uid 539,0
5077va (VaSet
5078vasetType 3
5079lineWidth 2
5080)
5081xt "58000,48000,80250,55000"
5082pts [
5083"80250,48000"
5084"70000,48000"
5085"70000,55000"
5086"58000,55000"
5087]
5088)
5089start &29
5090end &99
5091sat 32
5092eat 2
5093sty 1
5094st 0
5095sf 1
5096si 0
5097tg (WTG
5098uid 542,0
5099ps "ConnStartEndStrategy"
5100stg "STSignalDisplayStrategy"
5101f (Text
5102uid 543,0
5103va (VaSet
5104)
5105xt "71000,47000,76900,48000"
5106st "adc_data_array"
5107blo "71000,47800"
5108tm "WireNameMgr"
5109)
5110)
5111on &104
5112)
5113*169 (Wire
5114uid 546,0
5115shape (OrthoPolyLine
5116uid 547,0
5117va (VaSet
5118vasetType 3
5119)
5120xt "58000,43000,80250,54000"
5121pts [
5122"80250,43000"
5123"69000,43000"
5124"69000,54000"
5125"58000,54000"
5126]
5127)
5128start &16
5129end &99
5130sat 32
5131eat 1
5132st 0
5133sf 1
5134si 0
5135tg (WTG
5136uid 550,0
5137ps "ConnStartEndStrategy"
5138stg "STSignalDisplayStrategy"
5139f (Text
5140uid 551,0
5141va (VaSet
5142)
5143xt "71000,42000,74200,43000"
5144st "adc_oeb"
5145blo "71000,42800"
5146tm "WireNameMgr"
5147)
5148)
5149on &105
5150)
5151*170 (Wire
5152uid 554,0
5153shape (OrthoPolyLine
5154uid 555,0
5155va (VaSet
5156vasetType 3
5157)
5158xt "40750,54000,50000,54000"
5159pts [
5160"50000,54000"
5161"40750,54000"
5162]
5163)
5164start &99
5165end &95
5166sat 2
5167eat 32
5168st 0
5169sf 1
5170tg (WTG
5171uid 558,0
5172ps "ConnStartEndStrategy"
5173stg "STSignalDisplayStrategy"
5174f (Text
5175uid 559,0
5176va (VaSet
5177)
5178xt "42000,53000,45200,54000"
5179st "adc_oeb"
5180blo "42000,53800"
5181tm "WireNameMgr"
5182)
5183)
5184on &105
5185)
5186*171 (Wire
5187uid 562,0
5188shape (OrthoPolyLine
5189uid 563,0
5190va (VaSet
5191vasetType 3
5192)
5193xt "40750,53000,50000,53000"
5194pts [
5195"40750,53000"
5196"50000,53000"
5197]
5198)
5199start &94
5200end &99
5201sat 32
5202eat 1
5203st 0
5204sf 1
5205tg (WTG
5206uid 566,0
5207ps "ConnStartEndStrategy"
5208stg "STSignalDisplayStrategy"
5209f (Text
5210uid 567,0
5211va (VaSet
5212)
5213xt "42000,52000,44900,53000"
5214st "adc_otr"
5215blo "42000,52800"
5216tm "WireNameMgr"
5217)
5218)
5219on &106
5220)
5221*172 (Wire
5222uid 570,0
5223shape (OrthoPolyLine
5224uid 571,0
5225va (VaSet
5226vasetType 3
5227lineWidth 2
5228)
5229xt "40750,55000,50000,55000"
5230pts [
5231"40750,55000"
5232"50000,55000"
5233]
5234)
5235start &93
5236end &99
5237sat 32
5238eat 1
5239sty 1
5240st 0
5241sf 1
5242tg (WTG
5243uid 574,0
5244ps "ConnStartEndStrategy"
5245stg "STSignalDisplayStrategy"
5246f (Text
5247uid 575,0
5248va (VaSet
5249)
5250xt "42000,54000,48400,55000"
5251st "adc_data : (11:0)"
5252blo "42000,54800"
5253tm "WireNameMgr"
5254)
5255)
5256on &107
5257)
5258*173 (Wire
5259uid 578,0
5260shape (OrthoPolyLine
5261uid 579,0
5262va (VaSet
5263vasetType 3
5264)
5265xt "24000,53000,29250,53000"
5266pts [
5267"29250,53000"
5268"24000,53000"
5269]
5270)
5271start &92
5272sat 32
5273eat 16
5274st 0
5275sf 1
5276tg (WTG
5277uid 582,0
5278ps "ConnStartEndStrategy"
5279stg "STSignalDisplayStrategy"
5280f (Text
5281uid 583,0
5282va (VaSet
5283)
5284xt "25000,52000,29000,53000"
5285st "ADC_CLK"
5286blo "25000,52800"
5287tm "WireNameMgr"
5288)
5289)
5290on &144
5291)
5292*174 (Wire
5293uid 769,0
5294shape (OrthoPolyLine
5295uid 770,0
5296va (VaSet
5297vasetType 3
5298)
5299xt "109750,24000,116000,24000"
5300pts [
5301"109750,24000"
5302"116000,24000"
5303]
5304)
5305start &13
5306sat 32
5307eat 16
5308st 0
5309sf 1
5310si 0
5311tg (WTG
5312uid 773,0
5313ps "ConnStartEndStrategy"
5314stg "STSignalDisplayStrategy"
5315f (Text
5316uid 774,0
5317va (VaSet
5318)
5319xt "111000,23000,114600,24000"
5320st "wiz_reset"
5321blo "111000,23800"
5322tm "WireNameMgr"
5323)
5324)
5325on &108
5326)
5327*175 (Wire
5328uid 777,0
5329shape (OrthoPolyLine
5330uid 778,0
5331va (VaSet
5332vasetType 3
5333lineWidth 2
5334)
5335xt "109750,70000,116000,70000"
5336pts [
5337"109750,70000"
5338"116000,70000"
5339]
5340)
5341start &14
5342sat 32
5343eat 16
5344sty 1
5345st 0
5346sf 1
5347si 0
5348tg (WTG
5349uid 781,0
5350ps "ConnStartEndStrategy"
5351stg "STSignalDisplayStrategy"
5352f (Text
5353uid 782,0
5354va (VaSet
5355)
5356xt "111000,69000,115000,70000"
5357st "led : (7:0)"
5358blo "111000,69800"
5359tm "WireNameMgr"
5360)
5361)
5362on &109
5363)
5364*176 (Wire
5365uid 785,0
5366shape (OrthoPolyLine
5367uid 786,0
5368va (VaSet
5369vasetType 3
5370)
5371xt "109750,28000,122250,28000"
5372pts [
5373"109750,28000"
5374"122250,28000"
5375]
5376)
5377start &21
5378end &152
5379sat 32
5380eat 32
5381st 0
5382sf 1
5383si 0
5384tg (WTG
5385uid 789,0
5386ps "ConnStartEndStrategy"
5387stg "STSignalDisplayStrategy"
5388f (Text
5389uid 790,0
5390va (VaSet
5391)
5392xt "111000,27000,113700,28000"
5393st "wiz_cs"
5394blo "111000,27800"
5395tm "WireNameMgr"
5396)
5397)
5398on &110
5399)
5400*177 (Wire
5401uid 793,0
5402shape (OrthoPolyLine
5403uid 794,0
5404va (VaSet
5405vasetType 3
5406)
5407xt "109750,27000,122250,27000"
5408pts [
5409"122250,27000"
5410"109750,27000"
5411]
5412)
5413start &151
5414end &24
5415sat 32
5416eat 32
5417st 0
5418sf 1
5419si 0
5420tg (WTG
5421uid 797,0
5422ps "ConnStartEndStrategy"
5423stg "STSignalDisplayStrategy"
5424f (Text
5425uid 798,0
5426va (VaSet
5427)
5428xt "111000,26000,113700,27000"
5429st "wiz_int"
5430blo "111000,26800"
5431tm "WireNameMgr"
5432)
5433)
5434on &111
5435)
5436*178 (Wire
5437uid 801,0
5438shape (OrthoPolyLine
5439uid 802,0
5440va (VaSet
5441vasetType 3
5442)
5443xt "109750,40000,116000,40000"
5444pts [
5445"109750,40000"
5446"116000,40000"
5447]
5448)
5449start &40
5450sat 32
5451eat 16
5452st 0
5453sf 1
5454si 0
5455tg (WTG
5456uid 805,0
5457ps "ConnStartEndStrategy"
5458stg "STSignalDisplayStrategy"
5459f (Text
5460uid 806,0
5461va (VaSet
5462)
5463xt "111000,39000,113800,40000"
5464st "dac_cs"
5465blo "111000,39800"
5466tm "WireNameMgr"
5467)
5468)
5469on &112
5470)
5471*179 (Wire
5472uid 809,0
5473shape (OrthoPolyLine
5474uid 810,0
5475va (VaSet
5476vasetType 3
5477)
5478xt "109750,53000,116000,53000"
5479pts [
5480"109750,53000"
5481"116000,53000"
5482]
5483)
5484start &42
5485sat 32
5486eat 16
5487st 0
5488sf 1
5489si 0
5490tg (WTG
5491uid 813,0
5492ps "ConnStartEndStrategy"
5493stg "STSignalDisplayStrategy"
5494f (Text
5495uid 814,0
5496va (VaSet
5497)
5498xt "111000,52000,113000,53000"
5499st "mosi"
5500blo "111000,52800"
5501tm "WireNameMgr"
5502)
5503)
5504on &113
5505)
5506*180 (Wire
5507uid 817,0
5508shape (OrthoPolyLine
5509uid 818,0
5510va (VaSet
5511vasetType 3
5512)
5513xt "70000,66000,80250,66000"
5514pts [
5515"80250,66000"
5516"70000,66000"
5517]
5518)
5519start &43
5520sat 32
5521eat 16
5522st 0
5523sf 1
5524si 0
5525tg (WTG
5526uid 821,0
5527ps "ConnStartEndStrategy"
5528stg "STSignalDisplayStrategy"
5529f (Text
5530uid 822,0
5531va (VaSet
5532)
5533xt "71000,65000,74000,66000"
5534st "denable"
5535blo "71000,65800"
5536tm "WireNameMgr"
5537)
5538)
5539on &114
5540)
5541*181 (Wire
5542uid 825,0
5543shape (OrthoPolyLine
5544uid 826,0
5545va (VaSet
5546vasetType 3
5547)
5548xt "70000,23000,80250,23000"
5549pts [
5550"80250,23000"
5551"70000,23000"
5552]
5553)
5554start &25
5555sat 32
5556eat 16
5557st 0
5558sf 1
5559si 0
5560tg (WTG
5561uid 829,0
5562ps "ConnStartEndStrategy"
5563stg "STSignalDisplayStrategy"
5564f (Text
5565uid 830,0
5566va (VaSet
5567)
5568xt "71000,22000,75500,23000"
5569st "CLK_25_PS"
5570blo "71000,22800"
5571tm "WireNameMgr"
5572)
5573)
5574on &115
5575)
5576*182 (Wire
5577uid 833,0
5578shape (OrthoPolyLine
5579uid 834,0
5580va (VaSet
5581vasetType 3
5582)
5583xt "70000,22000,80250,22000"
5584pts [
5585"80250,22000"
5586"70000,22000"
5587]
5588)
5589start &26
5590sat 32
5591eat 16
5592st 0
5593sf 1
5594si 0
5595tg (WTG
5596uid 837,0
5597ps "ConnStartEndStrategy"
5598stg "STSignalDisplayStrategy"
5599f (Text
5600uid 838,0
5601va (VaSet
5602)
5603xt "71000,21000,74100,22000"
5604st "CLK_50"
5605blo "71000,21800"
5606tm "WireNameMgr"
5607)
5608)
5609on &116
5610)
5611*183 (Wire
5612uid 841,0
5613shape (OrthoPolyLine
5614uid 842,0
5615va (VaSet
5616vasetType 3
5617lineWidth 2
5618)
5619xt "70000,62000,80250,62000"
5620pts [
5621"80250,62000"
5622"70000,62000"
5623]
5624)
5625start &30
5626sat 32
5627eat 16
5628sty 1
5629st 0
5630sf 1
5631si 0
5632tg (WTG
5633uid 845,0
5634ps "ConnStartEndStrategy"
5635stg "STSignalDisplayStrategy"
5636f (Text
5637uid 846,0
5638va (VaSet
5639)
5640xt "71000,61000,79500,62000"
5641st "drs_channel_id : (3:0)"
5642blo "71000,61800"
5643tm "WireNameMgr"
5644)
5645)
5646on &117
5647)
5648*184 (Wire
5649uid 849,0
5650shape (OrthoPolyLine
5651uid 850,0
5652va (VaSet
5653vasetType 3
5654)
5655xt "70000,67000,80250,67000"
5656pts [
5657"80250,67000"
5658"70000,67000"
5659]
5660)
5661start &31
5662ss 0
5663sat 32
5664eat 16
5665st 0
5666sf 1
5667si 0
5668tg (WTG
5669uid 853,0
5670ps "ConnStartEndStrategy"
5671stg "STSignalDisplayStrategy"
5672f (Text
5673uid 854,0
5674va (VaSet
5675)
5676xt "71000,66000,75300,67000"
5677st "drs_dwrite"
5678blo "71000,66800"
5679tm "WireNameMgr"
5680)
5681)
5682on &118
5683)
5684*185 (Wire
5685uid 857,0
5686shape (OrthoPolyLine
5687uid 858,0
5688va (VaSet
5689vasetType 3
5690)
5691xt "70000,64000,80250,64000"
5692pts [
5693"80250,64000"
5694"70000,64000"
5695]
5696)
5697start &36
5698sat 32
5699eat 16
5700st 0
5701sf 1
5702si 0
5703tg (WTG
5704uid 861,0
5705ps "ConnStartEndStrategy"
5706stg "STSignalDisplayStrategy"
5707f (Text
5708uid 862,0
5709va (VaSet
5710)
5711xt "71000,63000,75200,64000"
5712st "RSRLOAD"
5713blo "71000,63800"
5714tm "WireNameMgr"
5715)
5716)
5717on &119
5718)
5719*186 (Wire
5720uid 865,0
5721shape (OrthoPolyLine
5722uid 866,0
5723va (VaSet
5724vasetType 3
5725)
5726xt "70000,65000,80250,65000"
5727pts [
5728"80250,65000"
5729"70000,65000"
5730]
5731)
5732start &37
5733sat 32
5734eat 16
5735st 0
5736sf 1
5737si 0
5738tg (WTG
5739uid 869,0
5740ps "ConnStartEndStrategy"
5741stg "STSignalDisplayStrategy"
5742f (Text
5743uid 870,0
5744va (VaSet
5745)
5746xt "71000,64000,74000,65000"
5747st "SRCLK"
5748blo "71000,64800"
5749tm "WireNameMgr"
5750)
5751)
5752on &120
5753)
5754*187 (Wire
5755uid 873,0
5756shape (OrthoPolyLine
5757uid 874,0
5758va (VaSet
5759vasetType 3
5760)
5761xt "70000,58000,80250,58000"
5762pts [
5763"70000,58000"
5764"80250,58000"
5765]
5766)
5767end &32
5768sat 16
5769eat 32
5770st 0
5771sf 1
5772si 0
5773tg (WTG
5774uid 877,0
5775ps "ConnStartEndStrategy"
5776stg "STSignalDisplayStrategy"
5777f (Text
5778uid 878,0
5779va (VaSet
5780)
5781xt "71000,57000,76400,58000"
5782st "SROUT_in_0"
5783blo "71000,57800"
5784tm "WireNameMgr"
5785)
5786)
5787on &121
5788)
5789*188 (Wire
5790uid 881,0
5791shape (OrthoPolyLine
5792uid 882,0
5793va (VaSet
5794vasetType 3
5795)
5796xt "70000,59000,80250,59000"
5797pts [
5798"70000,59000"
5799"80250,59000"
5800]
5801)
5802end &33
5803sat 16
5804eat 32
5805st 0
5806sf 1
5807si 0
5808tg (WTG
5809uid 885,0
5810ps "ConnStartEndStrategy"
5811stg "STSignalDisplayStrategy"
5812f (Text
5813uid 886,0
5814va (VaSet
5815)
5816xt "71000,58000,76400,59000"
5817st "SROUT_in_1"
5818blo "71000,58800"
5819tm "WireNameMgr"
5820)
5821)
5822on &122
5823)
5824*189 (Wire
5825uid 889,0
5826shape (OrthoPolyLine
5827uid 890,0
5828va (VaSet
5829vasetType 3
5830)
5831xt "70000,60000,80250,60000"
5832pts [
5833"70000,60000"
5834"80250,60000"
5835]
5836)
5837end &34
5838sat 16
5839eat 32
5840st 0
5841sf 1
5842si 0
5843tg (WTG
5844uid 893,0
5845ps "ConnStartEndStrategy"
5846stg "STSignalDisplayStrategy"
5847f (Text
5848uid 894,0
5849va (VaSet
5850)
5851xt "71000,59000,76400,60000"
5852st "SROUT_in_2"
5853blo "71000,59800"
5854tm "WireNameMgr"
5855)
5856)
5857on &123
5858)
5859*190 (Wire
5860uid 897,0
5861shape (OrthoPolyLine
5862uid 898,0
5863va (VaSet
5864vasetType 3
5865)
5866xt "70000,61000,80250,61000"
5867pts [
5868"70000,61000"
5869"80250,61000"
5870]
5871)
5872end &35
5873sat 16
5874eat 32
5875st 0
5876sf 1
5877si 0
5878tg (WTG
5879uid 901,0
5880ps "ConnStartEndStrategy"
5881stg "STSignalDisplayStrategy"
5882f (Text
5883uid 902,0
5884va (VaSet
5885)
5886xt "71000,60000,76400,61000"
5887st "SROUT_in_3"
5888blo "71000,60800"
5889tm "WireNameMgr"
5890)
5891)
5892on &124
5893)
5894*191 (Wire
5895uid 1437,0
5896shape (OrthoPolyLine
5897uid 1438,0
5898va (VaSet
5899vasetType 3
5900)
5901xt "73000,72000,80250,72000"
5902pts [
5903"80250,72000"
5904"73000,72000"
5905]
5906)
5907start &53
5908sat 32
5909eat 16
5910st 0
5911sf 1
5912si 0
5913tg (WTG
5914uid 1441,0
5915ps "ConnStartEndStrategy"
5916stg "STSignalDisplayStrategy"
5917f (Text
5918uid 1442,0
5919va (VaSet
5920)
5921xt "76000,72000,79700,73000"
5922st "SRIN_out"
5923blo "76000,72800"
5924tm "WireNameMgr"
5925)
5926)
5927on &125
5928)
5929*192 (Wire
5930uid 1445,0
5931shape (OrthoPolyLine
5932uid 1446,0
5933va (VaSet
5934vasetType 3
5935)
5936xt "109750,80000,115000,80000"
5937pts [
5938"109750,80000"
5939"115000,80000"
5940]
5941)
5942start &46
5943sat 32
5944eat 16
5945st 0
5946sf 1
5947si 0
5948tg (WTG
5949uid 1449,0
5950ps "ConnStartEndStrategy"
5951stg "STSignalDisplayStrategy"
5952f (Text
5953uid 1450,0
5954va (VaSet
5955)
5956xt "111000,79000,113500,80000"
5957st "amber"
5958blo "111000,79800"
5959tm "WireNameMgr"
5960)
5961)
5962on &126
5963)
5964*193 (Wire
5965uid 1453,0
5966shape (OrthoPolyLine
5967uid 1454,0
5968va (VaSet
5969vasetType 3
5970)
5971xt "109750,79000,114000,79000"
5972pts [
5973"109750,79000"
5974"114000,79000"
5975]
5976)
5977start &52
5978sat 32
5979eat 16
5980st 0
5981sf 1
5982si 0
5983tg (WTG
5984uid 1457,0
5985ps "ConnStartEndStrategy"
5986stg "STSignalDisplayStrategy"
5987f (Text
5988uid 1458,0
5989va (VaSet
5990)
5991xt "111000,78000,112500,79000"
5992st "red"
5993blo "111000,78800"
5994tm "WireNameMgr"
5995)
5996)
5997on &127
5998)
5999*194 (Wire
6000uid 1461,0
6001shape (OrthoPolyLine
6002uid 1462,0
6003va (VaSet
6004vasetType 3
6005)
6006xt "109750,78000,114000,78000"
6007pts [
6008"109750,78000"
6009"114000,78000"
6010]
6011)
6012start &50
6013sat 32
6014eat 16
6015st 0
6016sf 1
6017si 0
6018tg (WTG
6019uid 1465,0
6020ps "ConnStartEndStrategy"
6021stg "STSignalDisplayStrategy"
6022f (Text
6023uid 1466,0
6024va (VaSet
6025)
6026xt "111000,77000,113400,78000"
6027st "green"
6028blo "111000,77800"
6029tm "WireNameMgr"
6030)
6031)
6032on &128
6033)
6034*195 (Wire
6035uid 1469,0
6036shape (OrthoPolyLine
6037uid 1470,0
6038va (VaSet
6039vasetType 3
6040lineWidth 2
6041)
6042xt "109750,77000,121000,77000"
6043pts [
6044"109750,77000"
6045"121000,77000"
6046]
6047)
6048start &47
6049sat 32
6050eat 16
6051sty 1
6052st 0
6053sf 1
6054si 0
6055tg (WTG
6056uid 1473,0
6057ps "ConnStartEndStrategy"
6058stg "STSignalDisplayStrategy"
6059f (Text
6060uid 1474,0
6061va (VaSet
6062)
6063xt "111000,76000,119600,77000"
6064st "counter_result : (11:0)"
6065blo "111000,76800"
6066tm "WireNameMgr"
6067)
6068)
6069on &129
6070)
6071*196 (Wire
6072uid 1477,0
6073shape (OrthoPolyLine
6074uid 1478,0
6075va (VaSet
6076vasetType 3
6077)
6078xt "109750,75000,120000,75000"
6079pts [
6080"109750,75000"
6081"120000,75000"
6082]
6083)
6084start &45
6085sat 32
6086eat 16
6087st 0
6088sf 1
6089si 0
6090tg (WTG
6091uid 1481,0
6092ps "ConnStartEndStrategy"
6093stg "STSignalDisplayStrategy"
6094f (Text
6095uid 1482,0
6096va (VaSet
6097)
6098xt "111000,74000,119200,75000"
6099st "alarm_refclk_too_low"
6100blo "111000,74800"
6101tm "WireNameMgr"
6102)
6103)
6104on &130
6105)
6106*197 (Wire
6107uid 1485,0
6108shape (OrthoPolyLine
6109uid 1486,0
6110va (VaSet
6111vasetType 3
6112)
6113xt "109750,74000,121000,74000"
6114pts [
6115"109750,74000"
6116"121000,74000"
6117]
6118)
6119start &44
6120sat 32
6121eat 16
6122st 0
6123sf 1
6124si 0
6125tg (WTG
6126uid 1489,0
6127ps "ConnStartEndStrategy"
6128stg "STSignalDisplayStrategy"
6129f (Text
6130uid 1490,0
6131va (VaSet
6132)
6133xt "111000,73000,119600,74000"
6134st "alarm_refclk_too_high"
6135blo "111000,73800"
6136tm "WireNameMgr"
6137)
6138)
6139on &131
6140)
6141*198 (Wire
6142uid 1503,0
6143shape (OrthoPolyLine
6144uid 1504,0
6145va (VaSet
6146vasetType 3
6147lineWidth 2
6148)
6149xt "73000,75000,80250,75000"
6150pts [
6151"73000,75000"
6152"80250,75000"
6153]
6154)
6155end &48
6156sat 16
6157eat 32
6158sty 1
6159st 0
6160sf 1
6161si 0
6162tg (WTG
6163uid 1507,0
6164ps "ConnStartEndStrategy"
6165stg "STSignalDisplayStrategy"
6166f (Text
6167uid 1508,0
6168va (VaSet
6169)
6170xt "74000,74000,79500,75000"
6171st "D_T_in : (1:0)"
6172blo "74000,74800"
6173tm "WireNameMgr"
6174)
6175)
6176on &136
6177)
6178*199 (Wire
6179uid 1529,0
6180shape (OrthoPolyLine
6181uid 1530,0
6182va (VaSet
6183vasetType 3
6184)
6185xt "66750,76000,80250,79000"
6186pts [
6187"66750,79000"
6188"70000,79000"
6189"70000,76000"
6190"80250,76000"
6191]
6192)
6193start &138
6194end &49
6195sat 32
6196eat 32
6197st 0
6198sf 1
6199si 0
6200tg (WTG
6201uid 1531,0
6202ps "ConnStartEndStrategy"
6203stg "STSignalDisplayStrategy"
6204f (Text
6205uid 1532,0
6206va (VaSet
6207)
6208xt "68750,78000,72650,79000"
6209st "REF_CLK"
6210blo "68750,78800"
6211tm "WireNameMgr"
6212)
6213)
6214on &145
6215)
6216*200 (Wire
6217uid 1533,0
6218shape (OrthoPolyLine
6219uid 1534,0
6220va (VaSet
6221vasetType 3
6222)
6223xt "35000,70000,45000,70000"
6224pts [
6225"35000,70000"
6226"45000,70000"
6227]
6228)
6229start &132
6230sat 2
6231eat 16
6232st 0
6233sf 1
6234si 0
6235tg (WTG
6236uid 1539,0
6237ps "ConnStartEndStrategy"
6238stg "STSignalDisplayStrategy"
6239f (Text
6240uid 1540,0
6241va (VaSet
6242)
6243xt "37000,69000,42500,70000"
6244st "D_T_in : (1:0)"
6245blo "37000,69800"
6246tm "WireNameMgr"
6247)
6248)
6249on &136
6250)
6251*201 (Wire
6252uid 1561,0
6253shape (OrthoPolyLine
6254uid 1562,0
6255va (VaSet
6256vasetType 3
6257lineWidth 2
6258)
6259xt "72000,77000,80250,77000"
6260pts [
6261"72000,77000"
6262"80250,77000"
6263]
6264)
6265end &51
6266sat 16
6267eat 32
6268sty 1
6269st 0
6270sf 1
6271si 0
6272tg (WTG
6273uid 1565,0
6274ps "ConnStartEndStrategy"
6275stg "STSignalDisplayStrategy"
6276f (Text
6277uid 1566,0
6278va (VaSet
6279)
6280xt "73000,76000,79100,77000"
6281st "plllock_in : (3:0)"
6282blo "73000,76800"
6283tm "WireNameMgr"
6284)
6285)
6286on &143
6287)
6288*202 (Wire
6289uid 1567,0
6290shape (OrthoPolyLine
6291uid 1568,0
6292va (VaSet
6293vasetType 3
6294)
6295xt "35000,71000,45000,71000"
6296pts [
6297"35000,71000"
6298"45000,71000"
6299]
6300)
6301start &132
6302sat 2
6303eat 16
6304st 0
6305sf 1
6306si 0
6307tg (WTG
6308uid 1573,0
6309ps "ConnStartEndStrategy"
6310stg "STSignalDisplayStrategy"
6311f (Text
6312uid 1574,0
6313va (VaSet
6314)
6315xt "37000,70000,43100,71000"
6316st "plllock_in : (3:0)"
6317blo "37000,70800"
6318tm "WireNameMgr"
6319)
6320)
6321on &143
6322)
6323*203 (Wire
6324uid 1684,0
6325shape (OrthoPolyLine
6326uid 1685,0
6327va (VaSet
6328vasetType 3
6329)
6330xt "70000,24000,80250,24000"
6331pts [
6332"80250,24000"
6333"70000,24000"
6334]
6335)
6336start &54
6337sat 32
6338eat 16
6339st 0
6340sf 1
6341si 0
6342tg (WTG
6343uid 1688,0
6344ps "ConnStartEndStrategy"
6345stg "STSignalDisplayStrategy"
6346f (Text
6347uid 1689,0
6348va (VaSet
6349)
6350xt "71000,23000,75000,24000"
6351st "ADC_CLK"
6352blo "71000,23800"
6353tm "WireNameMgr"
6354)
6355)
6356on &144
6357)
6358]
6359bg "65535,65535,65535"
6360grid (Grid
6361origin "0,0"
6362isVisible 1
6363isActive 1
6364xSpacing 1000
6365xySpacing 1000
6366xShown 1
6367yShown 1
6368color "26368,26368,26368"
6369)
6370packageList *204 (PackageList
6371uid 41,0
6372stg "VerticalLayoutStrategy"
6373textVec [
6374*205 (Text
6375uid 42,0
6376va (VaSet
6377font "arial,8,1"
6378)
6379xt "-87000,0,-81600,1000"
6380st "Package List"
6381blo "-87000,800"
6382)
6383*206 (MLText
6384uid 43,0
6385va (VaSet
6386)
6387xt "-87000,1000,-70900,11000"
6388st "LIBRARY ieee;
6389USE ieee.std_logic_1164.all;
6390USE ieee.std_logic_arith.all;
6391USE ieee.std_logic_unsigned.all;
6392
6393LIBRARY FACT_FAD_lib;
6394USE FACT_FAD_lib.fad_definitions.all;
6395USE ieee.std_logic_textio.all;
6396LIBRARY std;
6397USE std.textio.all;"
6398tm "PackageList"
6399)
6400]
6401)
6402compDirBlock (MlTextGroup
6403uid 44,0
6404stg "VerticalLayoutStrategy"
6405textVec [
6406*207 (Text
6407uid 45,0
6408va (VaSet
6409isHidden 1
6410font "Arial,8,1"
6411)
6412xt "20000,0,28100,1000"
6413st "Compiler Directives"
6414blo "20000,800"
6415)
6416*208 (Text
6417uid 46,0
6418va (VaSet
6419isHidden 1
6420font "Arial,8,1"
6421)
6422xt "20000,1000,29600,2000"
6423st "Pre-module directives:"
6424blo "20000,1800"
6425)
6426*209 (MLText
6427uid 47,0
6428va (VaSet
6429isHidden 1
6430)
6431xt "20000,2000,28200,4000"
6432st "`resetall
6433`timescale 1ns/10ps"
6434tm "BdCompilerDirectivesTextMgr"
6435)
6436*210 (Text
6437uid 48,0
6438va (VaSet
6439isHidden 1
6440font "Arial,8,1"
6441)
6442xt "20000,4000,30100,5000"
6443st "Post-module directives:"
6444blo "20000,4800"
6445)
6446*211 (MLText
6447uid 49,0
6448va (VaSet
6449isHidden 1
6450)
6451xt "20000,0,20000,0"
6452tm "BdCompilerDirectivesTextMgr"
6453)
6454*212 (Text
6455uid 50,0
6456va (VaSet
6457isHidden 1
6458font "Arial,8,1"
6459)
6460xt "20000,5000,29900,6000"
6461st "End-module directives:"
6462blo "20000,5800"
6463)
6464*213 (MLText
6465uid 51,0
6466va (VaSet
6467isHidden 1
6468)
6469xt "20000,6000,20000,6000"
6470tm "BdCompilerDirectivesTextMgr"
6471)
6472]
6473associable 1
6474)
6475windowSize "0,0,1681,1030"
6476viewArea "60000,4200,152106,61908"
6477cachedDiagramExtent "-92000,0,146000,98000"
6478pageSetupInfo (PageSetupInfo
6479ptrCmd ""
6480toPrinter 1
6481exportedDirectories [
6482"$HDS_PROJECT_DIR/HTMLExport"
6483]
6484exportStdIncludeRefs 1
6485exportStdPackageRefs 1
6486)
6487hasePageBreakOrigin 1
6488pageBreakOrigin "-146000,0"
6489lastUid 2551,0
6490defaultCommentText (CommentText
6491shape (Rectangle
6492layer 0
6493va (VaSet
6494vasetType 1
6495fg "65280,65280,46080"
6496lineColor "0,0,32768"
6497)
6498xt "0,0,15000,5000"
6499)
6500text (MLText
6501va (VaSet
6502fg "0,0,32768"
6503)
6504xt "200,200,2400,1200"
6505st "
6506Text
6507"
6508tm "CommentText"
6509wrapOption 3
6510visibleHeight 4600
6511visibleWidth 14600
6512)
6513)
6514defaultPanel (Panel
6515shape (RectFrame
6516va (VaSet
6517vasetType 1
6518fg "65535,65535,65535"
6519lineColor "32768,0,0"
6520lineWidth 2
6521)
6522xt "0,0,20000,20000"
6523)
6524title (TextAssociate
6525ps "TopLeftStrategy"
6526text (Text
6527va (VaSet
6528font "Arial,8,1"
6529)
6530xt "1000,1000,3800,2000"
6531st "Panel0"
6532blo "1000,1800"
6533tm "PanelText"
6534)
6535)
6536)
6537defaultBlk (Blk
6538shape (Rectangle
6539va (VaSet
6540vasetType 1
6541fg "39936,56832,65280"
6542lineColor "0,0,32768"
6543lineWidth 2
6544)
6545xt "0,0,8000,10000"
6546)
6547ttg (MlTextGroup
6548ps "CenterOffsetStrategy"
6549stg "VerticalLayoutStrategy"
6550textVec [
6551*214 (Text
6552va (VaSet
6553font "Arial,8,1"
6554)
6555xt "2200,3500,5800,4500"
6556st "<library>"
6557blo "2200,4300"
6558tm "BdLibraryNameMgr"
6559)
6560*215 (Text
6561va (VaSet
6562font "Arial,8,1"
6563)
6564xt "2200,4500,5600,5500"
6565st "<block>"
6566blo "2200,5300"
6567tm "BlkNameMgr"
6568)
6569*216 (Text
6570va (VaSet
6571font "Arial,8,1"
6572)
6573xt "2200,5500,3200,6500"
6574st "I0"
6575blo "2200,6300"
6576tm "InstanceNameMgr"
6577)
6578]
6579)
6580ga (GenericAssociation
6581ps "EdgeToEdgeStrategy"
6582matrix (Matrix
6583text (MLText
6584va (VaSet
6585font "Courier New,8,0"
6586)
6587xt "2200,13500,2200,13500"
6588)
6589header ""
6590)
6591elements [
6592]
6593)
6594viewicon (ZoomableIcon
6595sl 0
6596va (VaSet
6597vasetType 1
6598fg "49152,49152,49152"
6599)
6600xt "0,0,1500,1500"
6601iconName "UnknownFile.png"
6602iconMaskName "UnknownFile.msk"
6603)
6604viewiconposition 0
6605)
6606defaultMWComponent (MWC
6607shape (Rectangle
6608va (VaSet
6609vasetType 1
6610fg "0,65535,0"
6611lineColor "0,32896,0"
6612lineWidth 2
6613)
6614xt "0,0,8000,10000"
6615)
6616ttg (MlTextGroup
6617ps "CenterOffsetStrategy"
6618stg "VerticalLayoutStrategy"
6619textVec [
6620*217 (Text
6621va (VaSet
6622font "Arial,8,1"
6623)
6624xt "550,3500,3450,4500"
6625st "Library"
6626blo "550,4300"
6627)
6628*218 (Text
6629va (VaSet
6630font "Arial,8,1"
6631)
6632xt "550,4500,7450,5500"
6633st "MWComponent"
6634blo "550,5300"
6635)
6636*219 (Text
6637va (VaSet
6638font "Arial,8,1"
6639)
6640xt "550,5500,1550,6500"
6641st "I0"
6642blo "550,6300"
6643tm "InstanceNameMgr"
6644)
6645]
6646)
6647ga (GenericAssociation
6648ps "EdgeToEdgeStrategy"
6649matrix (Matrix
6650text (MLText
6651va (VaSet
6652font "Courier New,8,0"
6653)
6654xt "-6450,1500,-6450,1500"
6655)
6656header ""
6657)
6658elements [
6659]
6660)
6661portVis (PortSigDisplay
6662)
6663prms (Property
6664pclass "params"
6665pname "params"
6666ptn "String"
6667)
6668visOptions (mwParamsVisibilityOptions
6669)
6670)
6671defaultSaComponent (SaComponent
6672shape (Rectangle
6673va (VaSet
6674vasetType 1
6675fg "0,65535,0"
6676lineColor "0,32896,0"
6677lineWidth 2
6678)
6679xt "0,0,8000,10000"
6680)
6681ttg (MlTextGroup
6682ps "CenterOffsetStrategy"
6683stg "VerticalLayoutStrategy"
6684textVec [
6685*220 (Text
6686va (VaSet
6687font "Arial,8,1"
6688)
6689xt "900,3500,3800,4500"
6690st "Library"
6691blo "900,4300"
6692tm "BdLibraryNameMgr"
6693)
6694*221 (Text
6695va (VaSet
6696font "Arial,8,1"
6697)
6698xt "900,4500,7100,5500"
6699st "SaComponent"
6700blo "900,5300"
6701tm "CptNameMgr"
6702)
6703*222 (Text
6704va (VaSet
6705font "Arial,8,1"
6706)
6707xt "900,5500,1900,6500"
6708st "I0"
6709blo "900,6300"
6710tm "InstanceNameMgr"
6711)
6712]
6713)
6714ga (GenericAssociation
6715ps "EdgeToEdgeStrategy"
6716matrix (Matrix
6717text (MLText
6718va (VaSet
6719font "Courier New,8,0"
6720)
6721xt "-6100,1500,-6100,1500"
6722)
6723header ""
6724)
6725elements [
6726]
6727)
6728viewicon (ZoomableIcon
6729sl 0
6730va (VaSet
6731vasetType 1
6732fg "49152,49152,49152"
6733)
6734xt "0,0,1500,1500"
6735iconName "UnknownFile.png"
6736iconMaskName "UnknownFile.msk"
6737)
6738viewiconposition 0
6739portVis (PortSigDisplay
6740)
6741archFileType "UNKNOWN"
6742)
6743defaultVhdlComponent (VhdlComponent
6744shape (Rectangle
6745va (VaSet
6746vasetType 1
6747fg "0,65535,0"
6748lineColor "0,32896,0"
6749lineWidth 2
6750)
6751xt "0,0,8000,10000"
6752)
6753ttg (MlTextGroup
6754ps "CenterOffsetStrategy"
6755stg "VerticalLayoutStrategy"
6756textVec [
6757*223 (Text
6758va (VaSet
6759font "Arial,8,1"
6760)
6761xt "500,3500,3400,4500"
6762st "Library"
6763blo "500,4300"
6764)
6765*224 (Text
6766va (VaSet
6767font "Arial,8,1"
6768)
6769xt "500,4500,7500,5500"
6770st "VhdlComponent"
6771blo "500,5300"
6772)
6773*225 (Text
6774va (VaSet
6775font "Arial,8,1"
6776)
6777xt "500,5500,1500,6500"
6778st "I0"
6779blo "500,6300"
6780tm "InstanceNameMgr"
6781)
6782]
6783)
6784ga (GenericAssociation
6785ps "EdgeToEdgeStrategy"
6786matrix (Matrix
6787text (MLText
6788va (VaSet
6789font "Courier New,8,0"
6790)
6791xt "-6500,1500,-6500,1500"
6792)
6793header ""
6794)
6795elements [
6796]
6797)
6798portVis (PortSigDisplay
6799)
6800entityPath ""
6801archName ""
6802archPath ""
6803)
6804defaultVerilogComponent (VerilogComponent
6805shape (Rectangle
6806va (VaSet
6807vasetType 1
6808fg "0,65535,0"
6809lineColor "0,32896,0"
6810lineWidth 2
6811)
6812xt "-450,0,8450,10000"
6813)
6814ttg (MlTextGroup
6815ps "CenterOffsetStrategy"
6816stg "VerticalLayoutStrategy"
6817textVec [
6818*226 (Text
6819va (VaSet
6820font "Arial,8,1"
6821)
6822xt "50,3500,2950,4500"
6823st "Library"
6824blo "50,4300"
6825)
6826*227 (Text
6827va (VaSet
6828font "Arial,8,1"
6829)
6830xt "50,4500,7950,5500"
6831st "VerilogComponent"
6832blo "50,5300"
6833)
6834*228 (Text
6835va (VaSet
6836font "Arial,8,1"
6837)
6838xt "50,5500,1050,6500"
6839st "I0"
6840blo "50,6300"
6841tm "InstanceNameMgr"
6842)
6843]
6844)
6845ga (GenericAssociation
6846ps "EdgeToEdgeStrategy"
6847matrix (Matrix
6848text (MLText
6849va (VaSet
6850font "Courier New,8,0"
6851)
6852xt "-6950,1500,-6950,1500"
6853)
6854header ""
6855)
6856elements [
6857]
6858)
6859entityPath ""
6860)
6861defaultHdlText (HdlText
6862shape (Rectangle
6863va (VaSet
6864vasetType 1
6865fg "65535,65535,37120"
6866lineColor "0,0,32768"
6867lineWidth 2
6868)
6869xt "0,0,8000,10000"
6870)
6871ttg (MlTextGroup
6872ps "CenterOffsetStrategy"
6873stg "VerticalLayoutStrategy"
6874textVec [
6875*229 (Text
6876va (VaSet
6877font "Arial,8,1"
6878)
6879xt "3150,4000,4850,5000"
6880st "eb1"
6881blo "3150,4800"
6882tm "HdlTextNameMgr"
6883)
6884*230 (Text
6885va (VaSet
6886font "Arial,8,1"
6887)
6888xt "3150,5000,3950,6000"
6889st "1"
6890blo "3150,5800"
6891tm "HdlTextNumberMgr"
6892)
6893]
6894)
6895viewicon (ZoomableIcon
6896sl 0
6897va (VaSet
6898vasetType 1
6899fg "49152,49152,49152"
6900)
6901xt "0,0,1500,1500"
6902iconName "UnknownFile.png"
6903iconMaskName "UnknownFile.msk"
6904)
6905viewiconposition 0
6906)
6907defaultEmbeddedText (EmbeddedText
6908commentText (CommentText
6909ps "CenterOffsetStrategy"
6910shape (Rectangle
6911va (VaSet
6912vasetType 1
6913fg "65535,65535,65535"
6914lineColor "0,0,32768"
6915lineWidth 2
6916)
6917xt "0,0,18000,5000"
6918)
6919text (MLText
6920va (VaSet
6921)
6922xt "200,200,2400,1200"
6923st "
6924Text
6925"
6926tm "HdlTextMgr"
6927wrapOption 3
6928visibleHeight 4600
6929visibleWidth 17600
6930)
6931)
6932)
6933defaultGlobalConnector (GlobalConnector
6934shape (Circle
6935va (VaSet
6936vasetType 1
6937fg "65535,65535,0"
6938)
6939xt "-1000,-1000,1000,1000"
6940radius 1000
6941)
6942name (Text
6943va (VaSet
6944font "Arial,8,1"
6945)
6946xt "-500,-500,500,500"
6947st "G"
6948blo "-500,300"
6949)
6950)
6951defaultRipper (Ripper
6952ps "OnConnectorStrategy"
6953shape (Line2D
6954pts [
6955"0,0"
6956"1000,1000"
6957]
6958va (VaSet
6959vasetType 1
6960)
6961xt "0,0,1000,1000"
6962)
6963)
6964defaultBdJunction (BdJunction
6965ps "OnConnectorStrategy"
6966shape (Circle
6967va (VaSet
6968vasetType 1
6969)
6970xt "-400,-400,400,400"
6971radius 400
6972)
6973)
6974defaultPortIoIn (PortIoIn
6975shape (CompositeShape
6976va (VaSet
6977vasetType 1
6978fg "0,0,32768"
6979)
6980optionalChildren [
6981(Pentagon
6982sl 0
6983ro 270
6984xt "-2000,-375,-500,375"
6985)
6986(Line
6987sl 0
6988ro 270
6989xt "-500,0,0,0"
6990pts [
6991"-500,0"
6992"0,0"
6993]
6994)
6995]
6996)
6997stc 0
6998sf 1
6999tg (WTG
7000ps "PortIoTextPlaceStrategy"
7001stg "STSignalDisplayStrategy"
7002f (Text
7003va (VaSet
7004)
7005xt "-1375,-1000,-1375,-1000"
7006ju 2
7007blo "-1375,-1000"
7008tm "WireNameMgr"
7009)
7010)
7011)
7012defaultPortIoOut (PortIoOut
7013shape (CompositeShape
7014va (VaSet
7015vasetType 1
7016fg "0,0,32768"
7017)
7018optionalChildren [
7019(Pentagon
7020sl 0
7021ro 270
7022xt "500,-375,2000,375"
7023)
7024(Line
7025sl 0
7026ro 270
7027xt "0,0,500,0"
7028pts [
7029"0,0"
7030"500,0"
7031]
7032)
7033]
7034)
7035stc 0
7036sf 1
7037tg (WTG
7038ps "PortIoTextPlaceStrategy"
7039stg "STSignalDisplayStrategy"
7040f (Text
7041va (VaSet
7042)
7043xt "625,-1000,625,-1000"
7044blo "625,-1000"
7045tm "WireNameMgr"
7046)
7047)
7048)
7049defaultPortIoInOut (PortIoInOut
7050shape (CompositeShape
7051va (VaSet
7052vasetType 1
7053fg "0,0,32768"
7054)
7055optionalChildren [
7056(Hexagon
7057sl 0
7058xt "500,-375,2000,375"
7059)
7060(Line
7061sl 0
7062xt "0,0,500,0"
7063pts [
7064"0,0"
7065"500,0"
7066]
7067)
7068]
7069)
7070stc 0
7071sf 1
7072tg (WTG
7073ps "PortIoTextPlaceStrategy"
7074stg "STSignalDisplayStrategy"
7075f (Text
7076va (VaSet
7077)
7078xt "0,-375,0,-375"
7079blo "0,-375"
7080tm "WireNameMgr"
7081)
7082)
7083)
7084defaultPortIoBuffer (PortIoBuffer
7085shape (CompositeShape
7086va (VaSet
7087vasetType 1
7088fg "65535,65535,65535"
7089lineColor "0,0,32768"
7090)
7091optionalChildren [
7092(Hexagon
7093sl 0
7094xt "500,-375,2000,375"
7095)
7096(Line
7097sl 0
7098xt "0,0,500,0"
7099pts [
7100"0,0"
7101"500,0"
7102]
7103)
7104]
7105)
7106stc 0
7107sf 1
7108tg (WTG
7109ps "PortIoTextPlaceStrategy"
7110stg "STSignalDisplayStrategy"
7111f (Text
7112va (VaSet
7113)
7114xt "0,-375,0,-375"
7115blo "0,-375"
7116tm "WireNameMgr"
7117)
7118)
7119)
7120defaultSignal (Wire
7121shape (OrthoPolyLine
7122va (VaSet
7123vasetType 3
7124)
7125pts [
7126"0,0"
7127"0,0"
7128]
7129)
7130ss 0
7131es 0
7132sat 32
7133eat 32
7134st 0
7135sf 1
7136si 0
7137tg (WTG
7138ps "ConnStartEndStrategy"
7139stg "STSignalDisplayStrategy"
7140f (Text
7141va (VaSet
7142)
7143xt "0,0,1900,1000"
7144st "sig0"
7145blo "0,800"
7146tm "WireNameMgr"
7147)
7148)
7149)
7150defaultBus (Wire
7151shape (OrthoPolyLine
7152va (VaSet
7153vasetType 3
7154lineWidth 2
7155)
7156pts [
7157"0,0"
7158"0,0"
7159]
7160)
7161ss 0
7162es 0
7163sat 32
7164eat 32
7165sty 1
7166st 0
7167sf 1
7168si 0
7169tg (WTG
7170ps "ConnStartEndStrategy"
7171stg "STSignalDisplayStrategy"
7172f (Text
7173va (VaSet
7174)
7175xt "0,0,2400,1000"
7176st "dbus0"
7177blo "0,800"
7178tm "WireNameMgr"
7179)
7180)
7181)
7182defaultBundle (Bundle
7183shape (OrthoPolyLine
7184va (VaSet
7185vasetType 3
7186lineColor "32768,0,0"
7187lineWidth 2
7188)
7189pts [
7190"0,0"
7191"0,0"
7192]
7193)
7194ss 0
7195es 0
7196sat 32
7197eat 32
7198textGroup (BiTextGroup
7199ps "ConnStartEndStrategy"
7200stg "VerticalLayoutStrategy"
7201first (Text
7202va (VaSet
7203)
7204xt "0,0,3000,1000"
7205st "bundle0"
7206blo "0,800"
7207tm "BundleNameMgr"
7208)
7209second (MLText
7210va (VaSet
7211)
7212xt "0,1000,1000,2000"
7213st "()"
7214tm "BundleContentsMgr"
7215)
7216)
7217bundleNet &0
7218)
7219defaultPortMapFrame (PortMapFrame
7220ps "PortMapFrameStrategy"
7221shape (RectFrame
7222va (VaSet
7223vasetType 1
7224fg "65535,65535,65535"
7225lineColor "0,0,32768"
7226lineWidth 2
7227)
7228xt "0,0,10000,12000"
7229)
7230portMapText (BiTextGroup
7231ps "BottomRightOffsetStrategy"
7232stg "VerticalLayoutStrategy"
7233first (MLText
7234va (VaSet
7235)
7236)
7237second (MLText
7238va (VaSet
7239)
7240tm "PortMapTextMgr"
7241)
7242)
7243)
7244defaultGenFrame (Frame
7245shape (RectFrame
7246va (VaSet
7247vasetType 1
7248fg "65535,65535,65535"
7249lineColor "26368,26368,26368"
7250lineStyle 2
7251lineWidth 2
7252)
7253xt "0,0,20000,20000"
7254)
7255title (TextAssociate
7256ps "TopLeftStrategy"
7257text (MLText
7258va (VaSet
7259)
7260xt "0,-1100,12900,-100"
7261st "g0: FOR i IN 0 TO n GENERATE"
7262tm "FrameTitleTextMgr"
7263)
7264)
7265seqNum (FrameSequenceNumber
7266ps "TopLeftStrategy"
7267shape (Rectangle
7268va (VaSet
7269vasetType 1
7270fg "65535,65535,65535"
7271)
7272xt "50,50,1250,1450"
7273)
7274num (Text
7275va (VaSet
7276)
7277xt "250,250,1050,1250"
7278st "1"
7279blo "250,1050"
7280tm "FrameSeqNumMgr"
7281)
7282)
7283decls (MlTextGroup
7284ps "BottomRightOffsetStrategy"
7285stg "VerticalLayoutStrategy"
7286textVec [
7287*231 (Text
7288va (VaSet
7289font "Arial,8,1"
7290)
7291xt "14100,20000,22000,21000"
7292st "Frame Declarations"
7293blo "14100,20800"
7294)
7295*232 (MLText
7296va (VaSet
7297)
7298xt "14100,21000,14100,21000"
7299tm "BdFrameDeclTextMgr"
7300)
7301]
7302)
7303)
7304defaultBlockFrame (Frame
7305shape (RectFrame
7306va (VaSet
7307vasetType 1
7308fg "65535,65535,65535"
7309lineColor "26368,26368,26368"
7310lineStyle 1
7311lineWidth 2
7312)
7313xt "0,0,20000,20000"
7314)
7315title (TextAssociate
7316ps "TopLeftStrategy"
7317text (MLText
7318va (VaSet
7319)
7320xt "0,-1100,7700,-100"
7321st "b0: BLOCK (guard)"
7322tm "FrameTitleTextMgr"
7323)
7324)
7325seqNum (FrameSequenceNumber
7326ps "TopLeftStrategy"
7327shape (Rectangle
7328va (VaSet
7329vasetType 1
7330fg "65535,65535,65535"
7331)
7332xt "50,50,1250,1450"
7333)
7334num (Text
7335va (VaSet
7336)
7337xt "250,250,1050,1250"
7338st "1"
7339blo "250,1050"
7340tm "FrameSeqNumMgr"
7341)
7342)
7343decls (MlTextGroup
7344ps "BottomRightOffsetStrategy"
7345stg "VerticalLayoutStrategy"
7346textVec [
7347*233 (Text
7348va (VaSet
7349font "Arial,8,1"
7350)
7351xt "14100,20000,22000,21000"
7352st "Frame Declarations"
7353blo "14100,20800"
7354)
7355*234 (MLText
7356va (VaSet
7357)
7358xt "14100,21000,14100,21000"
7359tm "BdFrameDeclTextMgr"
7360)
7361]
7362)
7363style 3
7364)
7365defaultSaCptPort (CptPort
7366ps "OnEdgeStrategy"
7367shape (Triangle
7368ro 90
7369va (VaSet
7370vasetType 1
7371fg "0,65535,0"
7372)
7373xt "0,0,750,750"
7374)
7375tg (CPTG
7376ps "CptPortTextPlaceStrategy"
7377stg "VerticalLayoutStrategy"
7378f (Text
7379va (VaSet
7380)
7381xt "0,750,1800,1750"
7382st "Port"
7383blo "0,1550"
7384)
7385)
7386thePort (LogicalPort
7387decl (Decl
7388n "Port"
7389t ""
7390o 0
7391)
7392)
7393)
7394defaultSaCptPortBuffer (CptPort
7395ps "OnEdgeStrategy"
7396shape (Diamond
7397va (VaSet
7398vasetType 1
7399fg "65535,65535,65535"
7400)
7401xt "0,0,750,750"
7402)
7403tg (CPTG
7404ps "CptPortTextPlaceStrategy"
7405stg "VerticalLayoutStrategy"
7406f (Text
7407va (VaSet
7408)
7409xt "0,750,1800,1750"
7410st "Port"
7411blo "0,1550"
7412)
7413)
7414thePort (LogicalPort
7415m 3
7416decl (Decl
7417n "Port"
7418t ""
7419o 0
7420)
7421)
7422)
7423defaultDeclText (MLText
7424va (VaSet
7425font "Courier New,8,0"
7426)
7427)
7428archDeclarativeBlock (BdArchDeclBlock
7429uid 1,0
7430stg "BdArchDeclBlockLS"
7431declLabel (Text
7432uid 2,0
7433va (VaSet
7434font "Arial,8,1"
7435)
7436xt "-92000,21600,-86600,22600"
7437st "Declarations"
7438blo "-92000,22400"
7439)
7440portLabel (Text
7441uid 3,0
7442va (VaSet
7443font "Arial,8,1"
7444)
7445xt "-92000,22600,-89300,23600"
7446st "Ports:"
7447blo "-92000,23400"
7448)
7449preUserLabel (Text
7450uid 4,0
7451va (VaSet
7452isHidden 1
7453font "Arial,8,1"
7454)
7455xt "-92000,21600,-88200,22600"
7456st "Pre User:"
7457blo "-92000,22400"
7458)
7459preUserText (MLText
7460uid 5,0
7461va (VaSet
7462isHidden 1
7463font "Courier New,8,0"
7464)
7465xt "-92000,21600,-92000,21600"
7466tm "BdDeclarativeTextMgr"
7467)
7468diagSignalLabel (Text
7469uid 6,0
7470va (VaSet
7471font "Arial,8,1"
7472)
7473xt "-92000,23600,-84900,24600"
7474st "Diagram Signals:"
7475blo "-92000,24400"
7476)
7477postUserLabel (Text
7478uid 7,0
7479va (VaSet
7480isHidden 1
7481font "Arial,8,1"
7482)
7483xt "-92000,21600,-87300,22600"
7484st "Post User:"
7485blo "-92000,22400"
7486)
7487postUserText (MLText
7488uid 8,0
7489va (VaSet
7490isHidden 1
7491font "Courier New,8,0"
7492)
7493xt "-92000,21600,-92000,21600"
7494tm "BdDeclarativeTextMgr"
7495)
7496)
7497commonDM (CommonDM
7498ldm (LogicalDM
7499suid 51,0
7500usingSuid 1
7501emptyRow *235 (LEmptyRow
7502)
7503uid 54,0
7504optionalChildren [
7505*236 (RefLabelRowHdr
7506)
7507*237 (TitleRowHdr
7508)
7509*238 (FilterRowHdr
7510)
7511*239 (RefLabelColHdr
7512tm "RefLabelColHdrMgr"
7513)
7514*240 (RowExpandColHdr
7515tm "RowExpandColHdrMgr"
7516)
7517*241 (GroupColHdr
7518tm "GroupColHdrMgr"
7519)
7520*242 (NameColHdr
7521tm "BlockDiagramNameColHdrMgr"
7522)
7523*243 (ModeColHdr
7524tm "BlockDiagramModeColHdrMgr"
7525)
7526*244 (TypeColHdr
7527tm "BlockDiagramTypeColHdrMgr"
7528)
7529*245 (BoundsColHdr
7530tm "BlockDiagramBoundsColHdrMgr"
7531)
7532*246 (InitColHdr
7533tm "BlockDiagramInitColHdrMgr"
7534)
7535*247 (EolColHdr
7536tm "BlockDiagramEolColHdrMgr"
7537)
7538*248 (LeafLogPort
7539port (LogicalPort
7540m 4
7541decl (Decl
7542n "clk"
7543t "STD_LOGIC"
7544preAdd 0
7545posAdd 0
7546o 1
7547suid 1,0
7548)
7549)
7550uid 340,0
7551)
7552*249 (LeafLogPort
7553port (LogicalPort
7554m 4
7555decl (Decl
7556n "wiz_addr"
7557t "std_logic_vector"
7558b "(9 DOWNTO 0)"
7559o 2
7560suid 2,0
7561)
7562)
7563uid 342,0
7564)
7565*250 (LeafLogPort
7566port (LogicalPort
7567m 4
7568decl (Decl
7569n "wiz_data"
7570t "std_logic_vector"
7571b "(15 DOWNTO 0)"
7572o 3
7573suid 3,0
7574)
7575)
7576uid 344,0
7577)
7578*251 (LeafLogPort
7579port (LogicalPort
7580m 4
7581decl (Decl
7582n "wiz_rd"
7583t "std_logic"
7584o 4
7585suid 4,0
7586i "'1'"
7587)
7588)
7589uid 346,0
7590)
7591*252 (LeafLogPort
7592port (LogicalPort
7593m 4
7594decl (Decl
7595n "wiz_wr"
7596t "std_logic"
7597o 5
7598suid 5,0
7599i "'1'"
7600)
7601)
7602uid 348,0
7603)
7604*253 (LeafLogPort
7605port (LogicalPort
7606m 4
7607decl (Decl
7608n "sensor_cs"
7609t "std_logic_vector"
7610b "(3 DOWNTO 0)"
7611o 6
7612suid 6,0
7613)
7614)
7615uid 404,0
7616)
7617*254 (LeafLogPort
7618port (LogicalPort
7619m 4
7620decl (Decl
7621n "sclk"
7622t "std_logic"
7623o 7
7624suid 7,0
7625)
7626)
7627uid 406,0
7628)
7629*255 (LeafLogPort
7630port (LogicalPort
7631m 4
7632decl (Decl
7633n "sio"
7634t "std_logic"
7635preAdd 0
7636posAdd 0
7637o 8
7638suid 8,0
7639)
7640)
7641uid 408,0
7642)
7643*256 (LeafLogPort
7644port (LogicalPort
7645m 4
7646decl (Decl
7647n "trigger"
7648t "std_logic"
7649preAdd 0
7650posAdd 0
7651o 9
7652suid 9,0
7653)
7654)
7655uid 456,0
7656)
7657*257 (LeafLogPort
7658port (LogicalPort
7659m 4
7660decl (Decl
7661n "board_id"
7662t "std_logic_vector"
7663b "(3 downto 0)"
7664preAdd 0
7665posAdd 0
7666o 10
7667suid 10,0
7668)
7669)
7670uid 458,0
7671)
7672*258 (LeafLogPort
7673port (LogicalPort
7674m 4
7675decl (Decl
7676n "crate_id"
7677t "std_logic_vector"
7678b "(1 downto 0)"
7679o 11
7680suid 11,0
7681)
7682)
7683uid 460,0
7684)
7685*259 (LeafLogPort
7686port (LogicalPort
7687m 4
7688decl (Decl
7689n "adc_otr_array"
7690t "std_logic_vector"
7691b "(3 DOWNTO 0)"
7692o 12
7693suid 12,0
7694)
7695)
7696uid 584,0
7697)
7698*260 (LeafLogPort
7699port (LogicalPort
7700m 4
7701decl (Decl
7702n "adc_data_array"
7703t "adc_data_array_type"
7704o 13
7705suid 13,0
7706)
7707)
7708uid 586,0
7709)
7710*261 (LeafLogPort
7711port (LogicalPort
7712m 4
7713decl (Decl
7714n "adc_oeb"
7715t "std_logic"
7716preAdd 0
7717posAdd 0
7718o 14
7719suid 14,0
7720)
7721)
7722uid 588,0
7723)
7724*262 (LeafLogPort
7725port (LogicalPort
7726m 4
7727decl (Decl
7728n "adc_otr"
7729t "STD_LOGIC"
7730preAdd 0
7731posAdd 0
7732o 16
7733suid 16,0
7734)
7735)
7736uid 590,0
7737)
7738*263 (LeafLogPort
7739port (LogicalPort
7740m 4
7741decl (Decl
7742n "adc_data"
7743t "std_logic_vector"
7744b "(11 DOWNTO 0)"
7745preAdd 0
7746posAdd 0
7747o 17
7748suid 17,0
7749)
7750)
7751uid 592,0
7752)
7753*264 (LeafLogPort
7754port (LogicalPort
7755m 4
7756decl (Decl
7757n "wiz_reset"
7758t "std_logic"
7759o 21
7760suid 23,0
7761i "'1'"
7762)
7763)
7764uid 903,0
7765)
7766*265 (LeafLogPort
7767port (LogicalPort
7768m 4
7769decl (Decl
7770n "led"
7771t "std_logic_vector"
7772b "(7 DOWNTO 0)"
7773posAdd 0
7774o 22
7775suid 24,0
7776i "(OTHERS => '0')"
7777)
7778)
7779uid 905,0
7780)
7781*266 (LeafLogPort
7782port (LogicalPort
7783m 4
7784decl (Decl
7785n "wiz_cs"
7786t "std_logic"
7787o 23
7788suid 25,0
7789i "'1'"
7790)
7791)
7792uid 907,0
7793)
7794*267 (LeafLogPort
7795port (LogicalPort
7796m 4
7797decl (Decl
7798n "wiz_int"
7799t "std_logic"
7800o 24
7801suid 26,0
7802)
7803)
7804uid 909,0
7805)
7806*268 (LeafLogPort
7807port (LogicalPort
7808m 4
7809decl (Decl
7810n "dac_cs"
7811t "std_logic"
7812o 25
7813suid 27,0
7814)
7815)
7816uid 911,0
7817)
7818*269 (LeafLogPort
7819port (LogicalPort
7820m 4
7821decl (Decl
7822n "mosi"
7823t "std_logic"
7824o 26
7825suid 28,0
7826i "'0'"
7827)
7828)
7829uid 913,0
7830)
7831*270 (LeafLogPort
7832port (LogicalPort
7833m 4
7834decl (Decl
7835n "denable"
7836t "std_logic"
7837eolc "-- default domino wave off"
7838posAdd 0
7839o 27
7840suid 29,0
7841i "'0'"
7842)
7843)
7844uid 915,0
7845)
7846*271 (LeafLogPort
7847port (LogicalPort
7848m 4
7849decl (Decl
7850n "CLK_25_PS"
7851t "std_logic"
7852o 28
7853suid 30,0
7854)
7855)
7856uid 917,0
7857)
7858*272 (LeafLogPort
7859port (LogicalPort
7860m 4
7861decl (Decl
7862n "CLK_50"
7863t "std_logic"
7864o 29
7865suid 31,0
7866)
7867)
7868uid 919,0
7869)
7870*273 (LeafLogPort
7871port (LogicalPort
7872m 4
7873decl (Decl
7874n "drs_channel_id"
7875t "std_logic_vector"
7876b "(3 downto 0)"
7877o 30
7878suid 32,0
7879i "(others => '0')"
7880)
7881)
7882uid 921,0
7883)
7884*274 (LeafLogPort
7885port (LogicalPort
7886m 4
7887decl (Decl
7888n "drs_dwrite"
7889t "std_logic"
7890o 31
7891suid 33,0
7892i "'1'"
7893)
7894)
7895uid 923,0
7896)
7897*275 (LeafLogPort
7898port (LogicalPort
7899m 4
7900decl (Decl
7901n "RSRLOAD"
7902t "std_logic"
7903o 32
7904suid 34,0
7905i "'0'"
7906)
7907)
7908uid 925,0
7909)
7910*276 (LeafLogPort
7911port (LogicalPort
7912m 4
7913decl (Decl
7914n "SRCLK"
7915t "std_logic"
7916o 33
7917suid 35,0
7918i "'0'"
7919)
7920)
7921uid 927,0
7922)
7923*277 (LeafLogPort
7924port (LogicalPort
7925m 4
7926decl (Decl
7927n "SROUT_in_0"
7928t "std_logic"
7929o 30
7930suid 36,0
7931)
7932)
7933uid 929,0
7934)
7935*278 (LeafLogPort
7936port (LogicalPort
7937m 4
7938decl (Decl
7939n "SROUT_in_1"
7940t "std_logic"
7941o 31
7942suid 37,0
7943)
7944)
7945uid 931,0
7946)
7947*279 (LeafLogPort
7948port (LogicalPort
7949m 4
7950decl (Decl
7951n "SROUT_in_2"
7952t "std_logic"
7953o 32
7954suid 38,0
7955)
7956)
7957uid 933,0
7958)
7959*280 (LeafLogPort
7960port (LogicalPort
7961m 4
7962decl (Decl
7963n "SROUT_in_3"
7964t "std_logic"
7965o 33
7966suid 39,0
7967)
7968)
7969uid 935,0
7970)
7971*281 (LeafLogPort
7972port (LogicalPort
7973m 4
7974decl (Decl
7975n "SRIN_out"
7976t "std_logic"
7977o 34
7978suid 40,0
7979i "'0'"
7980)
7981)
7982uid 1541,0
7983)
7984*282 (LeafLogPort
7985port (LogicalPort
7986m 4
7987decl (Decl
7988n "amber"
7989t "std_logic"
7990o 35
7991suid 41,0
7992)
7993)
7994uid 1543,0
7995)
7996*283 (LeafLogPort
7997port (LogicalPort
7998m 4
7999decl (Decl
8000n "red"
8001t "std_logic"
8002o 36
8003suid 42,0
8004)
8005)
8006uid 1545,0
8007)
8008*284 (LeafLogPort
8009port (LogicalPort
8010m 4
8011decl (Decl
8012n "green"
8013t "std_logic"
8014o 37
8015suid 43,0
8016)
8017)
8018uid 1547,0
8019)
8020*285 (LeafLogPort
8021port (LogicalPort
8022m 4
8023decl (Decl
8024n "counter_result"
8025t "std_logic_vector"
8026b "(11 DOWNTO 0)"
8027o 38
8028suid 44,0
8029)
8030)
8031uid 1549,0
8032)
8033*286 (LeafLogPort
8034port (LogicalPort
8035m 4
8036decl (Decl
8037n "alarm_refclk_too_low"
8038t "std_logic"
8039posAdd 0
8040o 39
8041suid 45,0
8042)
8043)
8044uid 1551,0
8045)
8046*287 (LeafLogPort
8047port (LogicalPort
8048m 4
8049decl (Decl
8050n "alarm_refclk_too_high"
8051t "std_logic"
8052o 40
8053suid 46,0
8054)
8055)
8056uid 1553,0
8057)
8058*288 (LeafLogPort
8059port (LogicalPort
8060m 4
8061decl (Decl
8062n "D_T_in"
8063t "std_logic_vector"
8064b "(1 DOWNTO 0)"
8065o 41
8066suid 47,0
8067)
8068)
8069uid 1555,0
8070)
8071*289 (LeafLogPort
8072port (LogicalPort
8073m 4
8074decl (Decl
8075n "plllock_in"
8076t "std_logic_vector"
8077b "(3 DOWNTO 0)"
8078eolc "-- high level, if dominowave is running and DRS PLL locked"
8079o 43
8080suid 49,0
8081)
8082)
8083uid 1575,0
8084)
8085*290 (LeafLogPort
8086port (LogicalPort
8087lang 2
8088m 4
8089decl (Decl
8090n "ADC_CLK"
8091t "std_logic"
8092o 44
8093suid 50,0
8094)
8095)
8096uid 1690,0
8097)
8098*291 (LeafLogPort
8099port (LogicalPort
8100m 4
8101decl (Decl
8102n "REF_CLK"
8103t "STD_LOGIC"
8104o 42
8105suid 51,0
8106i "'0'"
8107)
8108)
8109uid 2003,0
8110)
8111]
8112)
8113pdm (PhysicalDM
8114displayShortBounds 1
8115editShortBounds 1
8116uid 67,0
8117optionalChildren [
8118*292 (Sheet
8119sheetRow (SheetRow
8120headerVa (MVa
8121cellColor "49152,49152,49152"
8122fontColor "0,0,0"
8123font "Tahoma,10,0"
8124)
8125cellVa (MVa
8126cellColor "65535,65535,65535"
8127fontColor "0,0,0"
8128font "Tahoma,10,0"
8129)
8130groupVa (MVa
8131cellColor "39936,56832,65280"
8132fontColor "0,0,0"
8133font "Tahoma,10,0"
8134)
8135emptyMRCItem *293 (MRCItem
8136litem &235
8137pos 44
8138dimension 20
8139)
8140uid 69,0
8141optionalChildren [
8142*294 (MRCItem
8143litem &236
8144pos 0
8145dimension 20
8146uid 70,0
8147)
8148*295 (MRCItem
8149litem &237
8150pos 1
8151dimension 23
8152uid 71,0
8153)
8154*296 (MRCItem
8155litem &238
8156pos 2
8157hidden 1
8158dimension 20
8159uid 72,0
8160)
8161*297 (MRCItem
8162litem &248
8163pos 0
8164dimension 20
8165uid 341,0
8166)
8167*298 (MRCItem
8168litem &249
8169pos 1
8170dimension 20
8171uid 343,0
8172)
8173*299 (MRCItem
8174litem &250
8175pos 2
8176dimension 20
8177uid 345,0
8178)
8179*300 (MRCItem
8180litem &251
8181pos 3
8182dimension 20
8183uid 347,0
8184)
8185*301 (MRCItem
8186litem &252
8187pos 4
8188dimension 20
8189uid 349,0
8190)
8191*302 (MRCItem
8192litem &253
8193pos 5
8194dimension 20
8195uid 405,0
8196)
8197*303 (MRCItem
8198litem &254
8199pos 6
8200dimension 20
8201uid 407,0
8202)
8203*304 (MRCItem
8204litem &255
8205pos 7
8206dimension 20
8207uid 409,0
8208)
8209*305 (MRCItem
8210litem &256
8211pos 8
8212dimension 20
8213uid 457,0
8214)
8215*306 (MRCItem
8216litem &257
8217pos 9
8218dimension 20
8219uid 459,0
8220)
8221*307 (MRCItem
8222litem &258
8223pos 10
8224dimension 20
8225uid 461,0
8226)
8227*308 (MRCItem
8228litem &259
8229pos 11
8230dimension 20
8231uid 585,0
8232)
8233*309 (MRCItem
8234litem &260
8235pos 12
8236dimension 20
8237uid 587,0
8238)
8239*310 (MRCItem
8240litem &261
8241pos 13
8242dimension 20
8243uid 589,0
8244)
8245*311 (MRCItem
8246litem &262
8247pos 14
8248dimension 20
8249uid 591,0
8250)
8251*312 (MRCItem
8252litem &263
8253pos 15
8254dimension 20
8255uid 593,0
8256)
8257*313 (MRCItem
8258litem &264
8259pos 16
8260dimension 20
8261uid 904,0
8262)
8263*314 (MRCItem
8264litem &265
8265pos 17
8266dimension 20
8267uid 906,0
8268)
8269*315 (MRCItem
8270litem &266
8271pos 18
8272dimension 20
8273uid 908,0
8274)
8275*316 (MRCItem
8276litem &267
8277pos 19
8278dimension 20
8279uid 910,0
8280)
8281*317 (MRCItem
8282litem &268
8283pos 20
8284dimension 20
8285uid 912,0
8286)
8287*318 (MRCItem
8288litem &269
8289pos 21
8290dimension 20
8291uid 914,0
8292)
8293*319 (MRCItem
8294litem &270
8295pos 22
8296dimension 20
8297uid 916,0
8298)
8299*320 (MRCItem
8300litem &271
8301pos 23
8302dimension 20
8303uid 918,0
8304)
8305*321 (MRCItem
8306litem &272
8307pos 24
8308dimension 20
8309uid 920,0
8310)
8311*322 (MRCItem
8312litem &273
8313pos 25
8314dimension 20
8315uid 922,0
8316)
8317*323 (MRCItem
8318litem &274
8319pos 26
8320dimension 20
8321uid 924,0
8322)
8323*324 (MRCItem
8324litem &275
8325pos 27
8326dimension 20
8327uid 926,0
8328)
8329*325 (MRCItem
8330litem &276
8331pos 28
8332dimension 20
8333uid 928,0
8334)
8335*326 (MRCItem
8336litem &277
8337pos 29
8338dimension 20
8339uid 930,0
8340)
8341*327 (MRCItem
8342litem &278
8343pos 30
8344dimension 20
8345uid 932,0
8346)
8347*328 (MRCItem
8348litem &279
8349pos 31
8350dimension 20
8351uid 934,0
8352)
8353*329 (MRCItem
8354litem &280
8355pos 32
8356dimension 20
8357uid 936,0
8358)
8359*330 (MRCItem
8360litem &281
8361pos 33
8362dimension 20
8363uid 1542,0
8364)
8365*331 (MRCItem
8366litem &282
8367pos 34
8368dimension 20
8369uid 1544,0
8370)
8371*332 (MRCItem
8372litem &283
8373pos 35
8374dimension 20
8375uid 1546,0
8376)
8377*333 (MRCItem
8378litem &284
8379pos 36
8380dimension 20
8381uid 1548,0
8382)
8383*334 (MRCItem
8384litem &285
8385pos 37
8386dimension 20
8387uid 1550,0
8388)
8389*335 (MRCItem
8390litem &286
8391pos 38
8392dimension 20
8393uid 1552,0
8394)
8395*336 (MRCItem
8396litem &287
8397pos 39
8398dimension 20
8399uid 1554,0
8400)
8401*337 (MRCItem
8402litem &288
8403pos 40
8404dimension 20
8405uid 1556,0
8406)
8407*338 (MRCItem
8408litem &289
8409pos 41
8410dimension 20
8411uid 1576,0
8412)
8413*339 (MRCItem
8414litem &290
8415pos 42
8416dimension 20
8417uid 1691,0
8418)
8419*340 (MRCItem
8420litem &291
8421pos 43
8422dimension 20
8423uid 2004,0
8424)
8425]
8426)
8427sheetCol (SheetCol
8428propVa (MVa
8429cellColor "0,49152,49152"
8430fontColor "0,0,0"
8431font "Tahoma,10,0"
8432textAngle 90
8433)
8434uid 73,0
8435optionalChildren [
8436*341 (MRCItem
8437litem &239
8438pos 0
8439dimension 20
8440uid 74,0
8441)
8442*342 (MRCItem
8443litem &241
8444pos 1
8445dimension 50
8446uid 75,0
8447)
8448*343 (MRCItem
8449litem &242
8450pos 2
8451dimension 100
8452uid 76,0
8453)
8454*344 (MRCItem
8455litem &243
8456pos 3
8457dimension 50
8458uid 77,0
8459)
8460*345 (MRCItem
8461litem &244
8462pos 4
8463dimension 100
8464uid 78,0
8465)
8466*346 (MRCItem
8467litem &245
8468pos 5
8469dimension 100
8470uid 79,0
8471)
8472*347 (MRCItem
8473litem &246
8474pos 6
8475dimension 50
8476uid 80,0
8477)
8478*348 (MRCItem
8479litem &247
8480pos 7
8481dimension 80
8482uid 81,0
8483)
8484]
8485)
8486fixedCol 4
8487fixedRow 2
8488name "Ports"
8489uid 68,0
8490vaOverrides [
8491]
8492)
8493]
8494)
8495uid 53,0
8496)
8497genericsCommonDM (CommonDM
8498ldm (LogicalDM
8499emptyRow *349 (LEmptyRow
8500)
8501uid 83,0
8502optionalChildren [
8503*350 (RefLabelRowHdr
8504)
8505*351 (TitleRowHdr
8506)
8507*352 (FilterRowHdr
8508)
8509*353 (RefLabelColHdr
8510tm "RefLabelColHdrMgr"
8511)
8512*354 (RowExpandColHdr
8513tm "RowExpandColHdrMgr"
8514)
8515*355 (GroupColHdr
8516tm "GroupColHdrMgr"
8517)
8518*356 (NameColHdr
8519tm "GenericNameColHdrMgr"
8520)
8521*357 (TypeColHdr
8522tm "GenericTypeColHdrMgr"
8523)
8524*358 (InitColHdr
8525tm "GenericValueColHdrMgr"
8526)
8527*359 (PragmaColHdr
8528tm "GenericPragmaColHdrMgr"
8529)
8530*360 (EolColHdr
8531tm "GenericEolColHdrMgr"
8532)
8533]
8534)
8535pdm (PhysicalDM
8536displayShortBounds 1
8537editShortBounds 1
8538uid 95,0
8539optionalChildren [
8540*361 (Sheet
8541sheetRow (SheetRow
8542headerVa (MVa
8543cellColor "49152,49152,49152"
8544fontColor "0,0,0"
8545font "Tahoma,10,0"
8546)
8547cellVa (MVa
8548cellColor "65535,65535,65535"
8549fontColor "0,0,0"
8550font "Tahoma,10,0"
8551)
8552groupVa (MVa
8553cellColor "39936,56832,65280"
8554fontColor "0,0,0"
8555font "Tahoma,10,0"
8556)
8557emptyMRCItem *362 (MRCItem
8558litem &349
8559pos 0
8560dimension 20
8561)
8562uid 97,0
8563optionalChildren [
8564*363 (MRCItem
8565litem &350
8566pos 0
8567dimension 20
8568uid 98,0
8569)
8570*364 (MRCItem
8571litem &351
8572pos 1
8573dimension 23
8574uid 99,0
8575)
8576*365 (MRCItem
8577litem &352
8578pos 2
8579hidden 1
8580dimension 20
8581uid 100,0
8582)
8583]
8584)
8585sheetCol (SheetCol
8586propVa (MVa
8587cellColor "0,49152,49152"
8588fontColor "0,0,0"
8589font "Tahoma,10,0"
8590textAngle 90
8591)
8592uid 101,0
8593optionalChildren [
8594*366 (MRCItem
8595litem &353
8596pos 0
8597dimension 20
8598uid 102,0
8599)
8600*367 (MRCItem
8601litem &355
8602pos 1
8603dimension 50
8604uid 103,0
8605)
8606*368 (MRCItem
8607litem &356
8608pos 2
8609dimension 100
8610uid 104,0
8611)
8612*369 (MRCItem
8613litem &357
8614pos 3
8615dimension 100
8616uid 105,0
8617)
8618*370 (MRCItem
8619litem &358
8620pos 4
8621dimension 50
8622uid 106,0
8623)
8624*371 (MRCItem
8625litem &359
8626pos 5
8627dimension 50
8628uid 107,0
8629)
8630*372 (MRCItem
8631litem &360
8632pos 6
8633dimension 80
8634uid 108,0
8635)
8636]
8637)
8638fixedCol 3
8639fixedRow 2
8640name "Ports"
8641uid 96,0
8642vaOverrides [
8643]
8644)
8645]
8646)
8647uid 82,0
8648type 1
8649)
8650activeModelName "BlockDiag"
8651)
Note: See TracBrowser for help on using the repository browser.