source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd @ 10914

Last change on this file since 10914 was 10914, checked in by neise, 9 years ago
File size: 126.6 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
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979fg "0,65535,0"
980)
981xt "109000,21625,109750,22375"
982)
983tg (CPTG
984uid 139,0
985ps "CptPortTextPlaceStrategy"
986stg "RightVerticalLayoutStrategy"
987f (Text
988uid 140,0
989va (VaSet
990)
991xt "100800,21500,108000,22500"
992st "wiz_data : (15:0)"
993ju 2
994blo "108000,22300"
995)
996)
997thePort (LogicalPort
998m 2
999decl (Decl
1000n "wiz_data"
1001t "std_logic_vector"
1002b "(15 DOWNTO 0)"
1003o 53
1004suid 27,0
1005)
1006)
1007)
1008*21 (CptPort
1009uid 141,0
1010ps "OnEdgeStrategy"
1011shape (Triangle
1012uid 142,0
1013ro 90
1014va (VaSet
1015vasetType 1
1016fg "0,65535,0"
1017)
1018xt "109000,27625,109750,28375"
1019)
1020tg (CPTG
1021uid 143,0
1022ps "CptPortTextPlaceStrategy"
1023stg "RightVerticalLayoutStrategy"
1024f (Text
1025uid 144,0
1026va (VaSet
1027)
1028xt "105000,27500,108000,28500"
1029st "wiz_cs"
1030ju 2
1031blo "108000,28300"
1032)
1033)
1034thePort (LogicalPort
1035m 1
1036decl (Decl
1037n "wiz_cs"
1038t "std_logic"
1039o 48
1040suid 28,0
1041i "'1'"
1042)
1043)
1044)
1045*22 (CptPort
1046uid 145,0
1047ps "OnEdgeStrategy"
1048shape (Triangle
1049uid 146,0
1050ro 90
1051va (VaSet
1052vasetType 1
1053fg "0,65535,0"
1054)
1055xt "109000,25625,109750,26375"
1056)
1057tg (CPTG
1058uid 147,0
1059ps "CptPortTextPlaceStrategy"
1060stg "RightVerticalLayoutStrategy"
1061f (Text
1062uid 148,0
1063va (VaSet
1064)
1065xt "104800,25500,108000,26500"
1066st "wiz_wr"
1067ju 2
1068blo "108000,26300"
1069)
1070)
1071thePort (LogicalPort
1072m 1
1073decl (Decl
1074n "wiz_wr"
1075t "std_logic"
1076o 51
1077suid 29,0
1078i "'1'"
1079)
1080)
1081)
1082*23 (CptPort
1083uid 149,0
1084ps "OnEdgeStrategy"
1085shape (Triangle
1086uid 150,0
1087ro 90
1088va (VaSet
1089vasetType 1
1090fg "0,65535,0"
1091)
1092xt "109000,24625,109750,25375"
1093)
1094tg (CPTG
1095uid 151,0
1096ps "CptPortTextPlaceStrategy"
1097stg "RightVerticalLayoutStrategy"
1098f (Text
1099uid 152,0
1100va (VaSet
1101)
1102xt "104900,24500,108000,25500"
1103st "wiz_rd"
1104ju 2
1105blo "108000,25300"
1106)
1107)
1108thePort (LogicalPort
1109m 1
1110decl (Decl
1111n "wiz_rd"
1112t "std_logic"
1113o 49
1114suid 30,0
1115i "'1'"
1116)
1117)
1118)
1119*24 (CptPort
1120uid 153,0
1121ps "OnEdgeStrategy"
1122shape (Triangle
1123uid 154,0
1124ro 270
1125va (VaSet
1126vasetType 1
1127fg "0,65535,0"
1128)
1129xt "109000,26625,109750,27375"
1130)
1131tg (CPTG
1132uid 155,0
1133ps "CptPortTextPlaceStrategy"
1134stg "RightVerticalLayoutStrategy"
1135f (Text
1136uid 156,0
1137va (VaSet
1138)
1139xt "104800,26500,108000,27500"
1140st "wiz_int"
1141ju 2
1142blo "108000,27300"
1143)
1144)
1145thePort (LogicalPort
1146decl (Decl
1147n "wiz_int"
1148t "std_logic"
1149o 15
1150suid 31,0
1151)
1152)
1153)
1154*25 (CptPort
1155uid 157,0
1156ps "OnEdgeStrategy"
1157shape (Triangle
1158uid 158,0
1159ro 270
1160va (VaSet
1161vasetType 1
1162fg "0,65535,0"
1163)
1164xt "80250,22625,81000,23375"
1165)
1166tg (CPTG
1167uid 159,0
1168ps "CptPortTextPlaceStrategy"
1169stg "VerticalLayoutStrategy"
1170f (Text
1171uid 160,0
1172va (VaSet
1173)
1174xt "82000,22500,86800,23500"
1175st "CLK_25_PS"
1176blo "82000,23300"
1177)
1178)
1179thePort (LogicalPort
1180m 1
1181decl (Decl
1182n "CLK_25_PS"
1183t "std_logic"
1184o 17
1185suid 35,0
1186)
1187)
1188)
1189*26 (CptPort
1190uid 161,0
1191ps "OnEdgeStrategy"
1192shape (Triangle
1193uid 162,0
1194ro 270
1195va (VaSet
1196vasetType 1
1197fg "0,65535,0"
1198)
1199xt "80250,21625,81000,22375"
1200)
1201tg (CPTG
1202uid 163,0
1203ps "CptPortTextPlaceStrategy"
1204stg "VerticalLayoutStrategy"
1205f (Text
1206uid 164,0
1207va (VaSet
1208)
1209xt "82000,21500,85300,22500"
1210st "CLK_50"
1211blo "82000,22300"
1212)
1213)
1214thePort (LogicalPort
1215m 1
1216decl (Decl
1217n "CLK_50"
1218t "std_logic"
1219preAdd 0
1220posAdd 0
1221o 18
1222suid 37,0
1223)
1224)
1225)
1226*27 (CptPort
1227uid 165,0
1228ps "OnEdgeStrategy"
1229shape (Triangle
1230uid 166,0
1231ro 90
1232va (VaSet
1233vasetType 1
1234fg "0,65535,0"
1235)
1236xt "80250,20625,81000,21375"
1237)
1238tg (CPTG
1239uid 167,0
1240ps "CptPortTextPlaceStrategy"
1241stg "VerticalLayoutStrategy"
1242f (Text
1243uid 168,0
1244va (VaSet
1245)
1246xt "82000,20500,83900,21500"
1247st "CLK"
1248blo "82000,21300"
1249)
1250)
1251thePort (LogicalPort
1252decl (Decl
1253n "CLK"
1254t "std_logic"
1255o 1
1256suid 38,0
1257)
1258)
1259)
1260*28 (CptPort
1261uid 169,0
1262ps "OnEdgeStrategy"
1263shape (Triangle
1264uid 170,0
1265ro 90
1266va (VaSet
1267vasetType 1
1268fg "0,65535,0"
1269)
1270xt "80250,41625,81000,42375"
1271)
1272tg (CPTG
1273uid 171,0
1274ps "CptPortTextPlaceStrategy"
1275stg "VerticalLayoutStrategy"
1276f (Text
1277uid 172,0
1278va (VaSet
1279)
1280xt "82000,41500,91300,42500"
1281st "adc_otr_array : (3:0)"
1282blo "82000,42300"
1283)
1284)
1285thePort (LogicalPort
1286decl (Decl
1287n "adc_otr_array"
1288t "std_logic_vector"
1289b "(3 DOWNTO 0)"
1290o 9
1291suid 40,0
1292)
1293)
1294)
1295*29 (CptPort
1296uid 173,0
1297ps "OnEdgeStrategy"
1298shape (Triangle
1299uid 174,0
1300ro 90
1301va (VaSet
1302vasetType 1
1303fg "0,65535,0"
1304)
1305xt "80250,47625,81000,48375"
1306)
1307tg (CPTG
1308uid 175,0
1309ps "CptPortTextPlaceStrategy"
1310stg "VerticalLayoutStrategy"
1311f (Text
1312uid 176,0
1313va (VaSet
1314)
1315xt "82000,47500,88900,48500"
1316st "adc_data_array"
1317blo "82000,48300"
1318)
1319)
1320thePort (LogicalPort
1321decl (Decl
1322n "adc_data_array"
1323t "adc_data_array_type"
1324o 8
1325suid 41,0
1326)
1327)
1328)
1329*30 (CptPort
1330uid 177,0
1331ps "OnEdgeStrategy"
1332shape (Triangle
1333uid 178,0
1334ro 270
1335va (VaSet
1336vasetType 1
1337fg "0,65535,0"
1338)
1339xt "80250,61625,81000,62375"
1340)
1341tg (CPTG
1342uid 179,0
1343ps "CptPortTextPlaceStrategy"
1344stg "VerticalLayoutStrategy"
1345f (Text
1346uid 180,0
1347va (VaSet
1348)
1349xt "82000,61500,91500,62500"
1350st "drs_channel_id : (3:0)"
1351blo "82000,62300"
1352)
1353)
1354thePort (LogicalPort
1355m 1
1356decl (Decl
1357n "drs_channel_id"
1358t "std_logic_vector"
1359b "(3 downto 0)"
1360o 35
1361suid 48,0
1362i "(others => '0')"
1363)
1364)
1365)
1366*31 (CptPort
1367uid 181,0
1368ps "OnEdgeStrategy"
1369shape (Triangle
1370uid 182,0
1371ro 270
1372va (VaSet
1373vasetType 1
1374fg "0,65535,0"
1375)
1376xt "80250,66625,81000,67375"
1377)
1378tg (CPTG
1379uid 183,0
1380ps "CptPortTextPlaceStrategy"
1381stg "VerticalLayoutStrategy"
1382f (Text
1383uid 184,0
1384va (VaSet
1385)
1386xt "82000,66500,87200,67500"
1387st "drs_dwrite"
1388blo "82000,67300"
1389)
1390)
1391thePort (LogicalPort
1392m 1
1393decl (Decl
1394n "drs_dwrite"
1395t "std_logic"
1396o 36
1397suid 49,0
1398i "'1'"
1399)
1400)
1401)
1402*32 (CptPort
1403uid 185,0
1404ps "OnEdgeStrategy"
1405shape (Triangle
1406uid 186,0
1407ro 90
1408va (VaSet
1409vasetType 1
1410fg "0,65535,0"
1411)
1412xt "80250,57625,81000,58375"
1413)
1414tg (CPTG
1415uid 187,0
1416ps "CptPortTextPlaceStrategy"
1417stg "VerticalLayoutStrategy"
1418f (Text
1419uid 188,0
1420va (VaSet
1421)
1422xt "82000,57500,87800,58500"
1423st "SROUT_in_0"
1424blo "82000,58300"
1425)
1426)
1427thePort (LogicalPort
1428decl (Decl
1429n "SROUT_in_0"
1430t "std_logic"
1431o 4
1432suid 52,0
1433)
1434)
1435)
1436*33 (CptPort
1437uid 189,0
1438ps "OnEdgeStrategy"
1439shape (Triangle
1440uid 190,0
1441ro 90
1442va (VaSet
1443vasetType 1
1444fg "0,65535,0"
1445)
1446xt "80250,58625,81000,59375"
1447)
1448tg (CPTG
1449uid 191,0
1450ps "CptPortTextPlaceStrategy"
1451stg "VerticalLayoutStrategy"
1452f (Text
1453uid 192,0
1454va (VaSet
1455)
1456xt "82000,58500,87700,59500"
1457st "SROUT_in_1"
1458blo "82000,59300"
1459)
1460)
1461thePort (LogicalPort
1462decl (Decl
1463n "SROUT_in_1"
1464t "std_logic"
1465o 5
1466suid 53,0
1467)
1468)
1469)
1470*34 (CptPort
1471uid 193,0
1472ps "OnEdgeStrategy"
1473shape (Triangle
1474uid 194,0
1475ro 90
1476va (VaSet
1477vasetType 1
1478fg "0,65535,0"
1479)
1480xt "80250,59625,81000,60375"
1481)
1482tg (CPTG
1483uid 195,0
1484ps "CptPortTextPlaceStrategy"
1485stg "VerticalLayoutStrategy"
1486f (Text
1487uid 196,0
1488va (VaSet
1489)
1490xt "82000,59500,87800,60500"
1491st "SROUT_in_2"
1492blo "82000,60300"
1493)
1494)
1495thePort (LogicalPort
1496decl (Decl
1497n "SROUT_in_2"
1498t "std_logic"
1499o 6
1500suid 54,0
1501)
1502)
1503)
1504*35 (CptPort
1505uid 197,0
1506ps "OnEdgeStrategy"
1507shape (Triangle
1508uid 198,0
1509ro 90
1510va (VaSet
1511vasetType 1
1512fg "0,65535,0"
1513)
1514xt "80250,60625,81000,61375"
1515)
1516tg (CPTG
1517uid 199,0
1518ps "CptPortTextPlaceStrategy"
1519stg "VerticalLayoutStrategy"
1520f (Text
1521uid 200,0
1522va (VaSet
1523)
1524xt "82000,60500,87800,61500"
1525st "SROUT_in_3"
1526blo "82000,61300"
1527)
1528)
1529thePort (LogicalPort
1530decl (Decl
1531n "SROUT_in_3"
1532t "std_logic"
1533o 7
1534suid 55,0
1535)
1536)
1537)
1538*36 (CptPort
1539uid 201,0
1540ps "OnEdgeStrategy"
1541shape (Triangle
1542uid 202,0
1543ro 270
1544va (VaSet
1545vasetType 1
1546fg "0,65535,0"
1547)
1548xt "80250,63625,81000,64375"
1549)
1550tg (CPTG
1551uid 203,0
1552ps "CptPortTextPlaceStrategy"
1553stg "VerticalLayoutStrategy"
1554f (Text
1555uid 204,0
1556va (VaSet
1557)
1558xt "82000,63500,86200,64500"
1559st "RSRLOAD"
1560blo "82000,64300"
1561)
1562)
1563thePort (LogicalPort
1564m 1
1565decl (Decl
1566n "RSRLOAD"
1567t "std_logic"
1568o 23
1569suid 56,0
1570i "'0'"
1571)
1572)
1573)
1574*37 (CptPort
1575uid 205,0
1576ps "OnEdgeStrategy"
1577shape (Triangle
1578uid 206,0
1579ro 270
1580va (VaSet
1581vasetType 1
1582fg "0,65535,0"
1583)
1584xt "80250,64625,81000,65375"
1585)
1586tg (CPTG
1587uid 207,0
1588ps "CptPortTextPlaceStrategy"
1589stg "VerticalLayoutStrategy"
1590f (Text
1591uid 208,0
1592va (VaSet
1593)
1594xt "82000,64500,84900,65500"
1595st "SRCLK"
1596blo "82000,65300"
1597)
1598)
1599thePort (LogicalPort
1600m 1
1601decl (Decl
1602n "SRCLK"
1603t "std_logic"
1604o 24
1605suid 57,0
1606i "'0'"
1607)
1608)
1609)
1610*38 (CptPort
1611uid 209,0
1612ps "OnEdgeStrategy"
1613shape (Triangle
1614uid 210,0
1615ro 90
1616va (VaSet
1617vasetType 1
1618fg "0,65535,0"
1619)
1620xt "109000,50625,109750,51375"
1621)
1622tg (CPTG
1623uid 211,0
1624ps "CptPortTextPlaceStrategy"
1625stg "RightVerticalLayoutStrategy"
1626f (Text
1627uid 212,0
1628va (VaSet
1629)
1630xt "106100,50500,108000,51500"
1631st "sclk"
1632ju 2
1633blo "108000,51300"
1634)
1635)
1636thePort (LogicalPort
1637m 1
1638decl (Decl
1639n "sclk"
1640t "std_logic"
1641o 42
1642suid 62,0
1643)
1644)
1645)
1646*39 (CptPort
1647uid 213,0
1648ps "OnEdgeStrategy"
1649shape (Diamond
1650uid 214,0
1651ro 90
1652va (VaSet
1653vasetType 1
1654fg "0,65535,0"
1655)
1656xt "109000,51625,109750,52375"
1657)
1658tg (CPTG
1659uid 215,0
1660ps "CptPortTextPlaceStrategy"
1661stg "RightVerticalLayoutStrategy"
1662f (Text
1663uid 216,0
1664va (VaSet
1665)
1666xt "106600,51500,108000,52500"
1667st "sio"
1668ju 2
1669blo "108000,52300"
1670)
1671)
1672thePort (LogicalPort
1673m 2
1674decl (Decl
1675n "sio"
1676t "std_logic"
1677preAdd 0
1678posAdd 0
1679o 52
1680suid 63,0
1681)
1682)
1683)
1684*40 (CptPort
1685uid 217,0
1686ps "OnEdgeStrategy"
1687shape (Triangle
1688uid 218,0
1689ro 90
1690va (VaSet
1691vasetType 1
1692fg "0,65535,0"
1693)
1694xt "109000,39625,109750,40375"
1695)
1696tg (CPTG
1697uid 219,0
1698ps "CptPortTextPlaceStrategy"
1699stg "RightVerticalLayoutStrategy"
1700f (Text
1701uid 220,0
1702va (VaSet
1703)
1704xt "105000,39500,108000,40500"
1705st "dac_cs"
1706ju 2
1707blo "108000,40300"
1708)
1709)
1710thePort (LogicalPort
1711m 1
1712decl (Decl
1713n "dac_cs"
1714t "std_logic"
1715o 31
1716suid 64,0
1717)
1718)
1719)
1720*41 (CptPort
1721uid 221,0
1722ps "OnEdgeStrategy"
1723shape (Triangle
1724uid 222,0
1725ro 90
1726va (VaSet
1727vasetType 1
1728fg "0,65535,0"
1729)
1730xt "109000,41625,109750,42375"
1731)
1732tg (CPTG
1733uid 223,0
1734ps "CptPortTextPlaceStrategy"
1735stg "RightVerticalLayoutStrategy"
1736f (Text
1737uid 224,0
1738va (VaSet
1739)
1740xt "101000,41500,108000,42500"
1741st "sensor_cs : (3:0)"
1742ju 2
1743blo "108000,42300"
1744)
1745)
1746thePort (LogicalPort
1747m 1
1748decl (Decl
1749n "sensor_cs"
1750t "std_logic_vector"
1751b "(3 DOWNTO 0)"
1752o 43
1753suid 65,0
1754)
1755)
1756)
1757*42 (CptPort
1758uid 225,0
1759ps "OnEdgeStrategy"
1760shape (Triangle
1761uid 226,0
1762ro 90
1763va (VaSet
1764vasetType 1
1765fg "0,65535,0"
1766)
1767xt "109000,52625,109750,53375"
1768)
1769tg (CPTG
1770uid 227,0
1771ps "CptPortTextPlaceStrategy"
1772stg "RightVerticalLayoutStrategy"
1773f (Text
1774uid 228,0
1775va (VaSet
1776)
1777xt "106000,52500,108000,53500"
1778st "mosi"
1779ju 2
1780blo "108000,53300"
1781)
1782)
1783thePort (LogicalPort
1784m 1
1785decl (Decl
1786n "mosi"
1787t "std_logic"
1788o 40
1789suid 66,0
1790i "'0'"
1791)
1792)
1793)
1794*43 (CptPort
1795uid 229,0
1796ps "OnEdgeStrategy"
1797shape (Triangle
1798uid 230,0
1799ro 270
1800va (VaSet
1801vasetType 1
1802fg "0,65535,0"
1803)
1804xt "80250,65625,81000,66375"
1805)
1806tg (CPTG
1807uid 231,0
1808ps "CptPortTextPlaceStrategy"
1809stg "VerticalLayoutStrategy"
1810f (Text
1811uid 232,0
1812va (VaSet
1813)
1814xt "82000,65500,85200,66500"
1815st "denable"
1816blo "82000,66300"
1817)
1818)
1819thePort (LogicalPort
1820m 1
1821decl (Decl
1822n "denable"
1823t "std_logic"
1824eolc "-- default domino wave off"
1825posAdd 0
1826o 34
1827suid 67,0
1828i "'0'"
1829)
1830)
1831)
1832*44 (CptPort
1833uid 1395,0
1834ps "OnEdgeStrategy"
1835shape (Triangle
1836uid 1396,0
1837ro 90
1838va (VaSet
1839vasetType 1
1840fg "0,65535,0"
1841)
1842xt "109000,73625,109750,74375"
1843)
1844tg (CPTG
1845uid 1397,0
1846ps "CptPortTextPlaceStrategy"
1847stg "RightVerticalLayoutStrategy"
1848f (Text
1849uid 1398,0
1850va (VaSet
1851)
1852xt "98000,73500,108000,74500"
1853st "alarm_refclk_too_high"
1854ju 2
1855blo "108000,74300"
1856)
1857)
1858thePort (LogicalPort
1859m 1
1860decl (Decl
1861n "alarm_refclk_too_high"
1862t "std_logic"
1863o 27
1864suid 95,0
1865)
1866)
1867)
1868*45 (CptPort
1869uid 1399,0
1870ps "OnEdgeStrategy"
1871shape (Triangle
1872uid 1400,0
1873ro 90
1874va (VaSet
1875vasetType 1
1876fg "0,65535,0"
1877)
1878xt "109000,74625,109750,75375"
1879)
1880tg (CPTG
1881uid 1401,0
1882ps "CptPortTextPlaceStrategy"
1883stg "RightVerticalLayoutStrategy"
1884f (Text
1885uid 1402,0
1886va (VaSet
1887)
1888xt "98400,74500,108000,75500"
1889st "alarm_refclk_too_low"
1890ju 2
1891blo "108000,75300"
1892)
1893)
1894thePort (LogicalPort
1895m 1
1896decl (Decl
1897n "alarm_refclk_too_low"
1898t "std_logic"
1899posAdd 0
1900o 28
1901suid 96,0
1902)
1903)
1904)
1905*46 (CptPort
1906uid 1403,0
1907ps "OnEdgeStrategy"
1908shape (Triangle
1909uid 1404,0
1910ro 90
1911va (VaSet
1912vasetType 1
1913fg "0,65535,0"
1914)
1915xt "109000,79625,109750,80375"
1916)
1917tg (CPTG
1918uid 1405,0
1919ps "CptPortTextPlaceStrategy"
1920stg "RightVerticalLayoutStrategy"
1921f (Text
1922uid 1406,0
1923va (VaSet
1924)
1925xt "105300,79500,108000,80500"
1926st "amber"
1927ju 2
1928blo "108000,80300"
1929)
1930)
1931thePort (LogicalPort
1932m 1
1933decl (Decl
1934n "amber"
1935t "std_logic"
1936o 29
1937suid 87,0
1938)
1939)
1940)
1941*47 (CptPort
1942uid 1407,0
1943ps "OnEdgeStrategy"
1944shape (Triangle
1945uid 1408,0
1946ro 90
1947va (VaSet
1948vasetType 1
1949fg "0,65535,0"
1950)
1951xt "109000,76625,109750,77375"
1952)
1953tg (CPTG
1954uid 1409,0
1955ps "CptPortTextPlaceStrategy"
1956stg "RightVerticalLayoutStrategy"
1957f (Text
1958uid 1410,0
1959va (VaSet
1960)
1961xt "98400,76500,108000,77500"
1962st "counter_result : (11:0)"
1963ju 2
1964blo "108000,77300"
1965)
1966)
1967thePort (LogicalPort
1968m 1
1969decl (Decl
1970n "counter_result"
1971t "std_logic_vector"
1972b "(11 DOWNTO 0)"
1973o 30
1974suid 94,0
1975)
1976)
1977)
1978*48 (CptPort
1979uid 1411,0
1980ps "OnEdgeStrategy"
1981shape (Triangle
1982uid 1412,0
1983ro 90
1984va (VaSet
1985vasetType 1
1986fg "0,65535,0"
1987)
1988xt "80250,74625,81000,75375"
1989)
1990tg (CPTG
1991uid 1413,0
1992ps "CptPortTextPlaceStrategy"
1993stg "VerticalLayoutStrategy"
1994f (Text
1995uid 1414,0
1996va (VaSet
1997)
1998xt "82000,74500,87500,75500"
1999st "D_T_in : (1:0)"
2000blo "82000,75300"
2001)
2002)
2003thePort (LogicalPort
2004decl (Decl
2005n "D_T_in"
2006t "std_logic_vector"
2007b "(1 DOWNTO 0)"
2008o 2
2009suid 91,0
2010)
2011)
2012)
2013*49 (CptPort
2014uid 1415,0
2015ps "OnEdgeStrategy"
2016shape (Triangle
2017uid 1416,0
2018ro 90
2019va (VaSet
2020vasetType 1
2021fg "0,65535,0"
2022)
2023xt "80250,75625,81000,76375"
2024)
2025tg (CPTG
2026uid 1417,0
2027ps "CptPortTextPlaceStrategy"
2028stg "VerticalLayoutStrategy"
2029f (Text
2030uid 1418,0
2031va (VaSet
2032)
2033xt "82000,75500,88100,76500"
2034st "drs_refclk_in"
2035blo "82000,76300"
2036)
2037)
2038thePort (LogicalPort
2039decl (Decl
2040n "drs_refclk_in"
2041t "std_logic"
2042eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
2043o 12
2044suid 92,0
2045)
2046)
2047)
2048*50 (CptPort
2049uid 1419,0
2050ps "OnEdgeStrategy"
2051shape (Triangle
2052uid 1420,0
2053ro 90
2054va (VaSet
2055vasetType 1
2056fg "0,65535,0"
2057)
2058xt "109000,77625,109750,78375"
2059)
2060tg (CPTG
2061uid 1421,0
2062ps "CptPortTextPlaceStrategy"
2063stg "RightVerticalLayoutStrategy"
2064f (Text
2065uid 1422,0
2066va (VaSet
2067)
2068xt "105600,77500,108000,78500"
2069st "green"
2070ju 2
2071blo "108000,78300"
2072)
2073)
2074thePort (LogicalPort
2075m 1
2076decl (Decl
2077n "green"
2078t "std_logic"
2079o 37
2080suid 86,0
2081)
2082)
2083)
2084*51 (CptPort
2085uid 1423,0
2086ps "OnEdgeStrategy"
2087shape (Triangle
2088uid 1424,0
2089ro 90
2090va (VaSet
2091vasetType 1
2092fg "0,65535,0"
2093)
2094xt "80250,76625,81000,77375"
2095)
2096tg (CPTG
2097uid 1425,0
2098ps "CptPortTextPlaceStrategy"
2099stg "VerticalLayoutStrategy"
2100f (Text
2101uid 1426,0
2102va (VaSet
2103)
2104xt "82000,76500,88700,77500"
2105st "plllock_in : (3:0)"
2106blo "82000,77300"
2107)
2108)
2109thePort (LogicalPort
2110decl (Decl
2111n "plllock_in"
2112t "std_logic_vector"
2113b "(3 DOWNTO 0)"
2114eolc "-- high level, if dominowave is running and DRS PLL locked"
2115o 13
2116suid 93,0
2117)
2118)
2119)
2120*52 (CptPort
2121uid 1427,0
2122ps "OnEdgeStrategy"
2123shape (Triangle
2124uid 1428,0
2125ro 90
2126va (VaSet
2127vasetType 1
2128fg "0,65535,0"
2129)
2130xt "109000,78625,109750,79375"
2131)
2132tg (CPTG
2133uid 1429,0
2134ps "CptPortTextPlaceStrategy"
2135stg "RightVerticalLayoutStrategy"
2136f (Text
2137uid 1430,0
2138va (VaSet
2139)
2140xt "106300,78500,108000,79500"
2141st "red"
2142ju 2
2143blo "108000,79300"
2144)
2145)
2146thePort (LogicalPort
2147m 1
2148decl (Decl
2149n "red"
2150t "std_logic"
2151o 41
2152suid 88,0
2153)
2154)
2155)
2156*53 (CptPort
2157uid 1431,0
2158ps "OnEdgeStrategy"
2159shape (Triangle
2160uid 1432,0
2161ro 270
2162va (VaSet
2163vasetType 1
2164fg "0,65535,0"
2165)
2166xt "80250,71625,81000,72375"
2167)
2168tg (CPTG
2169uid 1433,0
2170ps "CptPortTextPlaceStrategy"
2171stg "VerticalLayoutStrategy"
2172f (Text
2173uid 1434,0
2174va (VaSet
2175)
2176xt "82000,71500,86200,72500"
2177st "SRIN_out"
2178blo "82000,72300"
2179)
2180)
2181thePort (LogicalPort
2182m 1
2183decl (Decl
2184n "SRIN_out"
2185t "std_logic"
2186o 25
2187suid 85,0
2188i "'0'"
2189)
2190)
2191)
2192*54 (CptPort
2193uid 1678,0
2194ps "OnEdgeStrategy"
2195shape (Triangle
2196uid 1679,0
2197ro 270
2198va (VaSet
2199vasetType 1
2200fg "0,65535,0"
2201)
2202xt "80250,23625,81000,24375"
2203)
2204tg (CPTG
2205uid 1680,0
2206ps "CptPortTextPlaceStrategy"
2207stg "VerticalLayoutStrategy"
2208f (Text
2209uid 1681,0
2210va (VaSet
2211)
2212xt "82000,23500,86000,24500"
2213st "ADC_CLK"
2214blo "82000,24300"
2215)
2216)
2217thePort (LogicalPort
2218lang 2
2219m 1
2220decl (Decl
2221n "ADC_CLK"
2222t "std_logic"
2223o 16
2224suid 97,0
2225)
2226)
2227)
2228*55 (CptPort
2229uid 2651,0
2230ps "OnEdgeStrategy"
2231shape (Triangle
2232uid 2652,0
2233ro 90
2234va (VaSet
2235vasetType 1
2236fg "0,65535,0"
2237)
2238xt "109000,80625,109750,81375"
2239)
2240tg (CPTG
2241uid 2653,0
2242ps "CptPortTextPlaceStrategy"
2243stg "RightVerticalLayoutStrategy"
2244f (Text
2245uid 2654,0
2246va (VaSet
2247)
2248xt "97600,80500,108000,81500"
2249st "debug_data_ram_empty"
2250ju 2
2251blo "108000,81300"
2252)
2253)
2254thePort (LogicalPort
2255m 1
2256decl (Decl
2257n "debug_data_ram_empty"
2258t "std_logic"
2259o 32
2260suid 104,0
2261)
2262)
2263)
2264*56 (CptPort
2265uid 2655,0
2266ps "OnEdgeStrategy"
2267shape (Triangle
2268uid 2656,0
2269ro 90
2270va (VaSet
2271vasetType 1
2272fg "0,65535,0"
2273)
2274xt "109000,81625,109750,82375"
2275)
2276tg (CPTG
2277uid 2657,0
2278ps "CptPortTextPlaceStrategy"
2279stg "RightVerticalLayoutStrategy"
2280f (Text
2281uid 2658,0
2282va (VaSet
2283)
2284xt "100500,81500,108000,82500"
2285st "debug_data_valid"
2286ju 2
2287blo "108000,82300"
2288)
2289)
2290thePort (LogicalPort
2291m 1
2292decl (Decl
2293n "debug_data_valid"
2294t "std_logic"
2295o 33
2296suid 105,0
2297)
2298)
2299)
2300*57 (CptPort
2301uid 2659,0
2302ps "OnEdgeStrategy"
2303shape (Triangle
2304uid 2660,0
2305ro 90
2306va (VaSet
2307vasetType 1
2308fg "0,65535,0"
2309)
2310xt "109000,82625,109750,83375"
2311)
2312tg (CPTG
2313uid 2661,0
2314ps "CptPortTextPlaceStrategy"
2315stg "RightVerticalLayoutStrategy"
2316f (Text
2317uid 2662,0
2318va (VaSet
2319)
2320xt "101100,82500,108000,83500"
2321st "DG_state : (7:0)"
2322ju 2
2323blo "108000,83300"
2324)
2325)
2326thePort (LogicalPort
2327m 1
2328decl (Decl
2329n "DG_state"
2330t "std_logic_vector"
2331b "(7 downto 0)"
2332prec "-- for debugging"
2333preAdd 0
2334o 19
2335suid 108,0
2336)
2337)
2338)
2339*58 (CptPort
2340uid 2663,0
2341ps "OnEdgeStrategy"
2342shape (Triangle
2343uid 2664,0
2344ro 90
2345va (VaSet
2346vasetType 1
2347fg "0,65535,0"
2348)
2349xt "80250,77625,81000,78375"
2350)
2351tg (CPTG
2352uid 2665,0
2353ps "CptPortTextPlaceStrategy"
2354stg "VerticalLayoutStrategy"
2355f (Text
2356uid 2666,0
2357va (VaSet
2358)
2359xt "82000,77500,90100,78500"
2360st "FTM_RS485_rx_d"
2361blo "82000,78300"
2362)
2363)
2364thePort (LogicalPort
2365decl (Decl
2366n "FTM_RS485_rx_d"
2367t "std_logic"
2368o 3
2369suid 99,0
2370)
2371)
2372)
2373*59 (CptPort
2374uid 2667,0
2375ps "OnEdgeStrategy"
2376shape (Triangle
2377uid 2668,0
2378ro 90
2379va (VaSet
2380vasetType 1
2381fg "0,65535,0"
2382)
2383xt "109000,83625,109750,84375"
2384)
2385tg (CPTG
2386uid 2669,0
2387ps "CptPortTextPlaceStrategy"
2388stg "RightVerticalLayoutStrategy"
2389f (Text
2390uid 2670,0
2391va (VaSet
2392)
2393xt "99600,83500,108000,84500"
2394st "FTM_RS485_rx_en"
2395ju 2
2396blo "108000,84300"
2397)
2398)
2399thePort (LogicalPort
2400m 1
2401decl (Decl
2402n "FTM_RS485_rx_en"
2403t "std_logic"
2404o 20
2405suid 101,0
2406)
2407)
2408)
2409*60 (CptPort
2410uid 2671,0
2411ps "OnEdgeStrategy"
2412shape (Triangle
2413uid 2672,0
2414ro 90
2415va (VaSet
2416vasetType 1
2417fg "0,65535,0"
2418)
2419xt "109000,84625,109750,85375"
2420)
2421tg (CPTG
2422uid 2673,0
2423ps "CptPortTextPlaceStrategy"
2424stg "RightVerticalLayoutStrategy"
2425f (Text
2426uid 2674,0
2427va (VaSet
2428)
2429xt "99900,84500,108000,85500"
2430st "FTM_RS485_tx_d"
2431ju 2
2432blo "108000,85300"
2433)
2434)
2435thePort (LogicalPort
2436m 1
2437decl (Decl
2438n "FTM_RS485_tx_d"
2439t "std_logic"
2440o 21
2441suid 100,0
2442)
2443)
2444)
2445*61 (CptPort
2446uid 2675,0
2447ps "OnEdgeStrategy"
2448shape (Triangle
2449uid 2676,0
2450ro 90
2451va (VaSet
2452vasetType 1
2453fg "0,65535,0"
2454)
2455xt "109000,85625,109750,86375"
2456)
2457tg (CPTG
2458uid 2677,0
2459ps "CptPortTextPlaceStrategy"
2460stg "RightVerticalLayoutStrategy"
2461f (Text
2462uid 2678,0
2463va (VaSet
2464)
2465xt "99600,85500,108000,86500"
2466st "FTM_RS485_tx_en"
2467ju 2
2468blo "108000,86300"
2469)
2470)
2471thePort (LogicalPort
2472m 1
2473decl (Decl
2474n "FTM_RS485_tx_en"
2475t "std_logic"
2476o 22
2477suid 102,0
2478)
2479)
2480)
2481*62 (CptPort
2482uid 2679,0
2483ps "OnEdgeStrategy"
2484shape (Triangle
2485uid 2680,0
2486ro 90
2487va (VaSet
2488vasetType 1
2489fg "0,65535,0"
2490)
2491xt "109000,86625,109750,87375"
2492)
2493tg (CPTG
2494uid 2681,0
2495ps "CptPortTextPlaceStrategy"
2496stg "RightVerticalLayoutStrategy"
2497f (Text
2498uid 2682,0
2499va (VaSet
2500)
2501xt "96600,86500,108000,87500"
2502st "mem_manager_state : (3:0)"
2503ju 2
2504blo "108000,87300"
2505)
2506)
2507thePort (LogicalPort
2508lang 2
2509m 1
2510decl (Decl
2511n "mem_manager_state"
2512t "std_logic_vector"
2513b "(3 DOWNTO 0)"
2514eolc "-- state is encoded here ... useful for debugging."
2515posAdd 0
2516o 39
2517suid 106,0
2518)
2519)
2520)
2521*63 (CptPort
2522uid 2683,0
2523ps "OnEdgeStrategy"
2524shape (Triangle
2525uid 2684,0
2526ro 90
2527va (VaSet
2528vasetType 1
2529fg "0,65535,0"
2530)
2531xt "109000,87625,109750,88375"
2532)
2533tg (CPTG
2534uid 2685,0
2535ps "CptPortTextPlaceStrategy"
2536stg "RightVerticalLayoutStrategy"
2537f (Text
2538uid 2686,0
2539va (VaSet
2540)
2541xt "102400,87500,108000,88500"
2542st "trigger_veto"
2543ju 2
2544blo "108000,88300"
2545)
2546)
2547thePort (LogicalPort
2548m 1
2549decl (Decl
2550n "trigger_veto"
2551t "std_logic"
2552o 45
2553suid 98,0
2554i "'1'"
2555)
2556)
2557)
2558*64 (CptPort
2559uid 2687,0
2560ps "OnEdgeStrategy"
2561shape (Triangle
2562uid 2688,0
2563ro 90
2564va (VaSet
2565vasetType 1
2566fg "0,65535,0"
2567)
2568xt "109000,88625,109750,89375"
2569)
2570tg (CPTG
2571uid 2689,0
2572ps "CptPortTextPlaceStrategy"
2573stg "RightVerticalLayoutStrategy"
2574f (Text
2575uid 2690,0
2576va (VaSet
2577)
2578xt "99600,88500,108000,89500"
2579st "w5300_state : (7:0)"
2580ju 2
2581blo "108000,89300"
2582)
2583)
2584thePort (LogicalPort
2585m 1
2586decl (Decl
2587n "w5300_state"
2588t "std_logic_vector"
2589b "(7 DOWNTO 0)"
2590eolc "-- state is encoded here ... useful for debugging."
2591posAdd 0
2592o 46
2593suid 103,0
2594)
2595)
2596)
2597*65 (CptPort
2598uid 2924,0
2599ps "OnEdgeStrategy"
2600shape (Triangle
2601uid 2925,0
2602ro 90
2603va (VaSet
2604vasetType 1
2605fg "0,65535,0"
2606)
2607xt "109000,89625,109750,90375"
2608)
2609tg (CPTG
2610uid 2926,0
2611ps "CptPortTextPlaceStrategy"
2612stg "RightVerticalLayoutStrategy"
2613f (Text
2614uid 2927,0
2615va (VaSet
2616)
2617xt "96100,89500,108000,90500"
2618st "socket_tx_free_out : (16:0)"
2619ju 2
2620blo "108000,90300"
2621)
2622)
2623thePort (LogicalPort
2624m 1
2625decl (Decl
2626n "socket_tx_free_out"
2627t "std_logic_vector"
2628b "(16 DOWNTO 0)"
2629eolc "-- 17bit value .. that's true"
2630posAdd 0
2631o 44
2632suid 109,0
2633)
2634)
2635)
2636]
2637shape (Rectangle
2638uid 234,0
2639va (VaSet
2640vasetType 1
2641fg "0,65535,0"
2642lineColor "0,32896,0"
2643lineWidth 2
2644)
2645xt "81000,19000,109000,91000"
2646)
2647oxt "15000,-8000,43000,46000"
2648ttg (MlTextGroup
2649uid 235,0
2650ps "CenterOffsetStrategy"
2651stg "VerticalLayoutStrategy"
2652textVec [
2653*66 (Text
2654uid 236,0
2655va (VaSet
2656font "Arial,8,1"
2657)
2658xt "83200,81000,89400,82000"
2659st "FACT_FAD_lib"
2660blo "83200,81800"
2661tm "BdLibraryNameMgr"
2662)
2663*67 (Text
2664uid 237,0
2665va (VaSet
2666font "Arial,8,1"
2667)
2668xt "83200,82000,87400,83000"
2669st "FAD_main"
2670blo "83200,82800"
2671tm "CptNameMgr"
2672)
2673*68 (Text
2674uid 238,0
2675va (VaSet
2676font "Arial,8,1"
2677)
2678xt "83200,83000,90000,84000"
2679st "I_mainTB_FPGA"
2680blo "83200,83800"
2681tm "InstanceNameMgr"
2682)
2683]
2684)
2685ga (GenericAssociation
2686uid 239,0
2687ps "EdgeToEdgeStrategy"
2688matrix (Matrix
2689uid 240,0
2690text (MLText
2691uid 241,0
2692va (VaSet
2693font "Courier New,8,0"
2694)
2695xt "81000,18200,101000,19000"
2696st "RAMADDRWIDTH64b = 15    ( integer )  "
2697)
2698header ""
2699)
2700elements [
2701(GiElement
2702name "RAMADDRWIDTH64b"
2703type "integer"
2704value "15"
2705)
2706]
2707)
2708viewicon (ZoomableIcon
2709uid 242,0
2710sl 0
2711va (VaSet
2712vasetType 1
2713fg "49152,49152,49152"
2714)
2715xt "81250,89250,82750,90750"
2716iconName "BlockDiagram.png"
2717iconMaskName "BlockDiagram.msk"
2718ftype 1
2719)
2720viewiconposition 0
2721portVis (PortSigDisplay
2722)
2723archFileType "UNKNOWN"
2724)
2725*69 (SaComponent
2726uid 274,0
2727optionalChildren [
2728*70 (CptPort
2729uid 266,0
2730ps "OnEdgeStrategy"
2731shape (Triangle
2732uid 267,0
2733ro 90
2734va (VaSet
2735vasetType 1
2736fg "0,65535,0"
2737)
2738xt "58000,20625,58750,21375"
2739)
2740tg (CPTG
2741uid 268,0
2742ps "CptPortTextPlaceStrategy"
2743stg "RightVerticalLayoutStrategy"
2744f (Text
2745uid 269,0
2746va (VaSet
2747)
2748xt "55700,20500,57000,21500"
2749st "clk"
2750ju 2
2751blo "57000,21300"
2752)
2753)
2754thePort (LogicalPort
2755m 1
2756decl (Decl
2757n "clk"
2758t "STD_LOGIC"
2759o 1
2760i "'0'"
2761)
2762)
2763)
2764*71 (CptPort
2765uid 270,0
2766ps "OnEdgeStrategy"
2767shape (Triangle
2768uid 271,0
2769ro 90
2770va (VaSet
2771vasetType 1
2772fg "0,65535,0"
2773)
2774xt "58000,21625,58750,22375"
2775)
2776tg (CPTG
2777uid 272,0
2778ps "CptPortTextPlaceStrategy"
2779stg "RightVerticalLayoutStrategy"
2780f (Text
2781uid 273,0
2782va (VaSet
2783)
2784xt "55700,21500,57000,22500"
2785st "rst"
2786ju 2
2787blo "57000,22300"
2788)
2789)
2790thePort (LogicalPort
2791m 1
2792decl (Decl
2793n "rst"
2794t "STD_LOGIC"
2795o 2
2796i "'0'"
2797)
2798)
2799)
2800]
2801shape (Rectangle
2802uid 275,0
2803va (VaSet
2804vasetType 1
2805fg "0,49152,49152"
2806lineColor "0,0,50000"
2807lineWidth 2
2808)
2809xt "50000,19000,58000,24000"
2810)
2811oxt "0,0,8000,10000"
2812ttg (MlTextGroup
2813uid 276,0
2814ps "CenterOffsetStrategy"
2815stg "VerticalLayoutStrategy"
2816textVec [
2817*72 (Text
2818uid 277,0
2819va (VaSet
2820font "Arial,8,1"
2821)
2822xt "50150,24000,57850,25000"
2823st "FACT_FAD_TB_lib"
2824blo "50150,24800"
2825tm "BdLibraryNameMgr"
2826)
2827*73 (Text
2828uid 278,0
2829va (VaSet
2830font "Arial,8,1"
2831)
2832xt "50150,25000,56850,26000"
2833st "clock_generator"
2834blo "50150,25800"
2835tm "CptNameMgr"
2836)
2837*74 (Text
2838uid 279,0
2839va (VaSet
2840font "Arial,8,1"
2841)
2842xt "50150,26000,56750,27000"
2843st "I_mainTB_clock"
2844blo "50150,26800"
2845tm "InstanceNameMgr"
2846)
2847]
2848)
2849ga (GenericAssociation
2850uid 280,0
2851ps "EdgeToEdgeStrategy"
2852matrix (Matrix
2853uid 281,0
2854text (MLText
2855uid 282,0
2856va (VaSet
2857font "Courier New,8,0"
2858)
2859xt "50000,17400,68500,19000"
2860st "clock_period = 20 ns    ( time ) 
2861reset_time   = 50 ns    ( time )  "
2862)
2863header ""
2864)
2865elements [
2866(GiElement
2867name "clock_period"
2868type "time"
2869value "20 ns"
2870)
2871(GiElement
2872name "reset_time"
2873type "time"
2874value "50 ns"
2875)
2876]
2877)
2878viewicon (ZoomableIcon
2879uid 283,0
2880sl 0
2881va (VaSet
2882vasetType 1
2883fg "49152,49152,49152"
2884)
2885xt "50250,22250,51750,23750"
2886iconName "VhdlFileViewIcon.png"
2887iconMaskName "VhdlFileViewIcon.msk"
2888ftype 10
2889)
2890ordering 1
2891viewiconposition 0
2892portVis (PortSigDisplay
2893)
2894archFileType "UNKNOWN"
2895)
2896*75 (Net
2897uid 284,0
2898decl (Decl
2899n "clk"
2900t "STD_LOGIC"
2901preAdd 0
2902posAdd 0
2903o 1
2904suid 1,0
2905)
2906declText (MLText
2907uid 285,0
2908va (VaSet
2909font "Courier New,8,0"
2910)
2911xt "-90000,46200,-68000,47000"
2912st "SIGNAL clk                   : STD_LOGIC
2913"
2914)
2915)
2916*76 (Net
2917uid 316,0
2918decl (Decl
2919n "wiz_addr"
2920t "std_logic_vector"
2921b "(9 DOWNTO 0)"
2922o 2
2923suid 2,0
2924)
2925declText (MLText
2926uid 317,0
2927va (VaSet
2928font "Courier New,8,0"
2929)
2930xt "-90000,63800,-58500,64600"
2931st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)
2932"
2933)
2934)
2935*77 (Net
2936uid 322,0
2937decl (Decl
2938n "wiz_data"
2939t "std_logic_vector"
2940b "(15 DOWNTO 0)"
2941o 3
2942suid 3,0
2943)
2944declText (MLText
2945uid 323,0
2946va (VaSet
2947font "Courier New,8,0"
2948)
2949xt "-90000,65400,-58000,66200"
2950st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)
2951"
2952)
2953)
2954*78 (Net
2955uid 328,0
2956decl (Decl
2957n "wiz_rd"
2958t "std_logic"
2959o 4
2960suid 4,0
2961i "'1'"
2962)
2963declText (MLText
2964uid 329,0
2965va (VaSet
2966font "Courier New,8,0"
2967)
2968xt "-90000,67000,-55000,67800"
2969st "SIGNAL wiz_rd                : std_logic                    := '1'
2970"
2971)
2972)
2973*79 (Net
2974uid 334,0
2975decl (Decl
2976n "wiz_wr"
2977t "std_logic"
2978o 5
2979suid 5,0
2980i "'1'"
2981)
2982declText (MLText
2983uid 335,0
2984va (VaSet
2985font "Courier New,8,0"
2986)
2987xt "-90000,68600,-55000,69400"
2988st "SIGNAL wiz_wr                : std_logic                    := '1'
2989"
2990)
2991)
2992*80 (SaComponent
2993uid 362,0
2994optionalChildren [
2995*81 (CptPort
2996uid 350,0
2997ps "OnEdgeStrategy"
2998shape (Triangle
2999uid 351,0
3000ro 90
3001va (VaSet
3002vasetType 1
3003fg "0,65535,0"
3004)
3005xt "122250,50625,123000,51375"
3006)
3007tg (CPTG
3008uid 352,0
3009ps "CptPortTextPlaceStrategy"
3010stg "VerticalLayoutStrategy"
3011f (Text
3012uid 353,0
3013va (VaSet
3014)
3015xt "124000,50500,125700,51500"
3016st "sclk"
3017blo "124000,51300"
3018)
3019)
3020thePort (LogicalPort
3021decl (Decl
3022n "sclk"
3023t "std_logic"
3024preAdd 0
3025posAdd 0
3026o 1
3027suid 1,0
3028)
3029)
3030)
3031*82 (CptPort
3032uid 354,0
3033ps "OnEdgeStrategy"
3034shape (Diamond
3035uid 355,0
3036ro 270
3037va (VaSet
3038vasetType 1
3039fg "0,65535,0"
3040)
3041xt "122250,51625,123000,52375"
3042)
3043tg (CPTG
3044uid 356,0
3045ps "CptPortTextPlaceStrategy"
3046stg "VerticalLayoutStrategy"
3047f (Text
3048uid 357,0
3049va (VaSet
3050)
3051xt "124000,51500,125400,52500"
3052st "sio"
3053blo "124000,52300"
3054)
3055)
3056thePort (LogicalPort
3057m 2
3058decl (Decl
3059n "sio"
3060t "std_logic"
3061preAdd 0
3062posAdd 0
3063o 2
3064suid 2,0
3065)
3066)
3067)
3068*83 (CptPort
3069uid 358,0
3070ps "OnEdgeStrategy"
3071shape (Triangle
3072uid 359,0
3073ro 90
3074va (VaSet
3075vasetType 1
3076fg "0,65535,0"
3077)
3078xt "122250,47625,123000,48375"
3079)
3080tg (CPTG
3081uid 360,0
3082ps "CptPortTextPlaceStrategy"
3083stg "VerticalLayoutStrategy"
3084f (Text
3085uid 361,0
3086va (VaSet
3087)
3088xt "124000,47500,130500,48500"
3089st "sensor_cs : (3:0)"
3090blo "124000,48300"
3091)
3092)
3093thePort (LogicalPort
3094decl (Decl
3095n "sensor_cs"
3096t "std_logic_vector"
3097b "(3 downto 0)"
3098preAdd 0
3099posAdd 0
3100o 3
3101suid 3,0
3102)
3103)
3104)
3105]
3106shape (Rectangle
3107uid 363,0
3108va (VaSet
3109vasetType 1
3110fg "0,49152,49152"
3111lineColor "0,0,50000"
3112lineWidth 2
3113)
3114xt "123000,46000,133000,56000"
3115)
3116oxt "30000,3000,40000,13000"
3117ttg (MlTextGroup
3118uid 364,0
3119ps "CenterOffsetStrategy"
3120stg "VerticalLayoutStrategy"
3121textVec [
3122*84 (Text
3123uid 365,0
3124va (VaSet
3125font "Arial,8,1"
3126)
3127xt "123200,56000,130900,57000"
3128st "FACT_FAD_TB_lib"
3129blo "123200,56800"
3130tm "BdLibraryNameMgr"
3131)
3132*85 (Text
3133uid 366,0
3134va (VaSet
3135font "Arial,8,1"
3136)
3137xt "123200,57000,130800,58000"
3138st "max6662_emulator"
3139blo "123200,57800"
3140tm "CptNameMgr"
3141)
3142*86 (Text
3143uid 367,0
3144va (VaSet
3145font "Arial,8,1"
3146)
3147xt "123200,58000,131000,59000"
3148st "I_mainTB_max6662"
3149blo "123200,58800"
3150tm "InstanceNameMgr"
3151)
3152]
3153)
3154ga (GenericAssociation
3155uid 368,0
3156ps "EdgeToEdgeStrategy"
3157matrix (Matrix
3158uid 369,0
3159text (MLText
3160uid 370,0
3161va (VaSet
3162font "Courier New,8,0"
3163)
3164xt "123000,45200,143000,46000"
3165st "DRS_TEMPERATURE = 51    ( integer )  "
3166)
3167header ""
3168)
3169elements [
3170(GiElement
3171name "DRS_TEMPERATURE"
3172type "integer"
3173value "51"
3174)
3175]
3176)
3177viewicon (ZoomableIcon
3178uid 371,0
3179sl 0
3180va (VaSet
3181vasetType 1
3182fg "49152,49152,49152"
3183)
3184xt "123250,54250,124750,55750"
3185iconName "VhdlFileViewIcon.png"
3186iconMaskName "VhdlFileViewIcon.msk"
3187ftype 10
3188)
3189ordering 1
3190viewiconposition 0
3191portVis (PortSigDisplay
3192sIVOD 1
3193)
3194archFileType "UNKNOWN"
3195)
3196*87 (Net
3197uid 372,0
3198decl (Decl
3199n "sensor_cs"
3200t "std_logic_vector"
3201b "(3 DOWNTO 0)"
3202o 6
3203suid 6,0
3204)
3205declText (MLText
3206uid 373,0
3207va (VaSet
3208font "Courier New,8,0"
3209)
3210xt "-90000,59000,-58500,59800"
3211st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)
3212"
3213)
3214)
3215*88 (Net
3216uid 378,0
3217decl (Decl
3218n "sclk"
3219t "std_logic"
3220o 7
3221suid 7,0
3222)
3223declText (MLText
3224uid 379,0
3225va (VaSet
3226font "Courier New,8,0"
3227)
3228xt "-90000,58200,-68000,59000"
3229st "SIGNAL sclk                  : std_logic
3230"
3231)
3232)
3233*89 (Net
3234uid 384,0
3235decl (Decl
3236n "sio"
3237t "std_logic"
3238preAdd 0
3239posAdd 0
3240o 8
3241suid 8,0
3242)
3243declText (MLText
3244uid 385,0
3245va (VaSet
3246font "Courier New,8,0"
3247)
3248xt "-90000,59800,-68000,60600"
3249st "SIGNAL sio                   : std_logic
3250"
3251)
3252)
3253*90 (SaComponent
3254uid 414,0
3255optionalChildren [
3256*91 (CptPort
3257uid 410,0
3258ps "OnEdgeStrategy"
3259shape (Triangle
3260uid 411,0
3261ro 90
3262va (VaSet
3263vasetType 1
3264fg "0,65535,0"
3265)
3266xt "58000,31625,58750,32375"
3267)
3268tg (CPTG
3269uid 412,0
3270ps "CptPortTextPlaceStrategy"
3271stg "RightVerticalLayoutStrategy"
3272f (Text
3273uid 413,0
3274va (VaSet
3275)
3276xt "54200,31500,57000,32500"
3277st "trigger"
3278ju 2
3279blo "57000,32300"
3280)
3281)
3282thePort (LogicalPort
3283m 1
3284decl (Decl
3285n "trigger"
3286t "std_logic"
3287preAdd 0
3288posAdd 0
3289o 1
3290suid 1,0
3291)
3292)
3293)
3294]
3295shape (Rectangle
3296uid 415,0
3297va (VaSet
3298vasetType 1
3299fg "0,49152,49152"
3300lineColor "0,0,50000"
3301lineWidth 2
3302)
3303xt "50000,30000,58000,36000"
3304)
3305oxt "19000,4000,29000,14000"
3306ttg (MlTextGroup
3307uid 416,0
3308ps "CenterOffsetStrategy"
3309stg "VerticalLayoutStrategy"
3310textVec [
3311*92 (Text
3312uid 417,0
3313va (VaSet
3314font "Arial,8,1"
3315)
3316xt "50200,36000,57900,37000"
3317st "FACT_FAD_TB_lib"
3318blo "50200,36800"
3319tm "BdLibraryNameMgr"
3320)
3321*93 (Text
3322uid 418,0
3323va (VaSet
3324font "Arial,8,1"
3325)
3326xt "50200,37000,57500,38000"
3327st "trigger_generator"
3328blo "50200,37800"
3329tm "CptNameMgr"
3330)
3331*94 (Text
3332uid 419,0
3333va (VaSet
3334font "Arial,8,1"
3335)
3336xt "50200,38000,57400,39000"
3337st "I_mainTB_trigger"
3338blo "50200,38800"
3339tm "InstanceNameMgr"
3340)
3341]
3342)
3343ga (GenericAssociation
3344uid 420,0
3345ps "EdgeToEdgeStrategy"
3346matrix (Matrix
3347uid 421,0
3348text (MLText
3349uid 422,0
3350va (VaSet
3351font "Courier New,8,0"
3352)
3353xt "50000,28400,68500,30000"
3354st "TRIGGER_RATE = 1 ms     ( time ) 
3355PULSE_WIDTH  = 20 ns    ( time )  "
3356)
3357header ""
3358)
3359elements [
3360(GiElement
3361name "TRIGGER_RATE"
3362type "time"
3363value "1 ms"
3364)
3365(GiElement
3366name "PULSE_WIDTH"
3367type "time"
3368value "20 ns"
3369)
3370]
3371)
3372viewicon (ZoomableIcon
3373uid 423,0
3374sl 0
3375va (VaSet
3376vasetType 1
3377fg "49152,49152,49152"
3378)
3379xt "50250,34250,51750,35750"
3380iconName "VhdlFileViewIcon.png"
3381iconMaskName "VhdlFileViewIcon.msk"
3382ftype 10
3383)
3384ordering 1
3385viewiconposition 0
3386portVis (PortSigDisplay
3387sIVOD 1
3388)
3389archFileType "UNKNOWN"
3390)
3391*95 (Net
3392uid 424,0
3393decl (Decl
3394n "trigger"
3395t "std_logic"
3396preAdd 0
3397posAdd 0
3398o 9
3399suid 9,0
3400)
3401declText (MLText
3402uid 425,0
3403va (VaSet
3404font "Courier New,8,0"
3405)
3406xt "-90000,61400,-68000,62200"
3407st "SIGNAL trigger               : std_logic
3408"
3409)
3410)
3411*96 (HdlText
3412uid 430,0
3413optionalChildren [
3414*97 (EmbeddedText
3415uid 436,0
3416commentText (CommentText
3417uid 437,0
3418ps "CenterOffsetStrategy"
3419shape (Rectangle
3420uid 438,0
3421va (VaSet
3422vasetType 1
3423fg "65535,65535,65535"
3424lineColor "0,0,32768"
3425lineWidth 2
3426)
3427xt "50000,45000,60000,49000"
3428)
3429oxt "0,0,18000,5000"
3430text (MLText
3431uid 439,0
3432va (VaSet
3433)
3434xt "50200,45200,60200,48200"
3435st "
3436-- eb_ID 1: hard-wired IDs
3437board_id <= \"0101\";
3438crate_id <= \"01\";
3439
3440"
3441tm "HdlTextMgr"
3442wrapOption 3
3443visibleHeight 4000
3444visibleWidth 10000
3445)
3446)
3447)
3448]
3449shape (Rectangle
3450uid 431,0
3451va (VaSet
3452vasetType 1
3453fg "65535,65535,37120"
3454lineColor "0,0,32768"
3455lineWidth 2
3456)
3457xt "50000,40000,58000,45000"
3458)
3459oxt "0,0,8000,10000"
3460ttg (MlTextGroup
3461uid 432,0
3462ps "CenterOffsetStrategy"
3463stg "VerticalLayoutStrategy"
3464textVec [
3465*98 (Text
3466uid 433,0
3467va (VaSet
3468font "Arial,8,1"
3469)
3470xt "51150,41000,57350,42000"
3471st "eb_mainTB_ID"
3472blo "51150,41800"
3473tm "HdlTextNameMgr"
3474)
3475*99 (Text
3476uid 434,0
3477va (VaSet
3478font "Arial,8,1"
3479)
3480xt "51150,42000,51950,43000"
3481st "1"
3482blo "51150,42800"
3483tm "HdlTextNumberMgr"
3484)
3485]
3486)
3487viewicon (ZoomableIcon
3488uid 435,0
3489sl 0
3490va (VaSet
3491vasetType 1
3492fg "49152,49152,49152"
3493)
3494xt "50250,43250,51750,44750"
3495iconName "TextFile.png"
3496iconMaskName "TextFile.msk"
3497ftype 21
3498)
3499viewiconposition 0
3500)
3501*100 (Net
3502uid 440,0
3503decl (Decl
3504n "board_id"
3505t "std_logic_vector"
3506b "(3 downto 0)"
3507preAdd 0
3508posAdd 0
3509o 10
3510suid 10,0
3511)
3512declText (MLText
3513uid 441,0
3514va (VaSet
3515font "Courier New,8,0"
3516)
3517xt "-90000,45400,-58500,46200"
3518st "SIGNAL board_id              : std_logic_vector(3 downto 0)
3519"
3520)
3521)
3522*101 (Net
3523uid 448,0
3524decl (Decl
3525n "crate_id"
3526t "std_logic_vector"
3527b "(1 downto 0)"
3528o 11
3529suid 11,0
3530)
3531declText (MLText
3532uid 449,0
3533va (VaSet
3534font "Courier New,8,0"
3535)
3536xt "-90000,47800,-58500,48600"
3537st "SIGNAL crate_id              : std_logic_vector(1 downto 0)
3538"
3539)
3540)
3541*102 (SaComponent
3542uid 508,0
3543optionalChildren [
3544*103 (CptPort
3545uid 489,0
3546ps "OnEdgeStrategy"
3547shape (Triangle
3548uid 490,0
3549ro 90
3550va (VaSet
3551vasetType 1
3552fg "0,65535,0"
3553)
3554xt "29250,52625,30000,53375"
3555)
3556tg (CPTG
3557uid 491,0
3558ps "CptPortTextPlaceStrategy"
3559stg "VerticalLayoutStrategy"
3560f (Text
3561uid 492,0
3562va (VaSet
3563)
3564xt "31000,52500,32300,53500"
3565st "clk"
3566blo "31000,53300"
3567)
3568)
3569thePort (LogicalPort
3570decl (Decl
3571n "clk"
3572t "STD_LOGIC"
3573preAdd 0
3574posAdd 0
3575o 1
3576suid 1,0
3577)
3578)
3579)
3580*104 (CptPort
3581uid 493,0
3582ps "OnEdgeStrategy"
3583shape (Triangle
3584uid 494,0
3585ro 90
3586va (VaSet
3587vasetType 1
3588fg "0,65535,0"
3589)
3590xt "40000,54625,40750,55375"
3591)
3592tg (CPTG
3593uid 495,0
3594ps "CptPortTextPlaceStrategy"
3595stg "RightVerticalLayoutStrategy"
3596f (Text
3597uid 496,0
3598va (VaSet
3599)
3600xt "34200,54500,39000,55500"
3601st "data : (11:0)"
3602ju 2
3603blo "39000,55300"
3604)
3605)
3606thePort (LogicalPort
3607m 1
3608decl (Decl
3609n "data"
3610t "STD_LOGIC_VECTOR"
3611b "(11 DOWNTO 0)"
3612preAdd 0
3613posAdd 0
3614o 2
3615suid 2,0
3616)
3617)
3618)
3619*105 (CptPort
3620uid 497,0
3621ps "OnEdgeStrategy"
3622shape (Triangle
3623uid 498,0
3624ro 90
3625va (VaSet
3626vasetType 1
3627fg "0,65535,0"
3628)
3629xt "40000,52625,40750,53375"
3630)
3631tg (CPTG
3632uid 499,0
3633ps "CptPortTextPlaceStrategy"
3634stg "RightVerticalLayoutStrategy"
3635f (Text
3636uid 500,0
3637va (VaSet
3638)
3639xt "37700,52500,39000,53500"
3640st "otr"
3641ju 2
3642blo "39000,53300"
3643)
3644)
3645thePort (LogicalPort
3646m 1
3647decl (Decl
3648n "otr"
3649t "STD_LOGIC"
3650preAdd 0
3651posAdd 0
3652o 3
3653suid 3,0
3654)
3655)
3656)
3657*106 (CptPort
3658uid 501,0
3659ps "OnEdgeStrategy"
3660shape (Triangle
3661uid 502,0
3662ro 270
3663va (VaSet
3664vasetType 1
3665fg "0,65535,0"
3666)
3667xt "40000,53625,40750,54375"
3668)
3669tg (CPTG
3670uid 503,0
3671ps "CptPortTextPlaceStrategy"
3672stg "RightVerticalLayoutStrategy"
3673f (Text
3674uid 504,0
3675va (VaSet
3676)
3677xt "37400,53500,39000,54500"
3678st "oeb"
3679ju 2
3680blo "39000,54300"
3681)
3682)
3683thePort (LogicalPort
3684decl (Decl
3685n "oeb"
3686t "STD_LOGIC"
3687preAdd 0
3688posAdd 0
3689o 4
3690suid 4,0
3691)
3692)
3693)
3694]
3695shape (Rectangle
3696uid 509,0
3697va (VaSet
3698vasetType 1
3699fg "0,49152,49152"
3700lineColor "0,0,50000"
3701lineWidth 2
3702)
3703xt "30000,51000,40000,58000"
3704)
3705oxt "29000,7000,39000,17000"
3706ttg (MlTextGroup
3707uid 510,0
3708ps "CenterOffsetStrategy"
3709stg "VerticalLayoutStrategy"
3710textVec [
3711*107 (Text
3712uid 511,0
3713va (VaSet
3714font "Arial,8,1"
3715)
3716xt "30200,58000,37900,59000"
3717st "FACT_FAD_TB_lib"
3718blo "30200,58800"
3719tm "BdLibraryNameMgr"
3720)
3721*108 (Text
3722uid 512,0
3723va (VaSet
3724font "Arial,8,1"
3725)
3726xt "30200,59000,36000,60000"
3727st "adc_emulator"
3728blo "30200,59800"
3729tm "CptNameMgr"
3730)
3731*109 (Text
3732uid 513,0
3733va (VaSet
3734font "Arial,8,1"
3735)
3736xt "30200,60000,36200,61000"
3737st "I_mainTB_adc"
3738blo "30200,60800"
3739tm "InstanceNameMgr"
3740)
3741]
3742)
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3810-- eb_adc 2: ADC routing
3811adc_data_array(0) <= adc_data;
3812adc_data_array(1) <= adc_data;
3813adc_data_array(2) <= adc_data;
3814adc_data_array(3) <= adc_data;
3815adc_otr_array(0) <= adc_otr;
3816adc_otr_array(1) <= adc_otr;
3817adc_otr_array(2) <= adc_otr;
3818adc_otr_array(3) <= adc_otr;
3819
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3821tm "HdlTextMgr"
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3900*115 (Net
3901uid 536,0
3902decl (Decl
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3919uid 544,0
3920decl (Decl
3921n "adc_oeb"
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3936)
3937)
3938*117 (Net
3939uid 560,0
3940decl (Decl
3941n "adc_otr"
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3956)
3957)
3958*118 (Net
3959uid 568,0
3960decl (Decl
3961n "adc_data"
3962t "std_logic_vector"
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3995"
3996)
3997)
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3999uid 775,0
4000decl (Decl
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4017)
4018)
4019*121 (Net
4020uid 783,0
4021decl (Decl
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4035"
4036)
4037)
4038*122 (Net
4039uid 791,0
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4072)
4073)
4074*124 (Net
4075uid 807,0
4076decl (Decl
4077n "mosi"
4078t "std_logic"
4079o 26
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4090"
4091)
4092)
4093*125 (Net
4094uid 815,0
4095decl (Decl
4096n "denable"
4097t "std_logic"
4098eolc "-- default domino wave off"
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4100o 27
4101suid 29,0
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4111"
4112)
4113)
4114*126 (Net
4115uid 823,0
4116decl (Decl
4117n "CLK_25_PS"
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4129"
4130)
4131)
4132*127 (Net
4133uid 831,0
4134decl (Decl
4135n "CLK_50"
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4148)
4149)
4150*128 (Net
4151uid 839,0
4152decl (Decl
4153n "drs_channel_id"
4154t "std_logic_vector"
4155b "(3 downto 0)"
4156o 30
4157suid 32,0
4158i "(others => '0')"
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4167"
4168)
4169)
4170*129 (Net
4171uid 847,0
4172decl (Decl
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4175o 31
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4182font "Courier New,8,0"
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4185st "SIGNAL drs_dwrite            : std_logic                    := '1'
4186"
4187)
4188)
4189*130 (Net
4190uid 855,0
4191decl (Decl
4192n "RSRLOAD"
4193t "std_logic"
4194o 32
4195suid 34,0
4196i "'0'"
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4200va (VaSet
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4204st "SIGNAL RSRLOAD               : std_logic                    := '0'
4205"
4206)
4207)
4208*131 (Net
4209uid 863,0
4210decl (Decl
4211n "SRCLK"
4212t "std_logic"
4213o 33
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4224"
4225)
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4227*132 (Net
4228uid 871,0
4229decl (Decl
4230n "SROUT_in_0"
4231t "std_logic"
4232o 30
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4242"
4243)
4244)
4245*133 (Net
4246uid 879,0
4247decl (Decl
4248n "SROUT_in_1"
4249t "std_logic"
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4260"
4261)
4262)
4263*134 (Net
4264uid 887,0
4265decl (Decl
4266n "SROUT_in_2"
4267t "std_logic"
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4279)
4280)
4281*135 (Net
4282uid 895,0
4283decl (Decl
4284n "SROUT_in_3"
4285t "std_logic"
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4297)
4298)
4299*136 (Net
4300uid 1435,0
4301decl (Decl
4302n "SRIN_out"
4303t "std_logic"
4304o 34
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4306i "'0'"
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4310va (VaSet
4311font "Courier New,8,0"
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4313xt "-90000,35000,-55000,35800"
4314st "SIGNAL SRIN_out              : std_logic                    := '0'
4315"
4316)
4317)
4318*137 (Net
4319uid 1443,0
4320decl (Decl
4321n "amber"
4322t "std_logic"
4323o 35
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4329font "Courier New,8,0"
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4332st "SIGNAL amber                 : std_logic
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4334)
4335)
4336*138 (Net
4337uid 1451,0
4338decl (Decl
4339n "red"
4340t "std_logic"
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4347font "Courier New,8,0"
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4350st "SIGNAL red                   : std_logic
4351"
4352)
4353)
4354*139 (Net
4355uid 1459,0
4356decl (Decl
4357n "green"
4358t "std_logic"
4359o 37
4360suid 43,0
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4364va (VaSet
4365font "Courier New,8,0"
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4368st "SIGNAL green                 : std_logic
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4370)
4371)
4372*140 (Net
4373uid 1467,0
4374decl (Decl
4375n "counter_result"
4376t "std_logic_vector"
4377b "(11 DOWNTO 0)"
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4389)
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4391*141 (Net
4392uid 1475,0
4393decl (Decl
4394n "alarm_refclk_too_low"
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4413n "alarm_refclk_too_high"
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4444xt "27000,72000,41000,77000"
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4448uid 1500,0
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4451xt "27200,72200,39400,77200"
4452st "
4453
4454D_T_in(1 downto 0) <= \"00\";
4455plllock_in(3 downto 0) <= \"1111\";
4456SROUT_in_0 <= '1';
4457SROUT_in_1 <= '0';
4458SROUT_in_2 <= '1';
4459SROUT_in_3 <= '0';
4460
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4462tm "HdlTextMgr"
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4480oxt "0,0,8000,10000"
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4491xt "28150,69000,35250,70000"
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4504tm "HdlTextNumberMgr"
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4520viewiconposition 0
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4523uid 1501,0
4524decl (Decl
4525n "D_T_in"
4526t "std_logic_vector"
4527b "(1 DOWNTO 0)"
4528o 41
4529suid 47,0
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4536xt "-90000,28600,-58500,29400"
4537st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)
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4539)
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4543optionalChildren [
4544*149 (CptPort
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4547shape (Triangle
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4549ro 90
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4551vasetType 1
4552fg "0,65535,0"
4553)
4554xt "66000,78625,66750,79375"
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4556tg (CPTG
4557uid 1521,0
4558ps "CptPortTextPlaceStrategy"
4559stg "RightVerticalLayoutStrategy"
4560f (Text
4561uid 1522,0
4562va (VaSet
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4564xt "63700,78500,65000,79500"
4565st "clk"
4566ju 2
4567blo "65000,79300"
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4569)
4570thePort (LogicalPort
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4572decl (Decl
4573n "clk"
4574t "STD_LOGIC"
4575o 1
4576i "'0'"
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4580*150 (CptPort
4581uid 1523,0
4582ps "OnEdgeStrategy"
4583shape (Triangle
4584uid 1524,0
4585ro 90
4586va (VaSet
4587vasetType 1
4588fg "0,65535,0"
4589)
4590xt "66000,79625,66750,80375"
4591)
4592tg (CPTG
4593uid 1525,0
4594ps "CptPortTextPlaceStrategy"
4595stg "RightVerticalLayoutStrategy"
4596f (Text
4597uid 1526,0
4598va (VaSet
4599)
4600xt "63700,79500,65000,80500"
4601st "rst"
4602ju 2
4603blo "65000,80300"
4604)
4605)
4606thePort (LogicalPort
4607m 1
4608decl (Decl
4609n "rst"
4610t "STD_LOGIC"
4611o 2
4612i "'0'"
4613)
4614)
4615)
4616]
4617shape (Rectangle
4618uid 1510,0
4619va (VaSet
4620vasetType 1
4621fg "0,49152,49152"
4622lineColor "0,0,50000"
4623lineWidth 2
4624)
4625xt "55000,77000,66000,82000"
4626)
4627oxt "0,0,8000,10000"
4628ttg (MlTextGroup
4629uid 1511,0
4630ps "CenterOffsetStrategy"
4631stg "VerticalLayoutStrategy"
4632textVec [
4633*151 (Text
4634uid 1512,0
4635va (VaSet
4636font "Arial,8,1"
4637)
4638xt "56150,78000,63850,79000"
4639st "FACT_FAD_TB_lib"
4640blo "56150,78800"
4641tm "BdLibraryNameMgr"
4642)
4643*152 (Text
4644uid 1513,0
4645va (VaSet
4646font "Arial,8,1"
4647)
4648xt "56150,79000,62850,80000"
4649st "clock_generator"
4650blo "56150,79800"
4651tm "CptNameMgr"
4652)
4653*153 (Text
4654uid 1514,0
4655va (VaSet
4656font "Arial,8,1"
4657)
4658xt "56150,80000,63150,81000"
4659st "I_mainTB_clock1"
4660blo "56150,80800"
4661tm "InstanceNameMgr"
4662)
4663]
4664)
4665ga (GenericAssociation
4666uid 1515,0
4667ps "EdgeToEdgeStrategy"
4668matrix (Matrix
4669uid 1516,0
4670text (MLText
4671uid 1517,0
4672va (VaSet
4673font "Courier New,8,0"
4674)
4675xt "55000,82400,73000,84000"
4676st "clock_period = 1 us    ( time ) 
4677reset_time   = 1 us    ( time )  "
4678)
4679header ""
4680)
4681elements [
4682(GiElement
4683name "clock_period"
4684type "time"
4685value "1 us"
4686)
4687(GiElement
4688name "reset_time"
4689type "time"
4690value "1 us"
4691)
4692]
4693)
4694viewicon (ZoomableIcon
4695uid 1518,0
4696sl 0
4697va (VaSet
4698vasetType 1
4699fg "49152,49152,49152"
4700)
4701xt "55250,80250,56750,81750"
4702iconName "VhdlFileViewIcon.png"
4703iconMaskName "VhdlFileViewIcon.msk"
4704ftype 10
4705)
4706ordering 1
4707viewiconposition 0
4708portVis (PortSigDisplay
4709)
4710archFileType "UNKNOWN"
4711)
4712*154 (Net
4713uid 1559,0
4714decl (Decl
4715n "plllock_in"
4716t "std_logic_vector"
4717b "(3 DOWNTO 0)"
4718eolc "-- high level, if dominowave is running and DRS PLL locked"
4719o 43
4720suid 49,0
4721)
4722declText (MLText
4723uid 1560,0
4724va (VaSet
4725font "Courier New,8,0"
4726)
4727xt "-90000,56600,-29000,57400"
4728st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
4729"
4730)
4731)
4732*155 (Net
4733uid 1682,0
4734lang 2
4735decl (Decl
4736n "ADC_CLK"
4737t "std_logic"
4738o 44
4739suid 50,0
4740)
4741declText (MLText
4742uid 1683,0
4743va (VaSet
4744font "Courier New,8,0"
4745)
4746xt "-90000,24600,-68000,25400"
4747st "SIGNAL ADC_CLK               : std_logic
4748"
4749)
4750)
4751*156 (Net
4752uid 2001,0
4753decl (Decl
4754n "REF_CLK"
4755t "STD_LOGIC"
4756o 42
4757suid 51,0
4758i "'0'"
4759)
4760declText (MLText
4761uid 2002,0
4762va (VaSet
4763font "Courier New,8,0"
4764)
4765xt "-90000,32600,-55000,33400"
4766st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'
4767"
4768)
4769)
4770*157 (SaComponent
4771uid 2336,0
4772optionalChildren [
4773*158 (CptPort
4774uid 2315,0
4775ps "OnEdgeStrategy"
4776shape (Triangle
4777uid 2316,0
4778ro 90
4779va (VaSet
4780vasetType 1
4781fg "0,65535,0"
4782)
4783xt "122250,20625,123000,21375"
4784)
4785tg (CPTG
4786uid 2317,0
4787ps "CptPortTextPlaceStrategy"
4788stg "VerticalLayoutStrategy"
4789f (Text
4790uid 2318,0
4791va (VaSet
4792)
4793xt "124000,20500,129100,21500"
4794st "addr : (9:0)"
4795blo "124000,21300"
4796)
4797)
4798thePort (LogicalPort
4799decl (Decl
4800n "addr"
4801t "std_logic_vector"
4802b "(9 DOWNTO 0)"
4803preAdd 0
4804posAdd 0
4805o 2
4806suid 1,0
4807)
4808)
4809)
4810*159 (CptPort
4811uid 2319,0
4812ps "OnEdgeStrategy"
4813shape (Diamond
4814uid 2320,0
4815ro 270
4816va (VaSet
4817vasetType 1
4818fg "0,65535,0"
4819)
4820xt "122250,21625,123000,22375"
4821)
4822tg (CPTG
4823uid 2321,0
4824ps "CptPortTextPlaceStrategy"
4825stg "VerticalLayoutStrategy"
4826f (Text
4827uid 2322,0
4828va (VaSet
4829)
4830xt "124000,21500,129400,22500"
4831st "data : (15:0)"
4832blo "124000,22300"
4833)
4834)
4835thePort (LogicalPort
4836m 2
4837decl (Decl
4838n "data"
4839t "std_logic_vector"
4840b "(15 DOWNTO 0)"
4841preAdd 0
4842posAdd 0
4843o 3
4844suid 2,0
4845)
4846)
4847)
4848*160 (CptPort
4849uid 2323,0
4850ps "OnEdgeStrategy"
4851shape (Triangle
4852uid 2324,0
4853ro 90
4854va (VaSet
4855vasetType 1
4856fg "0,65535,0"
4857)
4858xt "122250,24625,123000,25375"
4859)
4860tg (CPTG
4861uid 2325,0
4862ps "CptPortTextPlaceStrategy"
4863stg "VerticalLayoutStrategy"
4864f (Text
4865uid 2326,0
4866va (VaSet
4867)
4868xt "124000,24500,125300,25500"
4869st "rd"
4870blo "124000,25300"
4871)
4872)
4873thePort (LogicalPort
4874decl (Decl
4875n "rd"
4876t "std_logic"
4877preAdd 0
4878posAdd 0
4879o 4
4880suid 3,0
4881)
4882)
4883)
4884*161 (CptPort
4885uid 2327,0
4886ps "OnEdgeStrategy"
4887shape (Triangle
4888uid 2328,0
4889ro 90
4890va (VaSet
4891vasetType 1
4892fg "0,65535,0"
4893)
4894xt "122250,25625,123000,26375"
4895)
4896tg (CPTG
4897uid 2329,0
4898ps "CptPortTextPlaceStrategy"
4899stg "VerticalLayoutStrategy"
4900f (Text
4901uid 2330,0
4902va (VaSet
4903)
4904xt "124000,25500,125400,26500"
4905st "wr"
4906blo "124000,26300"
4907)
4908)
4909thePort (LogicalPort
4910decl (Decl
4911n "wr"
4912t "std_logic"
4913preAdd 0
4914posAdd 0
4915o 6
4916suid 4,0
4917)
4918)
4919)
4920*162 (CptPort
4921uid 2331,0
4922ps "OnEdgeStrategy"
4923shape (Triangle
4924uid 2332,0
4925ro 270
4926va (VaSet
4927vasetType 1
4928fg "0,65535,0"
4929)
4930xt "122250,26625,123000,27375"
4931)
4932tg (CPTG
4933uid 2333,0
4934ps "CptPortTextPlaceStrategy"
4935stg "VerticalLayoutStrategy"
4936f (Text
4937uid 2334,0
4938va (VaSet
4939)
4940xt "124000,26500,125400,27500"
4941st "int"
4942blo "124000,27300"
4943)
4944)
4945thePort (LogicalPort
4946m 1
4947decl (Decl
4948n "int"
4949t "std_logic"
4950o 1
4951suid 5,0
4952i "'1'"
4953)
4954)
4955)
4956*163 (CptPort
4957uid 2548,0
4958ps "OnEdgeStrategy"
4959shape (Triangle
4960uid 2549,0
4961ro 90
4962va (VaSet
4963vasetType 1
4964fg "0,65535,0"
4965)
4966xt "122250,27625,123000,28375"
4967)
4968tg (CPTG
4969uid 2550,0
4970ps "CptPortTextPlaceStrategy"
4971stg "VerticalLayoutStrategy"
4972f (Text
4973uid 2551,0
4974va (VaSet
4975)
4976xt "124000,27500,125200,28500"
4977st "cs"
4978blo "124000,28300"
4979)
4980)
4981thePort (LogicalPort
4982decl (Decl
4983n "cs"
4984t "std_logic"
4985o 5
4986suid 6,0
4987)
4988)
4989)
4990]
4991shape (Rectangle
4992uid 2337,0
4993va (VaSet
4994vasetType 1
4995fg "0,49152,49152"
4996lineColor "0,0,50000"
4997lineWidth 2
4998)
4999xt "123000,19000,133000,31000"
5000)
5001oxt "29000,0,39000,12000"
5002ttg (MlTextGroup
5003uid 2338,0
5004ps "CenterOffsetStrategy"
5005stg "VerticalLayoutStrategy"
5006textVec [
5007*164 (Text
5008uid 2339,0
5009va (VaSet
5010font "Arial,8,1"
5011)
5012xt "123200,31000,130900,32000"
5013st "FACT_FAD_TB_lib"
5014blo "123200,31800"
5015tm "BdLibraryNameMgr"
5016)
5017*165 (Text
5018uid 2340,0
5019va (VaSet
5020font "Arial,8,1"
5021)
5022xt "123200,32000,129800,33000"
5023st "w5300_emulator"
5024blo "123200,32800"
5025tm "CptNameMgr"
5026)
5027*166 (Text
5028uid 2341,0
5029va (VaSet
5030font "Arial,8,1"
5031)
5032xt "123200,33000,130000,34000"
5033st "I_mainTB_w5300"
5034blo "123200,33800"
5035tm "InstanceNameMgr"
5036)
5037]
5038)
5039ga (GenericAssociation
5040uid 2342,0
5041ps "EdgeToEdgeStrategy"
5042matrix (Matrix
5043uid 2343,0
5044text (MLText
5045uid 2344,0
5046va (VaSet
5047font "Courier New,8,0"
5048)
5049xt "123000,18000,123000,18000"
5050)
5051header ""
5052)
5053elements [
5054]
5055)
5056viewicon (ZoomableIcon
5057uid 2345,0
5058sl 0
5059va (VaSet
5060vasetType 1
5061fg "49152,49152,49152"
5062)
5063xt "123250,29250,124750,30750"
5064iconName "VhdlFileViewIcon.png"
5065iconMaskName "VhdlFileViewIcon.msk"
5066ftype 10
5067)
5068ordering 1
5069viewiconposition 0
5070portVis (PortSigDisplay
5071)
5072archFileType "UNKNOWN"
5073)
5074*167 (Net
5075uid 2705,0
5076decl (Decl
5077n "debug_data_ram_empty"
5078t "std_logic"
5079o 45
5080suid 53,0
5081)
5082declText (MLText
5083uid 2706,0
5084va (VaSet
5085font "Courier New,8,0"
5086)
5087xt "-90000,49400,-68000,50200"
5088st "SIGNAL debug_data_ram_empty  : std_logic
5089"
5090)
5091)
5092*168 (Net
5093uid 2713,0
5094decl (Decl
5095n "debug_data_valid"
5096t "std_logic"
5097o 46
5098suid 54,0
5099)
5100declText (MLText
5101uid 2714,0
5102va (VaSet
5103font "Courier New,8,0"
5104)
5105xt "-90000,50200,-68000,51000"
5106st "SIGNAL debug_data_valid      : std_logic
5107"
5108)
5109)
5110*169 (Net
5111uid 2721,0
5112decl (Decl
5113n "DG_state"
5114t "std_logic_vector"
5115b "(7 downto 0)"
5116prec "-- for debugging"
5117preAdd 0
5118o 47
5119suid 55,0
5120)
5121declText (MLText
5122uid 2722,0
5123va (VaSet
5124font "Courier New,8,0"
5125)
5126xt "-90000,27000,-58500,28600"
5127st "-- for debugging
5128SIGNAL DG_state              : std_logic_vector(7 downto 0)
5129"
5130)
5131)
5132*170 (Net
5133uid 2729,0
5134decl (Decl
5135n "FTM_RS485_rx_en"
5136t "std_logic"
5137o 48
5138suid 56,0
5139)
5140declText (MLText
5141uid 2730,0
5142va (VaSet
5143font "Courier New,8,0"
5144)
5145xt "-90000,30200,-68000,31000"
5146st "SIGNAL FTM_RS485_rx_en       : std_logic
5147"
5148)
5149)
5150*171 (Net
5151uid 2737,0
5152decl (Decl
5153n "FTM_RS485_tx_d"
5154t "std_logic"
5155o 49
5156suid 57,0
5157)
5158declText (MLText
5159uid 2738,0
5160va (VaSet
5161font "Courier New,8,0"
5162)
5163xt "-90000,31000,-68000,31800"
5164st "SIGNAL FTM_RS485_tx_d        : std_logic
5165"
5166)
5167)
5168*172 (Net
5169uid 2745,0
5170decl (Decl
5171n "FTM_RS485_tx_en"
5172t "std_logic"
5173o 50
5174suid 58,0
5175)
5176declText (MLText
5177uid 2746,0
5178va (VaSet
5179font "Courier New,8,0"
5180)
5181xt "-90000,31800,-68000,32600"
5182st "SIGNAL FTM_RS485_tx_en       : std_logic
5183"
5184)
5185)
5186*173 (Net
5187uid 2753,0
5188lang 2
5189decl (Decl
5190n "mem_manager_state"
5191t "std_logic_vector"
5192b "(3 DOWNTO 0)"
5193eolc "-- state is encoded here ... useful for debugging."
5194posAdd 0
5195o 51
5196suid 59,0
5197)
5198declText (MLText
5199uid 2754,0
5200va (VaSet
5201font "Courier New,8,0"
5202)
5203xt "-90000,55000,-33000,55800"
5204st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
5205"
5206)
5207)
5208*174 (Net
5209uid 2761,0
5210decl (Decl
5211n "trigger_veto"
5212t "std_logic"
5213o 52
5214suid 60,0
5215i "'1'"
5216)
5217declText (MLText
5218uid 2762,0
5219va (VaSet
5220font "Courier New,8,0"
5221)
5222xt "-90000,62200,-55000,63000"
5223st "SIGNAL trigger_veto          : std_logic                    := '1'
5224"
5225)
5226)
5227*175 (Net
5228uid 2769,0
5229decl (Decl
5230n "w5300_state"
5231t "std_logic_vector"
5232b "(7 DOWNTO 0)"
5233eolc "-- state is encoded here ... useful for debugging."
5234posAdd 0
5235o 53
5236suid 61,0
5237)
5238declText (MLText
5239uid 2770,0
5240va (VaSet
5241font "Courier New,8,0"
5242)
5243xt "-90000,63000,-33000,63800"
5244st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
5245"
5246)
5247)
5248*176 (Net
5249uid 2777,0
5250decl (Decl
5251n "FTM_RS485_rx_d"
5252t "std_logic"
5253o 54
5254suid 62,0
5255)
5256declText (MLText
5257uid 2778,0
5258va (VaSet
5259font "Courier New,8,0"
5260)
5261xt "-90000,29400,-68000,30200"
5262st "SIGNAL FTM_RS485_rx_d        : std_logic
5263"
5264)
5265)
5266*177 (Net
5267uid 2942,0
5268decl (Decl
5269n "socket_tx_free_out"
5270t "std_logic_vector"
5271b "(16 DOWNTO 0)"
5272eolc "-- 17bit value .. that's true"
5273posAdd 0
5274o 55
5275suid 64,0
5276)
5277declText (MLText
5278uid 2943,0
5279va (VaSet
5280font "Courier New,8,0"
5281)
5282xt "-90000,60600,-43000,61400"
5283st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true
5284"
5285)
5286)
5287*178 (Wire
5288uid 286,0
5289shape (OrthoPolyLine
5290uid 287,0
5291va (VaSet
5292vasetType 3
5293)
5294xt "58750,21000,80250,21000"
5295pts [
5296"58750,21000"
5297"80250,21000"
5298]
5299)
5300start &70
5301end &27
5302sat 32
5303eat 32
5304st 0
5305sf 1
5306si 0
5307tg (WTG
5308uid 288,0
5309ps "ConnStartEndStrategy"
5310stg "STSignalDisplayStrategy"
5311f (Text
5312uid 289,0
5313va (VaSet
5314)
5315xt "71000,20000,72300,21000"
5316st "clk"
5317blo "71000,20800"
5318tm "WireNameMgr"
5319)
5320)
5321on &75
5322)
5323*179 (Wire
5324uid 318,0
5325shape (OrthoPolyLine
5326uid 319,0
5327va (VaSet
5328vasetType 3
5329lineWidth 2
5330)
5331xt "109750,21000,122250,21000"
5332pts [
5333"109750,21000"
5334"122250,21000"
5335]
5336)
5337start &19
5338end &158
5339sat 32
5340eat 32
5341sty 1
5342st 0
5343sf 1
5344si 0
5345tg (WTG
5346uid 320,0
5347ps "ConnStartEndStrategy"
5348stg "STSignalDisplayStrategy"
5349f (Text
5350uid 321,0
5351va (VaSet
5352)
5353xt "111000,20000,117000,21000"
5354st "wiz_addr : (9:0)"
5355blo "111000,20800"
5356tm "WireNameMgr"
5357)
5358)
5359on &76
5360)
5361*180 (Wire
5362uid 324,0
5363shape (OrthoPolyLine
5364uid 325,0
5365va (VaSet
5366vasetType 3
5367lineWidth 2
5368)
5369xt "109750,22000,122250,22000"
5370pts [
5371"109750,22000"
5372"122250,22000"
5373]
5374)
5375start &20
5376end &159
5377sat 32
5378eat 32
5379sty 1
5380st 0
5381sf 1
5382si 0
5383tg (WTG
5384uid 326,0
5385ps "ConnStartEndStrategy"
5386stg "STSignalDisplayStrategy"
5387f (Text
5388uid 327,0
5389va (VaSet
5390)
5391xt "111000,21000,117300,22000"
5392st "wiz_data : (15:0)"
5393blo "111000,21800"
5394tm "WireNameMgr"
5395)
5396)
5397on &77
5398)
5399*181 (Wire
5400uid 330,0
5401shape (OrthoPolyLine
5402uid 331,0
5403va (VaSet
5404vasetType 3
5405)
5406xt "109750,25000,122250,25000"
5407pts [
5408"109750,25000"
5409"122250,25000"
5410]
5411)
5412start &23
5413end &160
5414sat 32
5415eat 32
5416st 0
5417sf 1
5418si 0
5419tg (WTG
5420uid 332,0
5421ps "ConnStartEndStrategy"
5422stg "STSignalDisplayStrategy"
5423f (Text
5424uid 333,0
5425va (VaSet
5426)
5427xt "111000,24000,113600,25000"
5428st "wiz_rd"
5429blo "111000,24800"
5430tm "WireNameMgr"
5431)
5432)
5433on &78
5434)
5435*182 (Wire
5436uid 336,0
5437shape (OrthoPolyLine
5438uid 337,0
5439va (VaSet
5440vasetType 3
5441)
5442xt "109750,26000,122250,26000"
5443pts [
5444"109750,26000"
5445"122250,26000"
5446]
5447)
5448start &22
5449end &161
5450sat 32
5451eat 32
5452st 0
5453sf 1
5454si 0
5455tg (WTG
5456uid 338,0
5457ps "ConnStartEndStrategy"
5458stg "STSignalDisplayStrategy"
5459f (Text
5460uid 339,0
5461va (VaSet
5462)
5463xt "111000,25000,113700,26000"
5464st "wiz_wr"
5465blo "111000,25800"
5466tm "WireNameMgr"
5467)
5468)
5469on &79
5470)
5471*183 (Wire
5472uid 374,0
5473shape (OrthoPolyLine
5474uid 375,0
5475va (VaSet
5476vasetType 3
5477lineWidth 2
5478)
5479xt "109750,42000,122250,48000"
5480pts [
5481"109750,42000"
5482"120000,42000"
5483"120000,48000"
5484"122250,48000"
5485]
5486)
5487start &41
5488end &83
5489sat 32
5490eat 32
5491sty 1
5492st 0
5493sf 1
5494si 0
5495tg (WTG
5496uid 376,0
5497ps "ConnStartEndStrategy"
5498stg "STSignalDisplayStrategy"
5499f (Text
5500uid 377,0
5501va (VaSet
5502)
5503xt "111000,41000,117500,42000"
5504st "sensor_cs : (3:0)"
5505blo "111000,41800"
5506tm "WireNameMgr"
5507)
5508)
5509on &87
5510)
5511*184 (Wire
5512uid 380,0
5513shape (OrthoPolyLine
5514uid 381,0
5515va (VaSet
5516vasetType 3
5517)
5518xt "109750,51000,122250,51000"
5519pts [
5520"109750,51000"
5521"122250,51000"
5522]
5523)
5524start &38
5525end &81
5526sat 32
5527eat 32
5528st 0
5529sf 1
5530si 0
5531tg (WTG
5532uid 382,0
5533ps "ConnStartEndStrategy"
5534stg "STSignalDisplayStrategy"
5535f (Text
5536uid 383,0
5537va (VaSet
5538)
5539xt "111000,50000,112700,51000"
5540st "sclk"
5541blo "111000,50800"
5542tm "WireNameMgr"
5543)
5544)
5545on &88
5546)
5547*185 (Wire
5548uid 386,0
5549shape (OrthoPolyLine
5550uid 387,0
5551va (VaSet
5552vasetType 3
5553)
5554xt "109750,52000,122250,52000"
5555pts [
5556"109750,52000"
5557"122250,52000"
5558]
5559)
5560start &39
5561end &82
5562sat 32
5563eat 32
5564st 0
5565sf 1
5566si 0
5567tg (WTG
5568uid 388,0
5569ps "ConnStartEndStrategy"
5570stg "STSignalDisplayStrategy"
5571f (Text
5572uid 389,0
5573va (VaSet
5574)
5575xt "111000,51000,112400,52000"
5576st "sio"
5577blo "111000,51800"
5578tm "WireNameMgr"
5579)
5580)
5581on &89
5582)
5583*186 (Wire
5584uid 426,0
5585shape (OrthoPolyLine
5586uid 427,0
5587va (VaSet
5588vasetType 3
5589)
5590xt "58750,32000,80250,32000"
5591pts [
5592"58750,32000"
5593"80250,32000"
5594]
5595)
5596start &91
5597end &15
5598sat 32
5599eat 32
5600st 0
5601sf 1
5602tg (WTG
5603uid 428,0
5604ps "ConnStartEndStrategy"
5605stg "STSignalDisplayStrategy"
5606f (Text
5607uid 429,0
5608va (VaSet
5609)
5610xt "71000,31000,73800,32000"
5611st "trigger"
5612blo "71000,31800"
5613tm "WireNameMgr"
5614)
5615)
5616on &95
5617)
5618*187 (Wire
5619uid 442,0
5620shape (OrthoPolyLine
5621uid 443,0
5622va (VaSet
5623vasetType 3
5624lineWidth 2
5625)
5626xt "58000,34000,80250,42000"
5627pts [
5628"80250,34000"
5629"64000,34000"
5630"64000,42000"
5631"58000,42000"
5632]
5633)
5634start &17
5635end &96
5636sat 32
5637eat 2
5638sty 1
5639st 0
5640sf 1
5641si 0
5642tg (WTG
5643uid 446,0
5644ps "ConnStartEndStrategy"
5645stg "STSignalDisplayStrategy"
5646f (Text
5647uid 447,0
5648va (VaSet
5649)
5650xt "71000,33000,76900,34000"
5651st "board_id : (3:0)"
5652blo "71000,33800"
5653tm "WireNameMgr"
5654)
5655)
5656on &100
5657)
5658*188 (Wire
5659uid 450,0
5660shape (OrthoPolyLine
5661uid 451,0
5662va (VaSet
5663vasetType 3
5664lineWidth 2
5665)
5666xt "58000,35000,80250,43000"
5667pts [
5668"80250,35000"
5669"65000,35000"
5670"65000,43000"
5671"58000,43000"
5672]
5673)
5674start &18
5675end &96
5676sat 32
5677eat 2
5678sty 1
5679st 0
5680sf 1
5681si 0
5682tg (WTG
5683uid 454,0
5684ps "ConnStartEndStrategy"
5685stg "STSignalDisplayStrategy"
5686f (Text
5687uid 455,0
5688va (VaSet
5689)
5690xt "71000,34000,76700,35000"
5691st "crate_id : (1:0)"
5692blo "71000,34800"
5693tm "WireNameMgr"
5694)
5695)
5696on &101
5697)
5698*189 (Wire
5699uid 530,0
5700shape (OrthoPolyLine
5701uid 531,0
5702va (VaSet
5703vasetType 3
5704lineWidth 2
5705)
5706xt "58000,42000,80250,53000"
5707pts [
5708"80250,42000"
5709"68000,42000"
5710"68000,53000"
5711"58000,53000"
5712]
5713)
5714start &28
5715end &110
5716sat 32
5717eat 2
5718sty 1
5719st 0
5720sf 1
5721si 0
5722tg (WTG
5723uid 534,0
5724ps "ConnStartEndStrategy"
5725stg "STSignalDisplayStrategy"
5726f (Text
5727uid 535,0
5728va (VaSet
5729)
5730xt "71000,41000,79000,42000"
5731st "adc_otr_array : (3:0)"
5732blo "71000,41800"
5733tm "WireNameMgr"
5734)
5735)
5736on &114
5737)
5738*190 (Wire
5739uid 538,0
5740shape (OrthoPolyLine
5741uid 539,0
5742va (VaSet
5743vasetType 3
5744lineWidth 2
5745)
5746xt "58000,48000,80250,55000"
5747pts [
5748"80250,48000"
5749"70000,48000"
5750"70000,55000"
5751"58000,55000"
5752]
5753)
5754start &29
5755end &110
5756sat 32
5757eat 2
5758sty 1
5759st 0
5760sf 1
5761si 0
5762tg (WTG
5763uid 542,0
5764ps "ConnStartEndStrategy"
5765stg "STSignalDisplayStrategy"
5766f (Text
5767uid 543,0
5768va (VaSet
5769)
5770xt "71000,47000,76900,48000"
5771st "adc_data_array"
5772blo "71000,47800"
5773tm "WireNameMgr"
5774)
5775)
5776on &115
5777)
5778*191 (Wire
5779uid 546,0
5780shape (OrthoPolyLine
5781uid 547,0
5782va (VaSet
5783vasetType 3
5784)
5785xt "58000,43000,80250,54000"
5786pts [
5787"80250,43000"
5788"69000,43000"
5789"69000,54000"
5790"58000,54000"
5791]
5792)
5793start &16
5794end &110
5795sat 32
5796eat 1
5797st 0
5798sf 1
5799si 0
5800tg (WTG
5801uid 550,0
5802ps "ConnStartEndStrategy"
5803stg "STSignalDisplayStrategy"
5804f (Text
5805uid 551,0
5806va (VaSet
5807)
5808xt "71000,42000,74200,43000"
5809st "adc_oeb"
5810blo "71000,42800"
5811tm "WireNameMgr"
5812)
5813)
5814on &116
5815)
5816*192 (Wire
5817uid 554,0
5818shape (OrthoPolyLine
5819uid 555,0
5820va (VaSet
5821vasetType 3
5822)
5823xt "40750,54000,50000,54000"
5824pts [
5825"50000,54000"
5826"40750,54000"
5827]
5828)
5829start &110
5830end &106
5831sat 2
5832eat 32
5833st 0
5834sf 1
5835tg (WTG
5836uid 558,0
5837ps "ConnStartEndStrategy"
5838stg "STSignalDisplayStrategy"
5839f (Text
5840uid 559,0
5841va (VaSet
5842)
5843xt "42000,53000,45200,54000"
5844st "adc_oeb"
5845blo "42000,53800"
5846tm "WireNameMgr"
5847)
5848)
5849on &116
5850)
5851*193 (Wire
5852uid 562,0
5853shape (OrthoPolyLine
5854uid 563,0
5855va (VaSet
5856vasetType 3
5857)
5858xt "40750,53000,50000,53000"
5859pts [
5860"40750,53000"
5861"50000,53000"
5862]
5863)
5864start &105
5865end &110
5866sat 32
5867eat 1
5868st 0
5869sf 1
5870tg (WTG
5871uid 566,0
5872ps "ConnStartEndStrategy"
5873stg "STSignalDisplayStrategy"
5874f (Text
5875uid 567,0
5876va (VaSet
5877)
5878xt "42000,52000,44900,53000"
5879st "adc_otr"
5880blo "42000,52800"
5881tm "WireNameMgr"
5882)
5883)
5884on &117
5885)
5886*194 (Wire
5887uid 570,0
5888shape (OrthoPolyLine
5889uid 571,0
5890va (VaSet
5891vasetType 3
5892lineWidth 2
5893)
5894xt "40750,55000,50000,55000"
5895pts [
5896"40750,55000"
5897"50000,55000"
5898]
5899)
5900start &104
5901end &110
5902sat 32
5903eat 1
5904sty 1
5905st 0
5906sf 1
5907tg (WTG
5908uid 574,0
5909ps "ConnStartEndStrategy"
5910stg "STSignalDisplayStrategy"
5911f (Text
5912uid 575,0
5913va (VaSet
5914)
5915xt "42000,54000,48400,55000"
5916st "adc_data : (11:0)"
5917blo "42000,54800"
5918tm "WireNameMgr"
5919)
5920)
5921on &118
5922)
5923*195 (Wire
5924uid 578,0
5925shape (OrthoPolyLine
5926uid 579,0
5927va (VaSet
5928vasetType 3
5929)
5930xt "24000,53000,29250,53000"
5931pts [
5932"29250,53000"
5933"24000,53000"
5934]
5935)
5936start &103
5937sat 32
5938eat 16
5939st 0
5940sf 1
5941tg (WTG
5942uid 582,0
5943ps "ConnStartEndStrategy"
5944stg "STSignalDisplayStrategy"
5945f (Text
5946uid 583,0
5947va (VaSet
5948)
5949xt "25000,52000,29000,53000"
5950st "ADC_CLK"
5951blo "25000,52800"
5952tm "WireNameMgr"
5953)
5954)
5955on &155
5956)
5957*196 (Wire
5958uid 769,0
5959shape (OrthoPolyLine
5960uid 770,0
5961va (VaSet
5962vasetType 3
5963)
5964xt "109750,24000,116000,24000"
5965pts [
5966"109750,24000"
5967"116000,24000"
5968]
5969)
5970start &13
5971sat 32
5972eat 16
5973st 0
5974sf 1
5975si 0
5976tg (WTG
5977uid 773,0
5978ps "ConnStartEndStrategy"
5979stg "STSignalDisplayStrategy"
5980f (Text
5981uid 774,0
5982va (VaSet
5983)
5984xt "111000,23000,114600,24000"
5985st "wiz_reset"
5986blo "111000,23800"
5987tm "WireNameMgr"
5988)
5989)
5990on &119
5991)
5992*197 (Wire
5993uid 777,0
5994shape (OrthoPolyLine
5995uid 778,0
5996va (VaSet
5997vasetType 3
5998lineWidth 2
5999)
6000xt "109750,70000,116000,70000"
6001pts [
6002"109750,70000"
6003"116000,70000"
6004]
6005)
6006start &14
6007sat 32
6008eat 16
6009sty 1
6010st 0
6011sf 1
6012si 0
6013tg (WTG
6014uid 781,0
6015ps "ConnStartEndStrategy"
6016stg "STSignalDisplayStrategy"
6017f (Text
6018uid 782,0
6019va (VaSet
6020)
6021xt "111000,69000,115000,70000"
6022st "led : (7:0)"
6023blo "111000,69800"
6024tm "WireNameMgr"
6025)
6026)
6027on &120
6028)
6029*198 (Wire
6030uid 785,0
6031shape (OrthoPolyLine
6032uid 786,0
6033va (VaSet
6034vasetType 3
6035)
6036xt "109750,28000,122250,28000"
6037pts [
6038"109750,28000"
6039"122250,28000"
6040]
6041)
6042start &21
6043end &163
6044sat 32
6045eat 32
6046st 0
6047sf 1
6048si 0
6049tg (WTG
6050uid 789,0
6051ps "ConnStartEndStrategy"
6052stg "STSignalDisplayStrategy"
6053f (Text
6054uid 790,0
6055va (VaSet
6056)
6057xt "111000,27000,113700,28000"
6058st "wiz_cs"
6059blo "111000,27800"
6060tm "WireNameMgr"
6061)
6062)
6063on &121
6064)
6065*199 (Wire
6066uid 793,0
6067shape (OrthoPolyLine
6068uid 794,0
6069va (VaSet
6070vasetType 3
6071)
6072xt "109750,27000,122250,27000"
6073pts [
6074"122250,27000"
6075"109750,27000"
6076]
6077)
6078start &162
6079end &24
6080sat 32
6081eat 32
6082st 0
6083sf 1
6084si 0
6085tg (WTG
6086uid 797,0
6087ps "ConnStartEndStrategy"
6088stg "STSignalDisplayStrategy"
6089f (Text
6090uid 798,0
6091va (VaSet
6092)
6093xt "111000,26000,113700,27000"
6094st "wiz_int"
6095blo "111000,26800"
6096tm "WireNameMgr"
6097)
6098)
6099on &122
6100)
6101*200 (Wire
6102uid 801,0
6103shape (OrthoPolyLine
6104uid 802,0
6105va (VaSet
6106vasetType 3
6107)
6108xt "109750,40000,116000,40000"
6109pts [
6110"109750,40000"
6111"116000,40000"
6112]
6113)
6114start &40
6115sat 32
6116eat 16
6117st 0
6118sf 1
6119si 0
6120tg (WTG
6121uid 805,0
6122ps "ConnStartEndStrategy"
6123stg "STSignalDisplayStrategy"
6124f (Text
6125uid 806,0
6126va (VaSet
6127)
6128xt "111000,39000,113800,40000"
6129st "dac_cs"
6130blo "111000,39800"
6131tm "WireNameMgr"
6132)
6133)
6134on &123
6135)
6136*201 (Wire
6137uid 809,0
6138shape (OrthoPolyLine
6139uid 810,0
6140va (VaSet
6141vasetType 3
6142)
6143xt "109750,53000,116000,53000"
6144pts [
6145"109750,53000"
6146"116000,53000"
6147]
6148)
6149start &42
6150sat 32
6151eat 16
6152st 0
6153sf 1
6154si 0
6155tg (WTG
6156uid 813,0
6157ps "ConnStartEndStrategy"
6158stg "STSignalDisplayStrategy"
6159f (Text
6160uid 814,0
6161va (VaSet
6162)
6163xt "111000,52000,113000,53000"
6164st "mosi"
6165blo "111000,52800"
6166tm "WireNameMgr"
6167)
6168)
6169on &124
6170)
6171*202 (Wire
6172uid 817,0
6173shape (OrthoPolyLine
6174uid 818,0
6175va (VaSet
6176vasetType 3
6177)
6178xt "70000,66000,80250,66000"
6179pts [
6180"80250,66000"
6181"70000,66000"
6182]
6183)
6184start &43
6185sat 32
6186eat 16
6187st 0
6188sf 1
6189si 0
6190tg (WTG
6191uid 821,0
6192ps "ConnStartEndStrategy"
6193stg "STSignalDisplayStrategy"
6194f (Text
6195uid 822,0
6196va (VaSet
6197)
6198xt "71000,65000,74000,66000"
6199st "denable"
6200blo "71000,65800"
6201tm "WireNameMgr"
6202)
6203)
6204on &125
6205)
6206*203 (Wire
6207uid 825,0
6208shape (OrthoPolyLine
6209uid 826,0
6210va (VaSet
6211vasetType 3
6212)
6213xt "70000,23000,80250,23000"
6214pts [
6215"80250,23000"
6216"70000,23000"
6217]
6218)
6219start &25
6220sat 32
6221eat 16
6222st 0
6223sf 1
6224si 0
6225tg (WTG
6226uid 829,0
6227ps "ConnStartEndStrategy"
6228stg "STSignalDisplayStrategy"
6229f (Text
6230uid 830,0
6231va (VaSet
6232)
6233xt "71000,22000,75500,23000"
6234st "CLK_25_PS"
6235blo "71000,22800"
6236tm "WireNameMgr"
6237)
6238)
6239on &126
6240)
6241*204 (Wire
6242uid 833,0
6243shape (OrthoPolyLine
6244uid 834,0
6245va (VaSet
6246vasetType 3
6247)
6248xt "70000,22000,80250,22000"
6249pts [
6250"80250,22000"
6251"70000,22000"
6252]
6253)
6254start &26
6255sat 32
6256eat 16
6257st 0
6258sf 1
6259si 0
6260tg (WTG
6261uid 837,0
6262ps "ConnStartEndStrategy"
6263stg "STSignalDisplayStrategy"
6264f (Text
6265uid 838,0
6266va (VaSet
6267)
6268xt "71000,21000,74100,22000"
6269st "CLK_50"
6270blo "71000,21800"
6271tm "WireNameMgr"
6272)
6273)
6274on &127
6275)
6276*205 (Wire
6277uid 841,0
6278shape (OrthoPolyLine
6279uid 842,0
6280va (VaSet
6281vasetType 3
6282lineWidth 2
6283)
6284xt "70000,62000,80250,62000"
6285pts [
6286"80250,62000"
6287"70000,62000"
6288]
6289)
6290start &30
6291sat 32
6292eat 16
6293sty 1
6294st 0
6295sf 1
6296si 0
6297tg (WTG
6298uid 845,0
6299ps "ConnStartEndStrategy"
6300stg "STSignalDisplayStrategy"
6301f (Text
6302uid 846,0
6303va (VaSet
6304)
6305xt "71000,61000,79500,62000"
6306st "drs_channel_id : (3:0)"
6307blo "71000,61800"
6308tm "WireNameMgr"
6309)
6310)
6311on &128
6312)
6313*206 (Wire
6314uid 849,0
6315shape (OrthoPolyLine
6316uid 850,0
6317va (VaSet
6318vasetType 3
6319)
6320xt "70000,67000,80250,67000"
6321pts [
6322"80250,67000"
6323"70000,67000"
6324]
6325)
6326start &31
6327ss 0
6328sat 32
6329eat 16
6330st 0
6331sf 1
6332si 0
6333tg (WTG
6334uid 853,0
6335ps "ConnStartEndStrategy"
6336stg "STSignalDisplayStrategy"
6337f (Text
6338uid 854,0
6339va (VaSet
6340)
6341xt "71000,66000,75300,67000"
6342st "drs_dwrite"
6343blo "71000,66800"
6344tm "WireNameMgr"
6345)
6346)
6347on &129
6348)
6349*207 (Wire
6350uid 857,0
6351shape (OrthoPolyLine
6352uid 858,0
6353va (VaSet
6354vasetType 3
6355)
6356xt "70000,64000,80250,64000"
6357pts [
6358"80250,64000"
6359"70000,64000"
6360]
6361)
6362start &36
6363sat 32
6364eat 16
6365st 0
6366sf 1
6367si 0
6368tg (WTG
6369uid 861,0
6370ps "ConnStartEndStrategy"
6371stg "STSignalDisplayStrategy"
6372f (Text
6373uid 862,0
6374va (VaSet
6375)
6376xt "71000,63000,75200,64000"
6377st "RSRLOAD"
6378blo "71000,63800"
6379tm "WireNameMgr"
6380)
6381)
6382on &130
6383)
6384*208 (Wire
6385uid 865,0
6386shape (OrthoPolyLine
6387uid 866,0
6388va (VaSet
6389vasetType 3
6390)
6391xt "70000,65000,80250,65000"
6392pts [
6393"80250,65000"
6394"70000,65000"
6395]
6396)
6397start &37
6398sat 32
6399eat 16
6400st 0
6401sf 1
6402si 0
6403tg (WTG
6404uid 869,0
6405ps "ConnStartEndStrategy"
6406stg "STSignalDisplayStrategy"
6407f (Text
6408uid 870,0
6409va (VaSet
6410)
6411xt "71000,64000,74000,65000"
6412st "SRCLK"
6413blo "71000,64800"
6414tm "WireNameMgr"
6415)
6416)
6417on &131
6418)
6419*209 (Wire
6420uid 873,0
6421shape (OrthoPolyLine
6422uid 874,0
6423va (VaSet
6424vasetType 3
6425)
6426xt "70000,58000,80250,58000"
6427pts [
6428"70000,58000"
6429"80250,58000"
6430]
6431)
6432end &32
6433sat 16
6434eat 32
6435st 0
6436sf 1
6437si 0
6438tg (WTG
6439uid 877,0
6440ps "ConnStartEndStrategy"
6441stg "STSignalDisplayStrategy"
6442f (Text
6443uid 878,0
6444va (VaSet
6445)
6446xt "71000,57000,76400,58000"
6447st "SROUT_in_0"
6448blo "71000,57800"
6449tm "WireNameMgr"
6450)
6451)
6452on &132
6453)
6454*210 (Wire
6455uid 881,0
6456shape (OrthoPolyLine
6457uid 882,0
6458va (VaSet
6459vasetType 3
6460)
6461xt "70000,59000,80250,59000"
6462pts [
6463"70000,59000"
6464"80250,59000"
6465]
6466)
6467end &33
6468sat 16
6469eat 32
6470st 0
6471sf 1
6472si 0
6473tg (WTG
6474uid 885,0
6475ps "ConnStartEndStrategy"
6476stg "STSignalDisplayStrategy"
6477f (Text
6478uid 886,0
6479va (VaSet
6480)
6481xt "71000,58000,76400,59000"
6482st "SROUT_in_1"
6483blo "71000,58800"
6484tm "WireNameMgr"
6485)
6486)
6487on &133
6488)
6489*211 (Wire
6490uid 889,0
6491shape (OrthoPolyLine
6492uid 890,0
6493va (VaSet
6494vasetType 3
6495)
6496xt "70000,60000,80250,60000"
6497pts [
6498"70000,60000"
6499"80250,60000"
6500]
6501)
6502end &34
6503sat 16
6504eat 32
6505st 0
6506sf 1
6507si 0
6508tg (WTG
6509uid 893,0
6510ps "ConnStartEndStrategy"
6511stg "STSignalDisplayStrategy"
6512f (Text
6513uid 894,0
6514va (VaSet
6515)
6516xt "71000,59000,76400,60000"
6517st "SROUT_in_2"
6518blo "71000,59800"
6519tm "WireNameMgr"
6520)
6521)
6522on &134
6523)
6524*212 (Wire
6525uid 897,0
6526shape (OrthoPolyLine
6527uid 898,0
6528va (VaSet
6529vasetType 3
6530)
6531xt "70000,61000,80250,61000"
6532pts [
6533"70000,61000"
6534"80250,61000"
6535]
6536)
6537end &35
6538sat 16
6539eat 32
6540st 0
6541sf 1
6542si 0
6543tg (WTG
6544uid 901,0
6545ps "ConnStartEndStrategy"
6546stg "STSignalDisplayStrategy"
6547f (Text
6548uid 902,0
6549va (VaSet
6550)
6551xt "71000,60000,76400,61000"
6552st "SROUT_in_3"
6553blo "71000,60800"
6554tm "WireNameMgr"
6555)
6556)
6557on &135
6558)
6559*213 (Wire
6560uid 1437,0
6561shape (OrthoPolyLine
6562uid 1438,0
6563va (VaSet
6564vasetType 3
6565)
6566xt "73000,72000,80250,72000"
6567pts [
6568"80250,72000"
6569"73000,72000"
6570]
6571)
6572start &53
6573sat 32
6574eat 16
6575st 0
6576sf 1
6577si 0
6578tg (WTG
6579uid 1441,0
6580ps "ConnStartEndStrategy"
6581stg "STSignalDisplayStrategy"
6582f (Text
6583uid 1442,0
6584va (VaSet
6585)
6586xt "76000,72000,79700,73000"
6587st "SRIN_out"
6588blo "76000,72800"
6589tm "WireNameMgr"
6590)
6591)
6592on &136
6593)
6594*214 (Wire
6595uid 1445,0
6596shape (OrthoPolyLine
6597uid 1446,0
6598va (VaSet
6599vasetType 3
6600)
6601xt "109750,80000,115000,80000"
6602pts [
6603"109750,80000"
6604"115000,80000"
6605]
6606)
6607start &46
6608sat 32
6609eat 16
6610st 0
6611sf 1
6612si 0
6613tg (WTG
6614uid 1449,0
6615ps "ConnStartEndStrategy"
6616stg "STSignalDisplayStrategy"
6617f (Text
6618uid 1450,0
6619va (VaSet
6620)
6621xt "111000,79000,113500,80000"
6622st "amber"
6623blo "111000,79800"
6624tm "WireNameMgr"
6625)
6626)
6627on &137
6628)
6629*215 (Wire
6630uid 1453,0
6631shape (OrthoPolyLine
6632uid 1454,0
6633va (VaSet
6634vasetType 3
6635)
6636xt "109750,79000,114000,79000"
6637pts [
6638"109750,79000"
6639"114000,79000"
6640]
6641)
6642start &52
6643sat 32
6644eat 16
6645st 0
6646sf 1
6647si 0
6648tg (WTG
6649uid 1457,0
6650ps "ConnStartEndStrategy"
6651stg "STSignalDisplayStrategy"
6652f (Text
6653uid 1458,0
6654va (VaSet
6655)
6656xt "111000,78000,112500,79000"
6657st "red"
6658blo "111000,78800"
6659tm "WireNameMgr"
6660)
6661)
6662on &138
6663)
6664*216 (Wire
6665uid 1461,0
6666shape (OrthoPolyLine
6667uid 1462,0
6668va (VaSet
6669vasetType 3
6670)
6671xt "109750,78000,114000,78000"
6672pts [
6673"109750,78000"
6674"114000,78000"
6675]
6676)
6677start &50
6678sat 32
6679eat 16
6680st 0
6681sf 1
6682si 0
6683tg (WTG
6684uid 1465,0
6685ps "ConnStartEndStrategy"
6686stg "STSignalDisplayStrategy"
6687f (Text
6688uid 1466,0
6689va (VaSet
6690)
6691xt "111000,77000,113400,78000"
6692st "green"
6693blo "111000,77800"
6694tm "WireNameMgr"
6695)
6696)
6697on &139
6698)
6699*217 (Wire
6700uid 1469,0
6701shape (OrthoPolyLine
6702uid 1470,0
6703va (VaSet
6704vasetType 3
6705lineWidth 2
6706)
6707xt "109750,77000,121000,77000"
6708pts [
6709"109750,77000"
6710"121000,77000"
6711]
6712)
6713start &47
6714sat 32
6715eat 16
6716sty 1
6717st 0
6718sf 1
6719si 0
6720tg (WTG
6721uid 1473,0
6722ps "ConnStartEndStrategy"
6723stg "STSignalDisplayStrategy"
6724f (Text
6725uid 1474,0
6726va (VaSet
6727)
6728xt "111000,76000,119600,77000"
6729st "counter_result : (11:0)"
6730blo "111000,76800"
6731tm "WireNameMgr"
6732)
6733)
6734on &140
6735)
6736*218 (Wire
6737uid 1477,0
6738shape (OrthoPolyLine
6739uid 1478,0
6740va (VaSet
6741vasetType 3
6742)
6743xt "109750,75000,120000,75000"
6744pts [
6745"109750,75000"
6746"120000,75000"
6747]
6748)
6749start &45
6750sat 32
6751eat 16
6752st 0
6753sf 1
6754si 0
6755tg (WTG
6756uid 1481,0
6757ps "ConnStartEndStrategy"
6758stg "STSignalDisplayStrategy"
6759f (Text
6760uid 1482,0
6761va (VaSet
6762)
6763xt "111000,74000,119200,75000"
6764st "alarm_refclk_too_low"
6765blo "111000,74800"
6766tm "WireNameMgr"
6767)
6768)
6769on &141
6770)
6771*219 (Wire
6772uid 1485,0
6773shape (OrthoPolyLine
6774uid 1486,0
6775va (VaSet
6776vasetType 3
6777)
6778xt "109750,74000,121000,74000"
6779pts [
6780"109750,74000"
6781"121000,74000"
6782]
6783)
6784start &44
6785sat 32
6786eat 16
6787st 0
6788sf 1
6789si 0
6790tg (WTG
6791uid 1489,0
6792ps "ConnStartEndStrategy"
6793stg "STSignalDisplayStrategy"
6794f (Text
6795uid 1490,0
6796va (VaSet
6797)
6798xt "111000,73000,119600,74000"
6799st "alarm_refclk_too_high"
6800blo "111000,73800"
6801tm "WireNameMgr"
6802)
6803)
6804on &142
6805)
6806*220 (Wire
6807uid 1503,0
6808shape (OrthoPolyLine
6809uid 1504,0
6810va (VaSet
6811vasetType 3
6812lineWidth 2
6813)
6814xt "73000,75000,80250,75000"
6815pts [
6816"73000,75000"
6817"80250,75000"
6818]
6819)
6820end &48
6821sat 16
6822eat 32
6823sty 1
6824st 0
6825sf 1
6826si 0
6827tg (WTG
6828uid 1507,0
6829ps "ConnStartEndStrategy"
6830stg "STSignalDisplayStrategy"
6831f (Text
6832uid 1508,0
6833va (VaSet
6834)
6835xt "74000,74000,79500,75000"
6836st "D_T_in : (1:0)"
6837blo "74000,74800"
6838tm "WireNameMgr"
6839)
6840)
6841on &147
6842)
6843*221 (Wire
6844uid 1529,0
6845shape (OrthoPolyLine
6846uid 1530,0
6847va (VaSet
6848vasetType 3
6849)
6850xt "66750,76000,80250,79000"
6851pts [
6852"66750,79000"
6853"70000,79000"
6854"70000,76000"
6855"80250,76000"
6856]
6857)
6858start &149
6859end &49
6860sat 32
6861eat 32
6862st 0
6863sf 1
6864si 0
6865tg (WTG
6866uid 1531,0
6867ps "ConnStartEndStrategy"
6868stg "STSignalDisplayStrategy"
6869f (Text
6870uid 1532,0
6871va (VaSet
6872)
6873xt "68750,78000,72650,79000"
6874st "REF_CLK"
6875blo "68750,78800"
6876tm "WireNameMgr"
6877)
6878)
6879on &156
6880)
6881*222 (Wire
6882uid 1533,0
6883shape (OrthoPolyLine
6884uid 1534,0
6885va (VaSet
6886vasetType 3
6887)
6888xt "35000,70000,45000,70000"
6889pts [
6890"35000,70000"
6891"45000,70000"
6892]
6893)
6894start &143
6895sat 2
6896eat 16
6897st 0
6898sf 1
6899si 0
6900tg (WTG
6901uid 1539,0
6902ps "ConnStartEndStrategy"
6903stg "STSignalDisplayStrategy"
6904f (Text
6905uid 1540,0
6906va (VaSet
6907)
6908xt "37000,69000,42500,70000"
6909st "D_T_in : (1:0)"
6910blo "37000,69800"
6911tm "WireNameMgr"
6912)
6913)
6914on &147
6915)
6916*223 (Wire
6917uid 1561,0
6918shape (OrthoPolyLine
6919uid 1562,0
6920va (VaSet
6921vasetType 3
6922lineWidth 2
6923)
6924xt "72000,77000,80250,77000"
6925pts [
6926"72000,77000"
6927"80250,77000"
6928]
6929)
6930end &51
6931sat 16
6932eat 32
6933sty 1
6934st 0
6935sf 1
6936si 0
6937tg (WTG
6938uid 1565,0
6939ps "ConnStartEndStrategy"
6940stg "STSignalDisplayStrategy"
6941f (Text
6942uid 1566,0
6943va (VaSet
6944)
6945xt "73000,76000,79100,77000"
6946st "plllock_in : (3:0)"
6947blo "73000,76800"
6948tm "WireNameMgr"
6949)
6950)
6951on &154
6952)
6953*224 (Wire
6954uid 1567,0
6955shape (OrthoPolyLine
6956uid 1568,0
6957va (VaSet
6958vasetType 3
6959)
6960xt "35000,71000,45000,71000"
6961pts [
6962"35000,71000"
6963"45000,71000"
6964]
6965)
6966start &143
6967sat 2
6968eat 16
6969st 0
6970sf 1
6971si 0
6972tg (WTG
6973uid 1573,0
6974ps "ConnStartEndStrategy"
6975stg "STSignalDisplayStrategy"
6976f (Text
6977uid 1574,0
6978va (VaSet
6979)
6980xt "37000,70000,43100,71000"
6981st "plllock_in : (3:0)"
6982blo "37000,70800"
6983tm "WireNameMgr"
6984)
6985)
6986on &154
6987)
6988*225 (Wire
6989uid 1684,0
6990shape (OrthoPolyLine
6991uid 1685,0
6992va (VaSet
6993vasetType 3
6994)
6995xt "70000,24000,80250,24000"
6996pts [
6997"80250,24000"
6998"70000,24000"
6999]
7000)
7001start &54
7002sat 32
7003eat 16
7004st 0
7005sf 1
7006si 0
7007tg (WTG
7008uid 1688,0
7009ps "ConnStartEndStrategy"
7010stg "STSignalDisplayStrategy"
7011f (Text
7012uid 1689,0
7013va (VaSet
7014)
7015xt "71000,23000,75000,24000"
7016st "ADC_CLK"
7017blo "71000,23800"
7018tm "WireNameMgr"
7019)
7020)
7021on &155
7022)
7023*226 (Wire
7024uid 2707,0
7025shape (OrthoPolyLine
7026uid 2708,0
7027va (VaSet
7028vasetType 3
7029)
7030xt "109750,81000,122000,81000"
7031pts [
7032"109750,81000"
7033"122000,81000"
7034]
7035)
7036start &55
7037sat 32
7038eat 16
7039st 0
7040sf 1
7041si 0
7042tg (WTG
7043uid 2711,0
7044ps "ConnStartEndStrategy"
7045stg "STSignalDisplayStrategy"
7046f (Text
7047uid 2712,0
7048va (VaSet
7049)
7050xt "111000,80000,121400,81000"
7051st "debug_data_ram_empty"
7052blo "111000,80800"
7053tm "WireNameMgr"
7054)
7055)
7056on &167
7057)
7058*227 (Wire
7059uid 2715,0
7060shape (OrthoPolyLine
7061uid 2716,0
7062va (VaSet
7063vasetType 3
7064)
7065xt "109750,82000,120000,82000"
7066pts [
7067"109750,82000"
7068"120000,82000"
7069]
7070)
7071start &56
7072sat 32
7073eat 16
7074st 0
7075sf 1
7076si 0
7077tg (WTG
7078uid 2719,0
7079ps "ConnStartEndStrategy"
7080stg "STSignalDisplayStrategy"
7081f (Text
7082uid 2720,0
7083va (VaSet
7084)
7085xt "111000,81000,118500,82000"
7086st "debug_data_valid"
7087blo "111000,81800"
7088tm "WireNameMgr"
7089)
7090)
7091on &168
7092)
7093*228 (Wire
7094uid 2723,0
7095shape (OrthoPolyLine
7096uid 2724,0
7097va (VaSet
7098vasetType 3
7099lineWidth 2
7100)
7101xt "109750,83000,119000,83000"
7102pts [
7103"109750,83000"
7104"119000,83000"
7105]
7106)
7107start &57
7108sat 32
7109eat 16
7110sty 1
7111st 0
7112sf 1
7113si 0
7114tg (WTG
7115uid 2727,0
7116ps "ConnStartEndStrategy"
7117stg "STSignalDisplayStrategy"
7118f (Text
7119uid 2728,0
7120va (VaSet
7121)
7122xt "111000,82000,117900,83000"
7123st "DG_state : (7:0)"
7124blo "111000,82800"
7125tm "WireNameMgr"
7126)
7127)
7128on &169
7129)
7130*229 (Wire
7131uid 2731,0
7132shape (OrthoPolyLine
7133uid 2732,0
7134va (VaSet
7135vasetType 3
7136)
7137xt "109750,84000,120000,84000"
7138pts [
7139"109750,84000"
7140"120000,84000"
7141]
7142)
7143start &59
7144sat 32
7145eat 16
7146st 0
7147sf 1
7148si 0
7149tg (WTG
7150uid 2735,0
7151ps "ConnStartEndStrategy"
7152stg "STSignalDisplayStrategy"
7153f (Text
7154uid 2736,0
7155va (VaSet
7156)
7157xt "111000,83000,119400,84000"
7158st "FTM_RS485_rx_en"
7159blo "111000,83800"
7160tm "WireNameMgr"
7161)
7162)
7163on &170
7164)
7165*230 (Wire
7166uid 2739,0
7167shape (OrthoPolyLine
7168uid 2740,0
7169va (VaSet
7170vasetType 3
7171)
7172xt "109750,85000,120000,85000"
7173pts [
7174"109750,85000"
7175"120000,85000"
7176]
7177)
7178start &60
7179sat 32
7180eat 16
7181st 0
7182sf 1
7183si 0
7184tg (WTG
7185uid 2743,0
7186ps "ConnStartEndStrategy"
7187stg "STSignalDisplayStrategy"
7188f (Text
7189uid 2744,0
7190va (VaSet
7191)
7192xt "111000,84000,119100,85000"
7193st "FTM_RS485_tx_d"
7194blo "111000,84800"
7195tm "WireNameMgr"
7196)
7197)
7198on &171
7199)
7200*231 (Wire
7201uid 2747,0
7202shape (OrthoPolyLine
7203uid 2748,0
7204va (VaSet
7205vasetType 3
7206)
7207xt "109750,86000,120000,86000"
7208pts [
7209"109750,86000"
7210"120000,86000"
7211]
7212)
7213start &61
7214sat 32
7215eat 16
7216st 0
7217sf 1
7218si 0
7219tg (WTG
7220uid 2751,0
7221ps "ConnStartEndStrategy"
7222stg "STSignalDisplayStrategy"
7223f (Text
7224uid 2752,0
7225va (VaSet
7226)
7227xt "111000,85000,119400,86000"
7228st "FTM_RS485_tx_en"
7229blo "111000,85800"
7230tm "WireNameMgr"
7231)
7232)
7233on &172
7234)
7235*232 (Wire
7236uid 2755,0
7237shape (OrthoPolyLine
7238uid 2756,0
7239va (VaSet
7240vasetType 3
7241lineWidth 2
7242)
7243xt "109750,87000,123000,87000"
7244pts [
7245"109750,87000"
7246"123000,87000"
7247]
7248)
7249start &62
7250sat 32
7251eat 16
7252sty 1
7253st 0
7254sf 1
7255si 0
7256tg (WTG
7257uid 2759,0
7258ps "ConnStartEndStrategy"
7259stg "STSignalDisplayStrategy"
7260f (Text
7261uid 2760,0
7262va (VaSet
7263)
7264xt "111000,86000,122400,87000"
7265st "mem_manager_state : (3:0)"
7266blo "111000,86800"
7267tm "WireNameMgr"
7268)
7269)
7270on &173
7271)
7272*233 (Wire
7273uid 2763,0
7274shape (OrthoPolyLine
7275uid 2764,0
7276va (VaSet
7277vasetType 3
7278)
7279xt "109750,88000,118000,88000"
7280pts [
7281"109750,88000"
7282"118000,88000"
7283]
7284)
7285start &63
7286sat 32
7287eat 16
7288st 0
7289sf 1
7290si 0
7291tg (WTG
7292uid 2767,0
7293ps "ConnStartEndStrategy"
7294stg "STSignalDisplayStrategy"
7295f (Text
7296uid 2768,0
7297va (VaSet
7298)
7299xt "111000,87000,116600,88000"
7300st "trigger_veto"
7301blo "111000,87800"
7302tm "WireNameMgr"
7303)
7304)
7305on &174
7306)
7307*234 (Wire
7308uid 2771,0
7309shape (OrthoPolyLine
7310uid 2772,0
7311va (VaSet
7312vasetType 3
7313lineWidth 2
7314)
7315xt "109750,89000,120000,89000"
7316pts [
7317"109750,89000"
7318"120000,89000"
7319]
7320)
7321start &64
7322sat 32
7323eat 16
7324sty 1
7325st 0
7326sf 1
7327si 0
7328tg (WTG
7329uid 2775,0
7330ps "ConnStartEndStrategy"
7331stg "STSignalDisplayStrategy"
7332f (Text
7333uid 2776,0
7334va (VaSet
7335)
7336xt "111000,88000,119400,89000"
7337st "w5300_state : (7:0)"
7338blo "111000,88800"
7339tm "WireNameMgr"
7340)
7341)
7342on &175
7343)
7344*235 (Wire
7345uid 2779,0
7346shape (OrthoPolyLine
7347uid 2780,0
7348va (VaSet
7349vasetType 3
7350)
7351xt "74000,78000,80250,82000"
7352pts [
7353"74000,82000"
7354"80250,78000"
7355]
7356)
7357end &58
7358sat 16
7359eat 32
7360st 0
7361sf 1
7362si 0
7363tg (WTG
7364uid 2783,0
7365ps "ConnStartEndStrategy"
7366stg "STSignalDisplayStrategy"
7367f (Text
7368uid 2784,0
7369va (VaSet
7370)
7371xt "73000,80000,81100,81000"
7372st "FTM_RS485_rx_d"
7373blo "73000,80800"
7374tm "WireNameMgr"
7375)
7376)
7377on &176
7378)
7379*236 (Wire
7380uid 2944,0
7381shape (OrthoPolyLine
7382uid 2945,0
7383va (VaSet
7384vasetType 3
7385lineWidth 2
7386)
7387xt "109750,90000,124000,90000"
7388pts [
7389"109750,90000"
7390"124000,90000"
7391]
7392)
7393start &65
7394sat 32
7395eat 16
7396sty 1
7397st 0
7398sf 1
7399si 0
7400tg (WTG
7401uid 2948,0
7402ps "ConnStartEndStrategy"
7403stg "STSignalDisplayStrategy"
7404f (Text
7405uid 2949,0
7406va (VaSet
7407)
7408xt "111000,89000,122900,90000"
7409st "socket_tx_free_out : (16:0)"
7410blo "111000,89800"
7411tm "WireNameMgr"
7412)
7413)
7414on &177
7415)
7416]
7417bg "65535,65535,65535"
7418grid (Grid
7419origin "0,0"
7420isVisible 1
7421isActive 1
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8358)
8359]
8360)
8361)
8362defaultBlockFrame (Frame
8363shape (RectFrame
8364va (VaSet
8365vasetType 1
8366fg "65535,65535,65535"
8367lineColor "26368,26368,26368"
8368lineStyle 1
8369lineWidth 2
8370)
8371xt "0,0,20000,20000"
8372)
8373title (TextAssociate
8374ps "TopLeftStrategy"
8375text (MLText
8376va (VaSet
8377)
8378xt "0,-1100,7400,-100"
8379st "b0: BLOCK (guard)"
8380tm "FrameTitleTextMgr"
8381)
8382)
8383seqNum (FrameSequenceNumber
8384ps "TopLeftStrategy"
8385shape (Rectangle
8386va (VaSet
8387vasetType 1
8388fg "65535,65535,65535"
8389)
8390xt "50,50,1250,1450"
8391)
8392num (Text
8393va (VaSet
8394)
8395xt "250,250,1050,1250"
8396st "1"
8397blo "250,1050"
8398tm "FrameSeqNumMgr"
8399)
8400)
8401decls (MlTextGroup
8402ps "BottomRightOffsetStrategy"
8403stg "VerticalLayoutStrategy"
8404textVec [
8405*266 (Text
8406va (VaSet
8407font "Arial,8,1"
8408)
8409xt "14100,20000,22000,21000"
8410st "Frame Declarations"
8411blo "14100,20800"
8412)
8413*267 (MLText
8414va (VaSet
8415)
8416xt "14100,21000,14100,21000"
8417tm "BdFrameDeclTextMgr"
8418)
8419]
8420)
8421style 3
8422)
8423defaultSaCptPort (CptPort
8424ps "OnEdgeStrategy"
8425shape (Triangle
8426ro 90
8427va (VaSet
8428vasetType 1
8429fg "0,65535,0"
8430)
8431xt "0,0,750,750"
8432)
8433tg (CPTG
8434ps "CptPortTextPlaceStrategy"
8435stg "VerticalLayoutStrategy"
8436f (Text
8437va (VaSet
8438)
8439xt "0,750,1800,1750"
8440st "Port"
8441blo "0,1550"
8442)
8443)
8444thePort (LogicalPort
8445decl (Decl
8446n "Port"
8447t ""
8448o 0
8449)
8450)
8451)
8452defaultSaCptPortBuffer (CptPort
8453ps "OnEdgeStrategy"
8454shape (Diamond
8455va (VaSet
8456vasetType 1
8457fg "65535,65535,65535"
8458)
8459xt "0,0,750,750"
8460)
8461tg (CPTG
8462ps "CptPortTextPlaceStrategy"
8463stg "VerticalLayoutStrategy"
8464f (Text
8465va (VaSet
8466)
8467xt "0,750,1800,1750"
8468st "Port"
8469blo "0,1550"
8470)
8471)
8472thePort (LogicalPort
8473m 3
8474decl (Decl
8475n "Port"
8476t ""
8477o 0
8478)
8479)
8480)
8481defaultDeclText (MLText
8482va (VaSet
8483font "Courier New,8,0"
8484)
8485)
8486archDeclarativeBlock (BdArchDeclBlock
8487uid 1,0
8488stg "BdArchDeclBlockLS"
8489declLabel (Text
8490uid 2,0
8491va (VaSet
8492font "Arial,8,1"
8493)
8494xt "-92000,21600,-86600,22600"
8495st "Declarations"
8496blo "-92000,22400"
8497)
8498portLabel (Text
8499uid 3,0
8500va (VaSet
8501font "Arial,8,1"
8502)
8503xt "-92000,22600,-89300,23600"
8504st "Ports:"
8505blo "-92000,23400"
8506)
8507preUserLabel (Text
8508uid 4,0
8509va (VaSet
8510isHidden 1
8511font "Arial,8,1"
8512)
8513xt "-92000,21600,-88200,22600"
8514st "Pre User:"
8515blo "-92000,22400"
8516)
8517preUserText (MLText
8518uid 5,0
8519va (VaSet
8520isHidden 1
8521font "Courier New,8,0"
8522)
8523xt "-92000,21600,-92000,21600"
8524tm "BdDeclarativeTextMgr"
8525)
8526diagSignalLabel (Text
8527uid 6,0
8528va (VaSet
8529font "Arial,8,1"
8530)
8531xt "-92000,23600,-84900,24600"
8532st "Diagram Signals:"
8533blo "-92000,24400"
8534)
8535postUserLabel (Text
8536uid 7,0
8537va (VaSet
8538isHidden 1
8539font "Arial,8,1"
8540)
8541xt "-92000,21600,-87300,22600"
8542st "Post User:"
8543blo "-92000,22400"
8544)
8545postUserText (MLText
8546uid 8,0
8547va (VaSet
8548isHidden 1
8549font "Courier New,8,0"
8550)
8551xt "-92000,21600,-92000,21600"
8552tm "BdDeclarativeTextMgr"
8553)
8554)
8555commonDM (CommonDM
8556ldm (LogicalDM
8557suid 64,0
8558usingSuid 1
8559emptyRow *268 (LEmptyRow
8560)
8561uid 54,0
8562optionalChildren [
8563*269 (RefLabelRowHdr
8564)
8565*270 (TitleRowHdr
8566)
8567*271 (FilterRowHdr
8568)
8569*272 (RefLabelColHdr
8570tm "RefLabelColHdrMgr"
8571)
8572*273 (RowExpandColHdr
8573tm "RowExpandColHdrMgr"
8574)
8575*274 (GroupColHdr
8576tm "GroupColHdrMgr"
8577)
8578*275 (NameColHdr
8579tm "BlockDiagramNameColHdrMgr"
8580)
8581*276 (ModeColHdr
8582tm "BlockDiagramModeColHdrMgr"
8583)
8584*277 (TypeColHdr
8585tm "BlockDiagramTypeColHdrMgr"
8586)
8587*278 (BoundsColHdr
8588tm "BlockDiagramBoundsColHdrMgr"
8589)
8590*279 (InitColHdr
8591tm "BlockDiagramInitColHdrMgr"
8592)
8593*280 (EolColHdr
8594tm "BlockDiagramEolColHdrMgr"
8595)
8596*281 (LeafLogPort
8597port (LogicalPort
8598m 4
8599decl (Decl
8600n "clk"
8601t "STD_LOGIC"
8602preAdd 0
8603posAdd 0
8604o 1
8605suid 1,0
8606)
8607)
8608uid 340,0
8609)
8610*282 (LeafLogPort
8611port (LogicalPort
8612m 4
8613decl (Decl
8614n "wiz_addr"
8615t "std_logic_vector"
8616b "(9 DOWNTO 0)"
8617o 2
8618suid 2,0
8619)
8620)
8621uid 342,0
8622)
8623*283 (LeafLogPort
8624port (LogicalPort
8625m 4
8626decl (Decl
8627n "wiz_data"
8628t "std_logic_vector"
8629b "(15 DOWNTO 0)"
8630o 3
8631suid 3,0
8632)
8633)
8634uid 344,0
8635)
8636*284 (LeafLogPort
8637port (LogicalPort
8638m 4
8639decl (Decl
8640n "wiz_rd"
8641t "std_logic"
8642o 4
8643suid 4,0
8644i "'1'"
8645)
8646)
8647uid 346,0
8648)
8649*285 (LeafLogPort
8650port (LogicalPort
8651m 4
8652decl (Decl
8653n "wiz_wr"
8654t "std_logic"
8655o 5
8656suid 5,0
8657i "'1'"
8658)
8659)
8660uid 348,0
8661)
8662*286 (LeafLogPort
8663port (LogicalPort
8664m 4
8665decl (Decl
8666n "sensor_cs"
8667t "std_logic_vector"
8668b "(3 DOWNTO 0)"
8669o 6
8670suid 6,0
8671)
8672)
8673uid 404,0
8674)
8675*287 (LeafLogPort
8676port (LogicalPort
8677m 4
8678decl (Decl
8679n "sclk"
8680t "std_logic"
8681o 7
8682suid 7,0
8683)
8684)
8685uid 406,0
8686)
8687*288 (LeafLogPort
8688port (LogicalPort
8689m 4
8690decl (Decl
8691n "sio"
8692t "std_logic"
8693preAdd 0
8694posAdd 0
8695o 8
8696suid 8,0
8697)
8698)
8699uid 408,0
8700)
8701*289 (LeafLogPort
8702port (LogicalPort
8703m 4
8704decl (Decl
8705n "trigger"
8706t "std_logic"
8707preAdd 0
8708posAdd 0
8709o 9
8710suid 9,0
8711)
8712)
8713uid 456,0
8714)
8715*290 (LeafLogPort
8716port (LogicalPort
8717m 4
8718decl (Decl
8719n "board_id"
8720t "std_logic_vector"
8721b "(3 downto 0)"
8722preAdd 0
8723posAdd 0
8724o 10
8725suid 10,0
8726)
8727)
8728uid 458,0
8729)
8730*291 (LeafLogPort
8731port (LogicalPort
8732m 4
8733decl (Decl
8734n "crate_id"
8735t "std_logic_vector"
8736b "(1 downto 0)"
8737o 11
8738suid 11,0
8739)
8740)
8741uid 460,0
8742)
8743*292 (LeafLogPort
8744port (LogicalPort
8745m 4
8746decl (Decl
8747n "adc_otr_array"
8748t "std_logic_vector"
8749b "(3 DOWNTO 0)"
8750o 12
8751suid 12,0
8752)
8753)
8754uid 584,0
8755)
8756*293 (LeafLogPort
8757port (LogicalPort
8758m 4
8759decl (Decl
8760n "adc_data_array"
8761t "adc_data_array_type"
8762o 13
8763suid 13,0
8764)
8765)
8766uid 586,0
8767)
8768*294 (LeafLogPort
8769port (LogicalPort
8770m 4
8771decl (Decl
8772n "adc_oeb"
8773t "std_logic"
8774preAdd 0
8775posAdd 0
8776o 14
8777suid 14,0
8778)
8779)
8780uid 588,0
8781)
8782*295 (LeafLogPort
8783port (LogicalPort
8784m 4
8785decl (Decl
8786n "adc_otr"
8787t "STD_LOGIC"
8788preAdd 0
8789posAdd 0
8790o 16
8791suid 16,0
8792)
8793)
8794uid 590,0
8795)
8796*296 (LeafLogPort
8797port (LogicalPort
8798m 4
8799decl (Decl
8800n "adc_data"
8801t "std_logic_vector"
8802b "(11 DOWNTO 0)"
8803preAdd 0
8804posAdd 0
8805o 17
8806suid 17,0
8807)
8808)
8809uid 592,0
8810)
8811*297 (LeafLogPort
8812port (LogicalPort
8813m 4
8814decl (Decl
8815n "wiz_reset"
8816t "std_logic"
8817o 21
8818suid 23,0
8819i "'1'"
8820)
8821)
8822uid 903,0
8823)
8824*298 (LeafLogPort
8825port (LogicalPort
8826m 4
8827decl (Decl
8828n "led"
8829t "std_logic_vector"
8830b "(7 DOWNTO 0)"
8831posAdd 0
8832o 22
8833suid 24,0
8834i "(OTHERS => '0')"
8835)
8836)
8837uid 905,0
8838)
8839*299 (LeafLogPort
8840port (LogicalPort
8841m 4
8842decl (Decl
8843n "wiz_cs"
8844t "std_logic"
8845o 23
8846suid 25,0
8847i "'1'"
8848)
8849)
8850uid 907,0
8851)
8852*300 (LeafLogPort
8853port (LogicalPort
8854m 4
8855decl (Decl
8856n "wiz_int"
8857t "std_logic"
8858o 24
8859suid 26,0
8860)
8861)
8862uid 909,0
8863)
8864*301 (LeafLogPort
8865port (LogicalPort
8866m 4
8867decl (Decl
8868n "dac_cs"
8869t "std_logic"
8870o 25
8871suid 27,0
8872)
8873)
8874uid 911,0
8875)
8876*302 (LeafLogPort
8877port (LogicalPort
8878m 4
8879decl (Decl
8880n "mosi"
8881t "std_logic"
8882o 26
8883suid 28,0
8884i "'0'"
8885)
8886)
8887uid 913,0
8888)
8889*303 (LeafLogPort
8890port (LogicalPort
8891m 4
8892decl (Decl
8893n "denable"
8894t "std_logic"
8895eolc "-- default domino wave off"
8896posAdd 0
8897o 27
8898suid 29,0
8899i "'0'"
8900)
8901)
8902uid 915,0
8903)
8904*304 (LeafLogPort
8905port (LogicalPort
8906m 4
8907decl (Decl
8908n "CLK_25_PS"
8909t "std_logic"
8910o 28
8911suid 30,0
8912)
8913)
8914uid 917,0
8915)
8916*305 (LeafLogPort
8917port (LogicalPort
8918m 4
8919decl (Decl
8920n "CLK_50"
8921t "std_logic"
8922o 29
8923suid 31,0
8924)
8925)
8926uid 919,0
8927)
8928*306 (LeafLogPort
8929port (LogicalPort
8930m 4
8931decl (Decl
8932n "drs_channel_id"
8933t "std_logic_vector"
8934b "(3 downto 0)"
8935o 30
8936suid 32,0
8937i "(others => '0')"
8938)
8939)
8940uid 921,0
8941)
8942*307 (LeafLogPort
8943port (LogicalPort
8944m 4
8945decl (Decl
8946n "drs_dwrite"
8947t "std_logic"
8948o 31
8949suid 33,0
8950i "'1'"
8951)
8952)
8953uid 923,0
8954)
8955*308 (LeafLogPort
8956port (LogicalPort
8957m 4
8958decl (Decl
8959n "RSRLOAD"
8960t "std_logic"
8961o 32
8962suid 34,0
8963i "'0'"
8964)
8965)
8966uid 925,0
8967)
8968*309 (LeafLogPort
8969port (LogicalPort
8970m 4
8971decl (Decl
8972n "SRCLK"
8973t "std_logic"
8974o 33
8975suid 35,0
8976i "'0'"
8977)
8978)
8979uid 927,0
8980)
8981*310 (LeafLogPort
8982port (LogicalPort
8983m 4
8984decl (Decl
8985n "SROUT_in_0"
8986t "std_logic"
8987o 30
8988suid 36,0
8989)
8990)
8991uid 929,0
8992)
8993*311 (LeafLogPort
8994port (LogicalPort
8995m 4
8996decl (Decl
8997n "SROUT_in_1"
8998t "std_logic"
8999o 31
9000suid 37,0
9001)
9002)
9003uid 931,0
9004)
9005*312 (LeafLogPort
9006port (LogicalPort
9007m 4
9008decl (Decl
9009n "SROUT_in_2"
9010t "std_logic"
9011o 32
9012suid 38,0
9013)
9014)
9015uid 933,0
9016)
9017*313 (LeafLogPort
9018port (LogicalPort
9019m 4
9020decl (Decl
9021n "SROUT_in_3"
9022t "std_logic"
9023o 33
9024suid 39,0
9025)
9026)
9027uid 935,0
9028)
9029*314 (LeafLogPort
9030port (LogicalPort
9031m 4
9032decl (Decl
9033n "SRIN_out"
9034t "std_logic"
9035o 34
9036suid 40,0
9037i "'0'"
9038)
9039)
9040uid 1541,0
9041)
9042*315 (LeafLogPort
9043port (LogicalPort
9044m 4
9045decl (Decl
9046n "amber"
9047t "std_logic"
9048o 35
9049suid 41,0
9050)
9051)
9052uid 1543,0
9053)
9054*316 (LeafLogPort
9055port (LogicalPort
9056m 4
9057decl (Decl
9058n "red"
9059t "std_logic"
9060o 36
9061suid 42,0
9062)
9063)
9064uid 1545,0
9065)
9066*317 (LeafLogPort
9067port (LogicalPort
9068m 4
9069decl (Decl
9070n "green"
9071t "std_logic"
9072o 37
9073suid 43,0
9074)
9075)
9076uid 1547,0
9077)
9078*318 (LeafLogPort
9079port (LogicalPort
9080m 4
9081decl (Decl
9082n "counter_result"
9083t "std_logic_vector"
9084b "(11 DOWNTO 0)"
9085o 38
9086suid 44,0
9087)
9088)
9089uid 1549,0
9090)
9091*319 (LeafLogPort
9092port (LogicalPort
9093m 4
9094decl (Decl
9095n "alarm_refclk_too_low"
9096t "std_logic"
9097posAdd 0
9098o 39
9099suid 45,0
9100)
9101)
9102uid 1551,0
9103)
9104*320 (LeafLogPort
9105port (LogicalPort
9106m 4
9107decl (Decl
9108n "alarm_refclk_too_high"
9109t "std_logic"
9110o 40
9111suid 46,0
9112)
9113)
9114uid 1553,0
9115)
9116*321 (LeafLogPort
9117port (LogicalPort
9118m 4
9119decl (Decl
9120n "D_T_in"
9121t "std_logic_vector"
9122b "(1 DOWNTO 0)"
9123o 41
9124suid 47,0
9125)
9126)
9127uid 1555,0
9128)
9129*322 (LeafLogPort
9130port (LogicalPort
9131m 4
9132decl (Decl
9133n "plllock_in"
9134t "std_logic_vector"
9135b "(3 DOWNTO 0)"
9136eolc "-- high level, if dominowave is running and DRS PLL locked"
9137o 43
9138suid 49,0
9139)
9140)
9141uid 1575,0
9142)
9143*323 (LeafLogPort
9144port (LogicalPort
9145lang 2
9146m 4
9147decl (Decl
9148n "ADC_CLK"
9149t "std_logic"
9150o 44
9151suid 50,0
9152)
9153)
9154uid 1690,0
9155)
9156*324 (LeafLogPort
9157port (LogicalPort
9158m 4
9159decl (Decl
9160n "REF_CLK"
9161t "STD_LOGIC"
9162o 42
9163suid 51,0
9164i "'0'"
9165)
9166)
9167uid 2003,0
9168)
9169*325 (LeafLogPort
9170port (LogicalPort
9171m 4
9172decl (Decl
9173n "debug_data_ram_empty"
9174t "std_logic"
9175o 45
9176suid 53,0
9177)
9178)
9179uid 2785,0
9180)
9181*326 (LeafLogPort
9182port (LogicalPort
9183m 4
9184decl (Decl
9185n "debug_data_valid"
9186t "std_logic"
9187o 46
9188suid 54,0
9189)
9190)
9191uid 2787,0
9192)
9193*327 (LeafLogPort
9194port (LogicalPort
9195m 4
9196decl (Decl
9197n "DG_state"
9198t "std_logic_vector"
9199b "(7 downto 0)"
9200prec "-- for debugging"
9201preAdd 0
9202o 47
9203suid 55,0
9204)
9205)
9206uid 2789,0
9207)
9208*328 (LeafLogPort
9209port (LogicalPort
9210m 4
9211decl (Decl
9212n "FTM_RS485_rx_en"
9213t "std_logic"
9214o 48
9215suid 56,0
9216)
9217)
9218uid 2791,0
9219)
9220*329 (LeafLogPort
9221port (LogicalPort
9222m 4
9223decl (Decl
9224n "FTM_RS485_tx_d"
9225t "std_logic"
9226o 49
9227suid 57,0
9228)
9229)
9230uid 2793,0
9231)
9232*330 (LeafLogPort
9233port (LogicalPort
9234m 4
9235decl (Decl
9236n "FTM_RS485_tx_en"
9237t "std_logic"
9238o 50
9239suid 58,0
9240)
9241)
9242uid 2795,0
9243)
9244*331 (LeafLogPort
9245port (LogicalPort
9246lang 2
9247m 4
9248decl (Decl
9249n "mem_manager_state"
9250t "std_logic_vector"
9251b "(3 DOWNTO 0)"
9252eolc "-- state is encoded here ... useful for debugging."
9253posAdd 0
9254o 51
9255suid 59,0
9256)
9257)
9258uid 2797,0
9259)
9260*332 (LeafLogPort
9261port (LogicalPort
9262m 4
9263decl (Decl
9264n "trigger_veto"
9265t "std_logic"
9266o 52
9267suid 60,0
9268i "'1'"
9269)
9270)
9271uid 2799,0
9272)
9273*333 (LeafLogPort
9274port (LogicalPort
9275m 4
9276decl (Decl
9277n "w5300_state"
9278t "std_logic_vector"
9279b "(7 DOWNTO 0)"
9280eolc "-- state is encoded here ... useful for debugging."
9281posAdd 0
9282o 53
9283suid 61,0
9284)
9285)
9286uid 2801,0
9287)
9288*334 (LeafLogPort
9289port (LogicalPort
9290m 4
9291decl (Decl
9292n "FTM_RS485_rx_d"
9293t "std_logic"
9294o 54
9295suid 62,0
9296)
9297)
9298uid 2803,0
9299)
9300*335 (LeafLogPort
9301port (LogicalPort
9302m 4
9303decl (Decl
9304n "socket_tx_free_out"
9305t "std_logic_vector"
9306b "(16 DOWNTO 0)"
9307eolc "-- 17bit value .. that's true"
9308posAdd 0
9309o 55
9310suid 64,0
9311)
9312)
9313uid 2950,0
9314)
9315]
9316)
9317pdm (PhysicalDM
9318displayShortBounds 1
9319editShortBounds 1
9320uid 67,0
9321optionalChildren [
9322*336 (Sheet
9323sheetRow (SheetRow
9324headerVa (MVa
9325cellColor "49152,49152,49152"
9326fontColor "0,0,0"
9327font "Tahoma,10,0"
9328)
9329cellVa (MVa
9330cellColor "65535,65535,65535"
9331fontColor "0,0,0"
9332font "Tahoma,10,0"
9333)
9334groupVa (MVa
9335cellColor "39936,56832,65280"
9336fontColor "0,0,0"
9337font "Tahoma,10,0"
9338)
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9615uid 1576,0
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9640)
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9664)
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9668dimension 20
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9670)
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9675uid 2800,0
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9680dimension 20
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9716uid 75,0
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9740uid 79,0
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9801tm "GenericEolColHdrMgr"
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9848pos 2
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