source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/REFCLK_counter_behavior.vhd @ 10149

Last change on this file since 10149 was 10149, checked in by neise, 9 years ago
REFCLK counter asserts alarm outputs at first place. phase shifter generates correct phaseshift output.
File size: 2.7 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.REFCLK_counter.behavior
3--
4-- Created:
5--          by - dneise.UNKNOWN (E5B-LABOR6)
6--          at - 12:10:57 28.01.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12use IEEE.NUMERIC_STD.ALL;
13
14library FACT_FAD_lib;
15use FACT_FAD_lib.fad_definitions.all;
16
17-- REFCLK counter counts rising edges on asynch REFCLK signal
18-- every ms a new value is returned.
19-- expected REFCLK frequency: up to 3.3MHz --> 12bit should be enough
20-- if the REFCLK id too low or too high, alarm outputs are generated
21
22ENTITY REFCLK_counter IS
23  PORT ( 
24    clk : in std_logic;       -- 50MHz!
25    refclk_in : in std_logic; -- asychronous signal
26    counter_result : out std_logic_vector(11 downto 0) := (others => '0');
27   
28    alarm_refclk_too_high : out std_logic := '1';
29    alarm_refclk_too_low : out std_logic := '1'
30  );   
31END ENTITY REFCLK_counter;
32
33--
34ARCHITECTURE behavior OF REFCLK_counter IS
35  constant FREQ_UPPER_LIMIT : integer := 3000;
36  constant FREQ_LOWER_LIMIT : integer := 300;
37  constant TIMER_MAX : integer := 100000;
38 
39  signal refclk_in_sr : std_logic_vector(1 downto 0) := "00";
40  signal gate_sr : std_logic_vector(1 downto 0) := "00";
41 
42  signal gate : std_logic := '0';
43  signal time : integer range 0 to TIMER_MAX-1; --2ms clock
44 
45  signal counter : integer range 0 to 4095 :=0 ;
46BEGIN
47 
48  -- synchronize REFCLK in
49  process (clk)
50  begin
51    if rising_edge(clk) then
52     -- Schieberegister
53     refclk_in_sr <= refclk_in_sr(0) & refclk_in;
54    end if;
55  end process;
56
57  process ( refclk_in_sr(1))
58   
59  begin
60    if rising_edge( refclk_in_sr(1) ) then
61      gate_sr <= gate_sr(0) & gate;
62      case gate_sr is
63      when "00" =>
64      when "01" => --rising edge
65        counter <= 0;
66      when "10" =>
67        counter_result <= std_logic_vector( to_unsigned(counter,12) );
68        if (counter < FREQ_LOWER_LIMIT ) then
69          alarm_refclk_too_low <= '1';
70        else
71          alarm_refclk_too_low <= '0';
72        end if;
73        if (counter > FREQ_UPPER_LIMIT ) then
74          alarm_refclk_too_high <= '1';
75        else
76          alarm_refclk_too_high <= '0';
77        end if;
78      when "11" =>
79        counter <= counter +1;
80      WHEN OTHERS =>
81       
82      end case;
83    end if;
84  end process;   
85 
86  -- timer proc; generates 1ms gate
87  gate_timer : process (clk)
88 
89  begin
90    if rising_edge(clk) then
91      if (time < TIMER_MAX-1) then 
92       time <= time + 1;
93      else 
94        time <= 0;
95      end if;
96 
97      if (time = 0) then 
98        gate <= '1';
99      end if;
100      if (time = (TIMER_MAX/2)-1) then
101        gate <= '0';
102      end if;
103    end if;
104  end process gate_timer; 
105
106END ARCHITECTURE behavior;
107
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