source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd@ 10121

Last change on this file since 10121 was 10121, checked in by neise, 12 years ago
synchronous trigger handling added continous soft trigger generation. ---> control frequency via 'send 0x21??' each step increases trigger delay by 12.5ms 0x2100 = 40Hz 0x21FF = 0.3Hz
File size: 5.7 KB
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1-- VHDL Entity FACT_FAD_lib.clock_generator_var_ps.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 11:57:15 26.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY clock_generator_var_ps IS
14 PORT(
15 CLK : IN std_logic;
16 RST_IN : IN std_logic;
17 direction : IN std_logic;
18 do_shift : IN std_logic;
19 CLK_25 : OUT std_logic;
20 CLK_25_PS : OUT std_logic;
21 CLK_50 : OUT std_logic;
22 DCM_locked : OUT std_logic;
23 LOCKED_extraOUT : OUT std_logic;
24 PSCLK_OUT : OUT std_logic;
25 PSDONE_extraOUT : OUT std_logic;
26 PSINCDEC_OUT : OUT std_logic;
27 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
28 ready : OUT std_logic := '0';
29 -- status:
30 shifting : OUT std_logic := '0'
31 );
32
33-- Declarations
34
35END clock_generator_var_ps ;
36
37--
38-- VHDL Architecture FACT_FAD_lib.clock_generator_var_ps.struct
39--
40-- Created:
41-- by - dneise.UNKNOWN (E5B-LABOR6)
42-- at - 11:57:15 26.01.2011
43--
44-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
45--
46LIBRARY ieee;
47USE ieee.std_logic_1164.all;
48USE ieee.std_logic_arith.all;
49USE ieee.numeric_std.all;
50LIBRARY UNISIM;
51--USE UNISIM.Vcomponents.all;
52
53LIBRARY FACT_FAD_lib;
54
55ARCHITECTURE struct OF clock_generator_var_ps IS
56
57 -- Architecture declarations
58
59 -- Internal signal declarations
60 SIGNAL CLK0_OUT : std_logic;
61 SIGNAL LOCKED_OUT : std_logic;
62 SIGNAL PSCLK_IN : std_logic;
63 SIGNAL PSDONE_OUT : std_logic;
64 SIGNAL PSEN_IN : std_logic;
65 SIGNAL PSINCDEC_IN : std_logic;
66
67 -- Implicit buffer signal declarations
68 SIGNAL CLK_25_internal : std_logic;
69
70
71 -- Component Declarations
72 COMPONENT dcm_50_to_25
73 PORT (
74 CLKIN_IN : IN std_logic;
75 CLK0_OUT : OUT std_logic;
76 CLKFX_OUT : OUT std_logic;
77 CLKIN_IBUFG_OUT : OUT std_logic
78 );
79 END COMPONENT;
80 COMPONENT dcm_ps_38ns
81 PORT (
82 CLKIN_IN : IN std_logic;
83 CLK0_OUT : OUT std_logic
84 );
85 END COMPONENT;
86 COMPONENT dcm_var_ps_38ns
87 PORT (
88 CLKIN_IN : IN std_logic;
89 PSCLK_IN : IN std_logic;
90 PSEN_IN : IN std_logic;
91 PSINCDEC_IN : IN std_logic;
92 RST_IN : IN std_logic;
93 CLK0_OUT : OUT std_logic;
94 LOCKED_OUT : OUT std_logic;
95 PSDONE_OUT : OUT std_logic
96 );
97 END COMPONENT;
98 COMPONENT phase_shifter
99 PORT (
100 CLK : IN std_logic ;
101 -- interface to: clock_generator_variable_PS_struct.vhd
102 PSCLK : OUT std_logic ;
103 PSEN : OUT std_logic := '0';
104 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing'
105 PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done.
106 LOCKED : IN std_logic ;
107 -- interface to: w5300_modul.vhd
108 shift_phase : IN std_logic ;
109 direction : IN std_logic ; -- corresponds TO 'PSINCDEC'
110 -- status:
111 shifting : OUT std_logic := '0';
112 ready : OUT std_logic := '0';
113 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
114 DCM_locked : OUT std_logic
115 );
116 END COMPONENT;
117
118 -- Optional embedded configurations
119 -- pragma synthesis_off
120 FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25;
121 FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns;
122 FOR ALL : dcm_var_ps_38ns USE ENTITY FACT_FAD_lib.dcm_var_ps_38ns;
123 FOR ALL : phase_shifter USE ENTITY FACT_FAD_lib.phase_shifter;
124 -- pragma synthesis_on
125
126
127BEGIN
128
129 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
130 PSCLK_OUT <= PSCLK_IN;
131
132 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
133 PSINCDEC_OUT <= PSINCDEC_IN;
134
135 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
136 PSDONE_extraOUT <= PSDONE_OUT;
137
138 -- ModuleWare code(v1.9) for instance 'U_9' of 'assignment'
139 LOCKED_extraOUT <= LOCKED_OUT;
140
141 -- Instance port mappings.
142 U_0 : dcm_50_to_25
143 PORT MAP (
144 CLKIN_IN => CLK,
145 CLKFX_OUT => CLK_25_internal,
146 CLKIN_IBUFG_OUT => OPEN,
147 CLK0_OUT => CLK_50
148 );
149 U_1 : dcm_ps_38ns
150 PORT MAP (
151 CLKIN_IN => CLK_25_internal,
152 CLK0_OUT => CLK0_OUT
153 );
154 U_2 : dcm_var_ps_38ns
155 PORT MAP (
156 CLKIN_IN => CLK0_OUT,
157 PSCLK_IN => PSCLK_IN,
158 PSEN_IN => PSEN_IN,
159 PSINCDEC_IN => PSINCDEC_IN,
160 RST_IN => RST_IN,
161 CLK0_OUT => CLK_25_PS,
162 LOCKED_OUT => LOCKED_OUT,
163 PSDONE_OUT => PSDONE_OUT
164 );
165 U_4 : phase_shifter
166 PORT MAP (
167 CLK => CLK0_OUT,
168 PSCLK => PSCLK_IN,
169 PSEN => PSEN_IN,
170 PSINCDEC => PSINCDEC_IN,
171 PSDONE => PSDONE_OUT,
172 LOCKED => LOCKED_OUT,
173 shift_phase => do_shift,
174 direction => direction,
175 shifting => shifting,
176 ready => ready,
177 offset => offset,
178 DCM_locked => DCM_locked
179 );
180
181 -- Implicit buffered output assignments
182 CLK_25 <= CLK_25_internal;
183
184END struct;
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