source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd@ 9912

Last change on this file since 9912 was 9912, checked in by neise, 12 years ago
most recent version quasi initial commit
File size: 5.7 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.controlRAM_manager.beha
3--
4-- Created:
5-- by - Benjamin Krumm.UNKNOWN (EEPC8)
6-- at - 14:35:46 14.04.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.ALL;
12USE ieee.std_logic_arith.ALL;
13USE ieee.std_logic_unsigned.ALL;
14LIBRARY FACT_FAD_LIB;
15USE FACT_FAD_LIB.fad_definitions.ALL;
16
17ENTITY control_manager IS
18 GENERIC(
19 NO_OF_ROI : integer := 36;
20 NO_OF_DAC : integer := 8;
21 ADDR_WIDTH : integer := 8
22 );
23 PORT(
24 clk : IN std_logic;
25 ram_data_out : IN std_logic_vector (15 DOWNTO 0);
26 config_ready, config_started : OUT std_logic := '0';
27 config_start : IN std_logic;
28 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
29 config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
30 config_wr_en : IN std_logic;
31 config_rd_en : IN std_logic;
32 config_data_valid : OUT std_logic := '0';
33 config_busy : OUT std_logic := '0';
34 ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
35 ram_data_in : OUT std_logic_vector (15 DOWNTO 0);
36 ram_write_en : OUT std_logic_vector (0 DOWNTO 0);
37 dac_array : OUT dac_array_type;
38 roi_array : OUT roi_array_type;
39 drs_address : OUT std_logic_vector (3 DOWNTO 0);
40 drs_address_mode : OUT std_logic
41 );
42
43-- Declarations
44
45END control_manager ;
46
47ARCHITECTURE beha OF control_manager IS
48
49 type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE,
50 CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA,
51 CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA);
52
53 signal ctrl_state : TYPE_CTRL_STATE := CTRL_INIT;
54 signal addr_cntr : integer range 0 to 2**ADDR_WIDTH - 1 := 0;
55 signal int_dac_array : dac_array_type := DEFAULT_DAC;
56 signal int_roi_array : roi_array_type := DEFAULT_ROI;
57 signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR;
58 signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE;
59
60BEGIN
61
62 control_fsm_proc: process (clk)
63 begin
64
65 if rising_edge(clk) then
66
67 config_busy <= '1'; -- is always busy except in idle mode
68
69 case ctrl_state is
70
71 when CTRL_INIT =>
72 -- WRITES DEFAULT VALUES IN config ram
73 addr_cntr <= addr_cntr + 1;
74 ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH);
75 config_data_valid <= '0';
76 config_ready <= '0';
77 ctrl_state <= CTRL_INIT;
78 ram_write_en <= "1";
79 if (addr_cntr < NO_OF_ROI) then
80 ram_data_in <= conv_std_logic_vector(int_roi_array(addr_cntr ), 16);
81 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
82 ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16);
83 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
84 ram_data_in <= "0000" & "0000"
85 & "000" & conv_std_logic_vector(int_drs_address_mode, 1)
86 & int_drs_address;
87 else
88 ram_write_en <= "0";
89 ctrl_state <= CTRL_IDLE;
90 end if;
91
92 when CTRL_IDLE =>
93 --
94 addr_cntr <= 0;
95 ram_write_en <= "0";
96 config_busy <= '0';
97 if (config_start = '1') then
98 config_started <= '1';
99 config_ready <= '0';
100 config_data_valid <= '0';
101 ctrl_state <= CTRL_LOAD_ADDR;
102 end if;
103 if (config_wr_en = '1') then
104 config_busy <= '1';
105 config_data <= (others => 'Z');
106 ctrl_state <= CTRL_WRITE;
107 end if;
108 if (config_rd_en = '1') then
109 ram_addr <= config_addr;
110 config_data_valid <= '0';
111-- ctrl_state <= CTRL_READ_ADDR;
112 ctrl_state <= CTRL_READ_WAIT;
113 end if;
114
115 when CTRL_WAIT_IDLE =>
116 ctrl_state <= CTRL_IDLE;
117
118 when CTRL_LOAD_ADDR =>
119 ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH);
120 ctrl_state <= CTRL_LOAD_WAIT;
121 when CTRL_LOAD_WAIT =>
122 ctrl_state <= CTRL_LOAD_DATA;
123 when CTRL_LOAD_DATA =>
124 addr_cntr <= addr_cntr + 1;
125 if (addr_cntr < NO_OF_ROI) then
126 roi_array(addr_cntr) <= conv_integer(ram_data_out);
127 ctrl_state <= CTRL_LOAD_ADDR;
128 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
129 dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out);
130 ctrl_state <= CTRL_LOAD_ADDR;
131 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
132 drs_address <= ram_data_out(3 downto 0);
133 drs_address_mode <= ram_data_out(4);
134 ctrl_state <= CTRL_LOAD_ADDR;
135 else
136 addr_cntr <= 0;
137 config_started <= '0';
138 config_ready <= '1';
139 ctrl_state <= CTRL_WAIT_IDLE;
140 end if;
141
142 when CTRL_WRITE =>
143 ram_data_in <= config_data;
144 ram_addr <= config_addr;
145 ram_write_en <= "1";
146 ctrl_state <= CTRL_IDLE;
147
148 -- *** IMPORTANT ***
149 -- read address must remain two clock cycles
150 when CTRL_READ_ADDR =>
151 ctrl_state <= CTRL_READ_WAIT;
152 when CTRL_READ_WAIT =>
153 ctrl_state <= CTRL_READ_DATA;
154 when CTRL_READ_DATA =>
155 config_data <= ram_data_out;
156 config_data_valid <= '1';
157 ctrl_state <= CTRL_IDLE;
158
159 end case;
160
161 end if;
162
163 end process control_fsm_proc;
164
165END ARCHITECTURE beha;
166
Note: See TracBrowser for help on using the repository browser.