source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak@ 10121

Last change on this file since 10121 was 10121, checked in by neise, 13 years ago
synchronous trigger handling added continous soft trigger generation. ---> control frequency via 'send 0x21??' each step increases trigger delay by 12.5ms 0x2100 = 40Hz 0x21FF = 0.3Hz
File size: 14.1 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.data_generator.beha
3--
4-- Created:
5-- by - FPGA_Developer.UNKNOWN (EEPC8)
6-- at - 14:36:14 10.02.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12use IEEE.STD_LOGIC_ARITH.ALL;
13use IEEE.STD_LOGIC_UNSIGNED.ALL;
14library fact_fad_lib;
15use fact_fad_lib.fad_definitions.all;
16
17-- -- Uncomment the following library declaration if instantiating
18-- -- any Xilinx primitives in this code.
19-- library UNISIM;
20-- use UNISIM.VComponents.all;
21
22entity data_generator is
23 generic(
24 RAM_ADDR_WIDTH : integer := 12
25 );
26 port(
27-- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
28
29 clk : in std_logic;
30 data_out : out std_logic_vector (63 downto 0);
31 addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
32 write_ea : out std_logic_vector (0 downto 0) := "0";
33 ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
34 ram_write_ea : in std_logic;
35 ram_write_ready : out std_logic := '0';
36 -- --
37 ram_write_ready_ack : IN std_logic;
38 -- --
39 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
40 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
41 config_started_mm, config_started_cm, config_started_spi : in std_logic;
42 roi_array : in roi_array_type;
43 roi_max : in roi_max_type;
44 sensor_array : in sensor_array_type;
45 sensor_ready : in std_logic;
46 dac_array : in dac_array_type;
47 package_length : in std_logic_vector (15 downto 0);
48 board_id : in std_logic_vector (3 downto 0);
49 crate_id : in std_logic_vector (1 downto 0);
50 trigger_id : in std_logic_vector (47 downto 0);
51 trigger : in std_logic;
52-- s_trigger : in std_logic;
53 new_config : in std_logic;
54 config_started : out std_logic := '0';
55 adc_data_array : in adc_data_array_type;
56 adc_oeb : out std_logic := '1';
57 adc_clk_en : out std_logic := '0';
58 adc_otr : in std_logic_vector (3 downto 0);
59 drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
60 -- --
61-- drs_dwrite : out std_logic := '1';
62 drs_readout_ready : out std_logic := '0';
63 -- --
64 drs_clk_en, drs_read_s_cell : out std_logic := '0';
65
66 drs_srin_write_8b : out std_logic := '0';
67 drs_srin_write_ack : in std_logic;
68 drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0');
69 drs_srin_write_ready : in std_logic;
70
71 drs_read_s_cell_ready : in std_logic;
72 drs_s_cell_array : in drs_s_cell_array_type;
73
74 drs_readout_started : out std_logic := '0'
75 );
76end data_generator ;
77
78architecture Behavioral of data_generator is
79
80type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
81 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
82 WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1,
83 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
84
85signal state_generate : state_generate_type := INIT;
86signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
87
88signal data_cntr : integer range 0 to 1024 := 0;
89signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0');
90signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words
91signal channel_id : integer range 0 to 9 := 0;
92signal adc_wait_cnt : integer range 0 to 7 := 0;
93
94signal trigger_flag :std_logic := '0';
95signal ram_write_ea_flag : std_logic := '0';
96signal new_config_int : std_logic := '0';
97
98signal roi_max_int : roi_max_type;
99
100signal sig_drs_readout_started : std_logic := '0';
101
102begin
103
104 drs_readout_started <= sig_drs_readout_started;
105
106 generate_data : process (clk)
107 begin
108 if rising_edge (clk) then
109 trigger_flag <= trigger;
110
111 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH);
112
113 case state_generate is
114 when INIT =>
115 state_generate <= CONFIG;
116
117 when CONFIG =>
118 config_started <= '1';
119 if (new_config = '0') then
120 config_started <= '0';
121 -- config config manager
122 config_start_cm <= '1';
123 if (config_started_cm = '1') then
124 config_start_cm <= '0';
125 state_generate <= CONFIG1;
126 end if;
127 end if;
128 when CONFIG1 =>
129 if (config_ready_cm = '1') then
130 config_start_mm <= '1';
131 end if;
132 if (config_started_mm = '1') then
133 config_start_mm <= '0';
134 state_generate <= CONFIG2;
135 end if;
136 when CONFIG2 =>
137 if (config_ready_mm = '1') then
138 config_start_spi <= '1';
139 end if;
140 if (config_started_spi = '1') then
141 config_start_spi <= '0';
142 state_generate <= CONFIG3;
143 end if;
144 when CONFIG3 =>
145 if (config_ready_spi = '1') then
146 state_generate <= CONFIG4;
147-- state_generate <= WRITE_DATA_IDLE;
148 end if;
149 -- configure DRS
150 when CONFIG4 =>
151 drs_channel_id <= DRS_WRITE_SHIFT_REG;
152 drs_srin_data <= "11111111";
153 drs_srin_write_8b <= '1';
154 if (drs_srin_write_ack = '1') then
155 drs_srin_write_8b <= '0';
156 state_generate <= CONFIG5;
157 end if;
158 when CONFIG5 =>
159 if (drs_srin_write_ready = '1') then
160 roi_max_int <= roi_max;
161 state_generate <= CONFIG6;
162 end if;
163 when CONFIG6 =>
164 drs_channel_id <= DRS_WRITE_CONFIG_REG;
165 drs_srin_data <= "11111111";
166 drs_srin_write_8b <= '1';
167 if (drs_srin_write_ack = '1') then
168 drs_srin_write_8b <= '0';
169 state_generate <= CONFIG7;
170 end if;
171 when CONFIG7 =>
172 if (drs_srin_write_ready = '1') then
173 roi_max_int <= roi_max;
174 state_generate <= WRITE_DATA_IDLE;
175 end if;
176 -- end configure DRS
177
178 when WRITE_DATA_IDLE =>
179 if (new_config = '1') then
180 state_generate <= CONFIG;
181 end if;
182-- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
183 if (ram_write_ea = '1' and trigger_flag = '1') then
184 sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
185 -- stop drs, dwrite low
186 -- drs_dwrite <= '0';
187 -- start reading of drs stop cell
188 drs_read_s_cell <= '1';
189 -- enable adc output
190 adc_oeb <= '0';
191 -- switch on ADC_CLK
192 adc_clk_en <= '1';
193 start_addr <= ram_start_addr;
194 state_generate <= WRITE_HEADER;
195 evnt_cntr <= evnt_cntr + 1;
196 end if;
197 when WRITE_HEADER =>
198 write_ea <= "1";
199 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
200 addr_cntr <= addr_cntr + 3;
201 state_generate <= WRITE_BOARD_ID;
202 when WRITE_BOARD_ID => -- crate ID & board ID
203 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
204 addr_cntr <= addr_cntr + 1;
205 state_generate <= WRITE_TEMPERATURES;
206 when WRITE_TEMPERATURES => -- temperatures
207 if (sensor_ready = '1') then
208 data_out <= conv_std_logic_vector (sensor_array (3), 16)
209 & conv_std_logic_vector (sensor_array (2), 16)
210 & conv_std_logic_vector (sensor_array (1), 16)
211 & conv_std_logic_vector (sensor_array (0), 16);
212 addr_cntr <= addr_cntr + 1;
213 state_generate <= WRITE_DAC1;
214 end if;
215
216 when WRITE_DAC1 =>
217 sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
218 data_out <= conv_std_logic_vector (dac_array (3), 16)
219 & conv_std_logic_vector (dac_array (2), 16)
220 & conv_std_logic_vector (dac_array (1), 16)
221 & conv_std_logic_vector (dac_array (0), 16);
222 addr_cntr <= addr_cntr + 1;
223 state_generate <= WRITE_DAC2;
224 when WRITE_DAC2 =>
225 data_out <= conv_std_logic_vector (dac_array (7), 16)
226 & conv_std_logic_vector (dac_array (6), 16)
227 & conv_std_logic_vector (dac_array (5), 16)
228 & conv_std_logic_vector (dac_array (4), 16);
229 addr_cntr <= addr_cntr + 1;
230 state_generate <= WAIT_FOR_STOP_CELL;
231
232 when WAIT_FOR_STOP_CELL =>
233 drs_read_s_cell <= '0';
234 if (drs_read_s_cell_ready = '1') then
235 state_generate <= START_DRS_READING;
236 end if;
237
238 when START_DRS_READING =>
239 --drs channel number
240 drs_channel_id <= conv_std_logic_vector (channel_id, 4);
241 --starte drs-clocking
242 --adc_oeb <= '0'; -- nur für Emulator
243 drs_clk_en <= '1';
244 adc_wait_cnt <= 0;
245 state_generate <= WRITE_CHANNEL_ID;
246
247 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs
248 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
249 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
250 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
251 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
252 addr_cntr <= addr_cntr + 1;
253 state_generate <= WRITE_START_CELL;
254 when WRITE_START_CELL => -- write start cells
255 data_out <= "000000" & drs_s_cell_array (3)
256 & "000000" & drs_s_cell_array (2)
257 & "000000" & drs_s_cell_array (1)
258 & "000000" & drs_s_cell_array (0);
259 addr_cntr <= addr_cntr + 1;
260 state_generate <= WRITE_ROI;
261 when WRITE_ROI => -- write ROI
262 data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11)
263 & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11)
264 & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11)
265 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
266 addr_cntr <= addr_cntr + 1;
267 state_generate <= WAIT_FOR_ADC;
268 when WAIT_FOR_ADC =>
269 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
270 if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
271 adc_wait_cnt <= adc_wait_cnt + 1;
272 else
273 state_generate <= WRITE_ADC_DATA;
274 end if;
275 when WRITE_ADC_DATA =>
276 if (data_cntr < roi_max (channel_id)) then
277 data_out <= "000" & adc_otr(3) & adc_data_array(3)
278 & "000" & adc_otr(2) & adc_data_array(2)
279 & "000" & adc_otr(1) & adc_data_array(1)
280 & "000" & adc_otr(0) & adc_data_array(0);
281 -- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
282-- & "00010" & conv_std_logic_vector (data_cntr, 11)
283-- & "00100" & conv_std_logic_vector (data_cntr, 11)
284-- & "00110" & conv_std_logic_vector (data_cntr, 11) ;
285 addr_cntr <= addr_cntr + 1;
286 state_generate <= WRITE_ADC_DATA;
287 data_cntr <= data_cntr + 1;
288 else
289 drs_clk_en <= '0';
290 --adc_oeb <= '1'; -- nur für Emulator
291 if (channel_id = 8) then
292 state_generate <= WRITE_EXTERNAL_TRIGGER;
293 adc_oeb <= '1';
294 -- switch off ADC_CLK
295 adc_clk_en <= '0';
296 else
297 channel_id <= channel_id + 1; -- increment channel_id
298 state_generate <= START_DRS_READING;
299 data_cntr <= 0;
300 end if;
301 end if;
302
303
304 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID
305 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
306-- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
307 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
308 state_generate <= WRITE_INTERNAL_TRIGGER;
309 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID
310 addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH);
311 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
312 state_generate <= WRITE_END_FLAG;
313 when WRITE_END_FLAG =>
314 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
315 addr_cntr <= addr_cntr + 1;
316 state_generate <= WRITE_DATA_END;
317 when WRITE_DATA_END =>
318 write_ea <= "0";
319 ram_write_ready <= '1';
320 state_generate <= WRITE_DATA_END_WAIT;
321 when WRITE_DATA_END_WAIT =>
322 -- --
323 if (ram_write_ready_ack = '1') then
324 state_generate <= WRITE_DATA_STOP;
325 -- --
326 ram_write_ready <= '0';
327 -- --
328 end if;
329 -- --
330 when WRITE_DATA_STOP =>
331 -- --
332 if (ram_write_ready_ack = '0') then
333 -- --
334-- drs_dwrite <= '1';
335 drs_readout_ready <= '1';
336 data_cntr <= 0;
337 addr_cntr <= 0;
338 channel_id <= 0;
339 state_generate <= WRITE_DATA_STOP1;
340 -- --
341 end if;
342 -- --
343 when WRITE_DATA_STOP1 =>
344 if (drs_readout_ready_ack = '1') then
345 drs_readout_ready <= '0';
346 state_generate <= WRITE_DATA_IDLE;
347 end if;
348 when others =>
349 null;
350
351 end case; -- state_generate
352 end if; -- rising_edge (clk)
353 end process generate_data;
354
355end Behavioral;
356
357
Note: See TracBrowser for help on using the repository browser.