source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak@ 9912

Last change on this file since 9912 was 9912, checked in by neise, 12 years ago
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1--
2-- VHDL Architecture FACT_FAD_lib.data_generator.beha
3--
4-- Created:
5-- by - FPGA_Developer.UNKNOWN (EEPC8)
6-- at - 14:36:14 10.02.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12use IEEE.STD_LOGIC_ARITH.ALL;
13use IEEE.STD_LOGIC_UNSIGNED.ALL;
14library fact_fad_lib;
15use fact_fad_lib.fad_definitions.all;
16
17-- -- Uncomment the following library declaration if instantiating
18-- -- any Xilinx primitives in this code.
19-- library UNISIM;
20-- use UNISIM.VComponents.all;
21
22entity data_generator is
23 generic(
24 RAM_ADDR_WIDTH : integer := 12
25 );
26 port(
27 clk : in std_logic;
28 data_out : out std_logic_vector (63 downto 0);
29 addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
30 write_ea : out std_logic_vector (0 downto 0) := "0";
31 ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
32 ram_write_ea : in std_logic;
33 ram_write_ready : out std_logic := '0';
34 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
35 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
36 config_started_mm, config_started_cm, config_started_spi : in std_logic;
37 roi_array : in roi_array_type;
38 roi_max : in roi_max_type;
39 sensor_array : in sensor_array_type;
40 sensor_ready : in std_logic;
41 dac_array : in dac_array_type;
42 package_length : in std_logic_vector (15 downto 0);
43 board_id : in std_logic_vector (3 downto 0);
44 crate_id : in std_logic_vector (1 downto 0);
45 trigger_id : in std_logic_vector (47 downto 0);
46 trigger : in std_logic;
47 s_trigger : in std_logic;
48 new_config : in std_logic;
49 config_started : out std_logic := '0';
50 adc_data_array : in adc_data_array_type;
51 adc_oeb : out std_logic := '1';
52 adc_clk_en : out std_logic := '0';
53 adc_otr : in std_logic_vector (3 downto 0);
54 drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
55 drs_dwrite : out std_logic := '1';
56 drs_clk_en, drs_read_s_cell : out std_logic := '0';
57 drs_read_s_cell_ready : in std_logic;
58 drs_s_cell_array : in drs_s_cell_array_type
59 );
60end data_generator ;
61
62architecture Behavioral of data_generator is
63
64type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
65 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
66 WRITE_END_FLAG, WRITE_DATA_STOP,
67 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
68
69signal state_generate : state_generate_type := INIT;
70signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
71
72signal data_cntr : integer range 0 to 1024 := 0;
73signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0');
74signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words
75signal channel_id : integer range 0 to 9 := 0;
76signal adc_wait_cnt : integer range 0 to 7 := 0;
77
78
79begin
80
81
82 generate_data : process (clk)
83 begin
84 if rising_edge (clk) then
85
86 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH);
87
88 case state_generate is
89 when INIT =>
90 state_generate <= CONFIG;
91
92 when CONFIG =>
93 config_started <= '1';
94 -- config config manager
95 config_start_cm <= '1';
96 if (config_started_cm = '1') then
97 state_generate <= CONFIG1;
98 end if;
99 when CONFIG1 =>
100 if (config_ready_cm = '1') then
101 config_started <= '0';
102 config_start_cm <= '0';
103 config_start_mm <= '1';
104 end if;
105 if (config_started_mm = '1') then
106 state_generate <= CONFIG2;
107 end if;
108 when CONFIG2 =>
109 if (config_ready_mm = '1') then
110 config_start_mm <= '0';
111 config_start_spi <= '1';
112 end if;
113 if (config_started_spi = '1') then
114 state_generate <= CONFIG3;
115 end if;
116 when CONFIG3 =>
117 if (config_ready_spi = '1') then
118 config_start_spi <= '0';
119 state_generate <= WRITE_DATA_IDLE;
120 end if;
121
122 when WRITE_DATA_IDLE =>
123 if (new_config = '1') then
124 state_generate <= CONFIG;
125 end if;
126 if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then
127 -- stop drs, dwrite low
128 drs_dwrite <= '0';
129 -- start reading of drs stop cell
130 drs_read_s_cell <= '1';
131 -- enable adc output
132 adc_oeb <= '0';
133 -- switch on ADC_CLK
134 adc_clk_en <= '1';
135 start_addr <= ram_start_addr;
136 state_generate <= WRITE_HEADER;
137 evnt_cntr <= evnt_cntr + 1;
138 end if;
139 when WRITE_HEADER =>
140 write_ea <= "1";
141 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
142 addr_cntr <= addr_cntr + 3;
143 state_generate <= WRITE_BOARD_ID;
144 when WRITE_BOARD_ID => -- crate ID & board ID
145 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
146 addr_cntr <= addr_cntr + 1;
147 state_generate <= WRITE_TEMPERATURES;
148 when WRITE_TEMPERATURES => -- temperatures
149 if (sensor_ready = '1') then
150 data_out <= conv_std_logic_vector (sensor_array (3), 16)
151 & conv_std_logic_vector (sensor_array (2), 16)
152 & conv_std_logic_vector (sensor_array (1), 16)
153 & conv_std_logic_vector (sensor_array (0), 16);
154 addr_cntr <= addr_cntr + 1;
155 state_generate <= WRITE_DAC1;
156 end if;
157
158 when WRITE_DAC1 =>
159 data_out <= conv_std_logic_vector (dac_array (3), 16)
160 & conv_std_logic_vector (dac_array (2), 16)
161 & conv_std_logic_vector (dac_array (1), 16)
162 & conv_std_logic_vector (dac_array (0), 16);
163 addr_cntr <= addr_cntr + 1;
164 state_generate <= WRITE_DAC2;
165 when WRITE_DAC2 =>
166 data_out <= conv_std_logic_vector (dac_array (7), 16)
167 & conv_std_logic_vector (dac_array (6), 16)
168 & conv_std_logic_vector (dac_array (5), 16)
169 & conv_std_logic_vector (dac_array (4), 16);
170 addr_cntr <= addr_cntr + 1;
171 state_generate <= WAIT_FOR_STOP_CELL;
172
173 when WAIT_FOR_STOP_CELL =>
174 drs_read_s_cell <= '0';
175 if (drs_read_s_cell_ready = '1') then
176 state_generate <= START_DRS_READING;
177 end if;
178
179 when START_DRS_READING =>
180 --drs channel number
181 drs_channel_id <= conv_std_logic_vector (channel_id, 4);
182 --starte drs-clocking
183 --adc_oeb <= '0'; -- nur für Emulator
184 drs_clk_en <= '1';
185 adc_wait_cnt <= 0;
186 state_generate <= WRITE_CHANNEL_ID;
187
188 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs
189 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
190 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
191 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
192 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
193 addr_cntr <= addr_cntr + 1;
194 state_generate <= WRITE_START_CELL;
195 when WRITE_START_CELL => -- write start cells
196 data_out <= "000000" & drs_s_cell_array (3)
197 & "000000" & drs_s_cell_array (2)
198 & "000000" & drs_s_cell_array (1)
199 & "000000" & drs_s_cell_array (0);
200 addr_cntr <= addr_cntr + 1;
201 state_generate <= WRITE_ROI;
202 when WRITE_ROI => -- write ROI
203 data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11)
204 & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11)
205 & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11)
206 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
207 addr_cntr <= addr_cntr + 1;
208 state_generate <= WAIT_FOR_ADC;
209 when WAIT_FOR_ADC =>
210 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
211 if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
212 adc_wait_cnt <= adc_wait_cnt + 1;
213 else
214 state_generate <= WRITE_ADC_DATA;
215 end if;
216 when WRITE_ADC_DATA =>
217 if (data_cntr < roi_max (channel_id)) then
218 data_out <= "000" & adc_otr(3) & adc_data_array(3)
219 & "000" & adc_otr(2) & adc_data_array(2)
220 & "000" & adc_otr(1) & adc_data_array(1)
221 & "000" & adc_otr(0) & adc_data_array(0);
222-- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
223-- & "00010" & conv_std_logic_vector (data_cntr, 11)
224-- & "00100" & conv_std_logic_vector (data_cntr, 11)
225-- & "00110" & conv_std_logic_vector (data_cntr, 11) ;
226 addr_cntr <= addr_cntr + 1;
227 state_generate <= WRITE_ADC_DATA;
228 data_cntr <= data_cntr + 1;
229 else
230 drs_clk_en <= '0';
231 --adc_oeb <= '1'; -- nur für Emulator
232 if (channel_id = 8) then
233 state_generate <= WRITE_EXTERNAL_TRIGGER;
234 adc_oeb <= '1';
235 -- switch off ADC_CLK
236 adc_clk_en <= '0';
237 else
238 channel_id <= channel_id + 1; -- increment channel_id
239 state_generate <= START_DRS_READING;
240 data_cntr <= 0;
241 end if;
242 end if;
243
244
245 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID
246 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
247 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
248 state_generate <= WRITE_INTERNAL_TRIGGER;
249 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID
250 addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH);
251 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
252 state_generate <= WRITE_END_FLAG;
253 when WRITE_END_FLAG =>
254 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
255 addr_cntr <= addr_cntr + 1;
256 state_generate <= WRITE_DATA_END;
257 when WRITE_DATA_END =>
258 write_ea <= "0";
259 ram_write_ready <= '1';
260 state_generate <= WRITE_DATA_END_WAIT;
261 when WRITE_DATA_END_WAIT =>
262 state_generate <= WRITE_DATA_STOP;
263 when WRITE_DATA_STOP =>
264 drs_dwrite <= '1';
265 data_cntr <= 0;
266 addr_cntr <= 0;
267 channel_id <= 0;
268 ram_write_ready <= '0';
269 state_generate <= WRITE_DATA_IDLE;
270
271 when others =>
272 null;
273
274 end case; -- state_generate
275 end if; -- rising_edge (clk)
276 end process generate_data;
277
278end Behavioral;
279
280
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