source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd@ 10081

Last change on this file since 10081 was 10081, checked in by neise, 14 years ago
DRS write shift register & write config register
File size: 13.8 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.data_generator.beha
3--
4-- Created:
5-- by - FPGA_Developer.UNKNOWN (EEPC8)
6-- at - 14:36:14 10.02.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12use IEEE.STD_LOGIC_ARITH.ALL;
13use IEEE.STD_LOGIC_UNSIGNED.ALL;
14library fact_fad_lib;
15use fact_fad_lib.fad_definitions.all;
16
17-- -- Uncomment the following library declaration if instantiating
18-- -- any Xilinx primitives in this code.
19-- library UNISIM;
20-- use UNISIM.VComponents.all;
21
22entity data_generator is
23 generic(
24 RAM_ADDR_WIDTH : integer := 12
25 );
26 port(
27-- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
28
29 clk : in std_logic;
30 data_out : out std_logic_vector (63 downto 0);
31 addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
32 write_ea : out std_logic_vector (0 downto 0) := "0";
33 ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
34 ram_write_ea : in std_logic;
35 ram_write_ready : out std_logic := '0';
36 -- --
37 ram_write_ready_ack : IN std_logic;
38 -- --
39 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
40 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
41 config_started_mm, config_started_cm, config_started_spi : in std_logic;
42 roi_array : in roi_array_type;
43 roi_max : in roi_max_type;
44 sensor_array : in sensor_array_type;
45 sensor_ready : in std_logic;
46 dac_array : in dac_array_type;
47 package_length : in std_logic_vector (15 downto 0);
48 board_id : in std_logic_vector (3 downto 0);
49 crate_id : in std_logic_vector (1 downto 0);
50 trigger_id : in std_logic_vector (47 downto 0);
51 trigger : in std_logic;
52-- s_trigger : in std_logic;
53 new_config : in std_logic;
54 config_started : out std_logic := '0';
55 adc_data_array : in adc_data_array_type;
56 adc_oeb : out std_logic := '1';
57 adc_clk_en : out std_logic := '0';
58 adc_otr : in std_logic_vector (3 downto 0);
59 drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
60 drs_dwrite : out std_logic := '1';
61 drs_clk_en, drs_read_s_cell : out std_logic := '0';
62
63 drs_srin_write_8b : out std_logic := '0';
64 drs_srin_write_ack : in std_logic;
65 drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0');
66 drs_srin_write_ready : in std_logic;
67
68 drs_read_s_cell_ready : in std_logic;
69 drs_s_cell_array : in drs_s_cell_array_type;
70
71 drs_readout_started : out std_logic
72 );
73end data_generator ;
74
75architecture Behavioral of data_generator is
76
77type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
78 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
79 WRITE_END_FLAG, WRITE_DATA_STOP,
80 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
81
82signal state_generate : state_generate_type := INIT;
83signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
84
85signal data_cntr : integer range 0 to 1024 := 0;
86signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0');
87signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words
88signal channel_id : integer range 0 to 9 := 0;
89signal adc_wait_cnt : integer range 0 to 7 := 0;
90
91signal trigger_flag :std_logic := '0';
92signal ram_write_ea_flag : std_logic := '0';
93signal new_config_int : std_logic := '0';
94
95signal roi_max_int : roi_max_type;
96
97signal sig_drs_readout_started : std_logic := '0';
98
99begin
100
101 drs_readout_started <= sig_drs_readout_started;
102
103 generate_data : process (clk)
104 begin
105 if rising_edge (clk) then
106 trigger_flag <= trigger;
107
108 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH);
109
110 case state_generate is
111 when INIT =>
112 state_generate <= CONFIG;
113
114 when CONFIG =>
115 config_started <= '1';
116 if (new_config = '0') then
117 config_started <= '0';
118 -- config config manager
119 config_start_cm <= '1';
120 if (config_started_cm = '1') then
121 config_start_cm <= '0';
122 state_generate <= CONFIG1;
123 end if;
124 end if;
125 when CONFIG1 =>
126 if (config_ready_cm = '1') then
127 config_start_mm <= '1';
128 end if;
129 if (config_started_mm = '1') then
130 config_start_mm <= '0';
131 state_generate <= CONFIG2;
132 end if;
133 when CONFIG2 =>
134 if (config_ready_mm = '1') then
135 config_start_spi <= '1';
136 end if;
137 if (config_started_spi = '1') then
138 config_start_spi <= '0';
139 state_generate <= CONFIG3;
140 end if;
141 when CONFIG3 =>
142 if (config_ready_spi = '1') then
143 state_generate <= CONFIG4;
144-- state_generate <= WRITE_DATA_IDLE;
145 end if;
146 -- configure DRS
147 when CONFIG4 =>
148 drs_channel_id <= DRS_WRITE_SHIFT_REG;
149 drs_srin_data <= "11111111";
150 drs_srin_write_8b <= '1';
151 if (drs_srin_write_ack = '1') then
152 drs_srin_write_8b <= '0';
153 state_generate <= CONFIG5;
154 end if;
155 when CONFIG5 =>
156 if (drs_srin_write_ready = '1') then
157 roi_max_int <= roi_max;
158 state_generate <= CONFIG6;
159 end if;
160 when CONFIG6 =>
161 drs_channel_id <= DRS_WRITE_CONFIG_REG;
162 drs_srin_data <= "11111111";
163 drs_srin_write_8b <= '1';
164 if (drs_srin_write_ack = '1') then
165 drs_srin_write_8b <= '0';
166 state_generate <= CONFIG7;
167 end if;
168 when CONFIG7 =>
169 if (drs_srin_write_ready = '1') then
170 roi_max_int <= roi_max;
171 state_generate <= WRITE_DATA_IDLE;
172 end if;
173 -- end configure DRS
174
175 when WRITE_DATA_IDLE =>
176 if (new_config = '1') then
177 state_generate <= CONFIG;
178 end if;
179-- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
180 if (ram_write_ea = '1' and trigger_flag = '1') then
181 sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
182 -- stop drs, dwrite low
183 drs_dwrite <= '0';
184 -- start reading of drs stop cell
185 drs_read_s_cell <= '1';
186 -- enable adc output
187 adc_oeb <= '0';
188 -- switch on ADC_CLK
189 adc_clk_en <= '1';
190 start_addr <= ram_start_addr;
191 state_generate <= WRITE_HEADER;
192 evnt_cntr <= evnt_cntr + 1;
193 end if;
194 when WRITE_HEADER =>
195 write_ea <= "1";
196 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
197 addr_cntr <= addr_cntr + 3;
198 state_generate <= WRITE_BOARD_ID;
199 when WRITE_BOARD_ID => -- crate ID & board ID
200 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
201 addr_cntr <= addr_cntr + 1;
202 state_generate <= WRITE_TEMPERATURES;
203 when WRITE_TEMPERATURES => -- temperatures
204 if (sensor_ready = '1') then
205 data_out <= conv_std_logic_vector (sensor_array (3), 16)
206 & conv_std_logic_vector (sensor_array (2), 16)
207 & conv_std_logic_vector (sensor_array (1), 16)
208 & conv_std_logic_vector (sensor_array (0), 16);
209 addr_cntr <= addr_cntr + 1;
210 state_generate <= WRITE_DAC1;
211 end if;
212
213 when WRITE_DAC1 =>
214 sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
215 data_out <= conv_std_logic_vector (dac_array (3), 16)
216 & conv_std_logic_vector (dac_array (2), 16)
217 & conv_std_logic_vector (dac_array (1), 16)
218 & conv_std_logic_vector (dac_array (0), 16);
219 addr_cntr <= addr_cntr + 1;
220 state_generate <= WRITE_DAC2;
221 when WRITE_DAC2 =>
222 data_out <= conv_std_logic_vector (dac_array (7), 16)
223 & conv_std_logic_vector (dac_array (6), 16)
224 & conv_std_logic_vector (dac_array (5), 16)
225 & conv_std_logic_vector (dac_array (4), 16);
226 addr_cntr <= addr_cntr + 1;
227 state_generate <= WAIT_FOR_STOP_CELL;
228
229 when WAIT_FOR_STOP_CELL =>
230 drs_read_s_cell <= '0';
231 if (drs_read_s_cell_ready = '1') then
232 state_generate <= START_DRS_READING;
233 end if;
234
235 when START_DRS_READING =>
236 --drs channel number
237 drs_channel_id <= conv_std_logic_vector (channel_id, 4);
238 --starte drs-clocking
239 --adc_oeb <= '0'; -- nur für Emulator
240 drs_clk_en <= '1';
241 adc_wait_cnt <= 0;
242 state_generate <= WRITE_CHANNEL_ID;
243
244 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs
245 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
246 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
247 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
248 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
249 addr_cntr <= addr_cntr + 1;
250 state_generate <= WRITE_START_CELL;
251 when WRITE_START_CELL => -- write start cells
252 data_out <= "000000" & drs_s_cell_array (3)
253 & "000000" & drs_s_cell_array (2)
254 & "000000" & drs_s_cell_array (1)
255 & "000000" & drs_s_cell_array (0);
256 addr_cntr <= addr_cntr + 1;
257 state_generate <= WRITE_ROI;
258 when WRITE_ROI => -- write ROI
259 data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11)
260 & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11)
261 & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11)
262 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
263 addr_cntr <= addr_cntr + 1;
264 state_generate <= WAIT_FOR_ADC;
265 when WAIT_FOR_ADC =>
266 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
267 if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
268 adc_wait_cnt <= adc_wait_cnt + 1;
269 else
270 state_generate <= WRITE_ADC_DATA;
271 end if;
272 when WRITE_ADC_DATA =>
273 if (data_cntr < roi_max (channel_id)) then
274 data_out <= "000" & adc_otr(3) & adc_data_array(3)
275 & "000" & adc_otr(2) & adc_data_array(2)
276 & "000" & adc_otr(1) & adc_data_array(1)
277 & "000" & adc_otr(0) & adc_data_array(0);
278 -- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
279-- & "00010" & conv_std_logic_vector (data_cntr, 11)
280-- & "00100" & conv_std_logic_vector (data_cntr, 11)
281-- & "00110" & conv_std_logic_vector (data_cntr, 11) ;
282 addr_cntr <= addr_cntr + 1;
283 state_generate <= WRITE_ADC_DATA;
284 data_cntr <= data_cntr + 1;
285 else
286 drs_clk_en <= '0';
287 --adc_oeb <= '1'; -- nur für Emulator
288 if (channel_id = 8) then
289 state_generate <= WRITE_EXTERNAL_TRIGGER;
290 adc_oeb <= '1';
291 -- switch off ADC_CLK
292 adc_clk_en <= '0';
293 else
294 channel_id <= channel_id + 1; -- increment channel_id
295 state_generate <= START_DRS_READING;
296 data_cntr <= 0;
297 end if;
298 end if;
299
300
301 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID
302 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
303-- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
304 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
305 state_generate <= WRITE_INTERNAL_TRIGGER;
306 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID
307 addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH);
308 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
309 state_generate <= WRITE_END_FLAG;
310 when WRITE_END_FLAG =>
311 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
312 addr_cntr <= addr_cntr + 1;
313 state_generate <= WRITE_DATA_END;
314 when WRITE_DATA_END =>
315 write_ea <= "0";
316 ram_write_ready <= '1';
317 state_generate <= WRITE_DATA_END_WAIT;
318 when WRITE_DATA_END_WAIT =>
319 -- --
320 if (ram_write_ready_ack = '1') then
321 state_generate <= WRITE_DATA_STOP;
322 -- --
323 ram_write_ready <= '0';
324 -- --
325 end if;
326 -- --
327 when WRITE_DATA_STOP =>
328 -- --
329 if (ram_write_ready_ack = '0') then
330 -- --
331 drs_dwrite <= '1';
332 data_cntr <= 0;
333 addr_cntr <= 0;
334 channel_id <= 0;
335 state_generate <= WRITE_DATA_IDLE;
336 -- --
337 end if;
338 -- --
339 when others =>
340 null;
341
342 end case; -- state_generate
343 end if; -- rising_edge (clk)
344 end process generate_data;
345
346end Behavioral;
347
348
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