source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd@ 9912

Last change on this file since 9912 was 9912, checked in by neise, 12 years ago
most recent version quasi initial commit
File size: 11.5 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.data_generator.beha
3--
4-- Created:
5-- by - FPGA_Developer.UNKNOWN (EEPC8)
6-- at - 14:36:14 10.02.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12use IEEE.STD_LOGIC_ARITH.ALL;
13use IEEE.STD_LOGIC_UNSIGNED.ALL;
14library fact_fad_lib;
15use fact_fad_lib.fad_definitions.all;
16
17-- -- Uncomment the following library declaration if instantiating
18-- -- any Xilinx primitives in this code.
19-- library UNISIM;
20-- use UNISIM.VComponents.all;
21
22entity data_generator is
23 generic(
24 RAM_ADDR_WIDTH : integer := 12
25 );
26 port(
27 clk : in std_logic;
28 data_out : out std_logic_vector (63 downto 0);
29 addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
30 write_ea : out std_logic_vector (0 downto 0) := "0";
31 ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
32 ram_write_ea : in std_logic;
33 ram_write_ready : out std_logic := '0';
34 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
35 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
36 config_started_mm, config_started_cm, config_started_spi : in std_logic;
37 roi_array : in roi_array_type;
38 roi_max : in roi_max_type;
39 sensor_array : in sensor_array_type;
40 sensor_ready : in std_logic;
41 dac_array : in dac_array_type;
42 package_length : in std_logic_vector (15 downto 0);
43 board_id : in std_logic_vector (3 downto 0);
44 crate_id : in std_logic_vector (1 downto 0);
45 trigger_id : in std_logic_vector (47 downto 0);
46 trigger : in std_logic;
47 s_trigger : in std_logic;
48 new_config : in std_logic;
49 config_started : out std_logic := '0';
50 adc_data_array : in adc_data_array_type;
51 adc_oeb : out std_logic := '1';
52 adc_clk_en : out std_logic := '0';
53 adc_otr : in std_logic_vector (3 downto 0);
54 drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
55 drs_dwrite : out std_logic := '1';
56 drs_clk_en, drs_read_s_cell : out std_logic := '0';
57 drs_read_s_cell_ready : in std_logic;
58 drs_s_cell_array : in drs_s_cell_array_type
59 );
60end data_generator ;
61
62architecture Behavioral of data_generator is
63
64type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
65 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
66 WRITE_END_FLAG, WRITE_DATA_STOP,
67 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
68
69signal state_generate : state_generate_type := INIT;
70signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
71
72signal data_cntr : integer range 0 to 1024 := 0;
73signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0');
74signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words
75signal channel_id : integer range 0 to 9 := 0;
76signal adc_wait_cnt : integer range 0 to 7 := 0;
77
78signal trigger_flag : std_logic := '0';
79
80
81begin
82
83
84 generate_data : process (clk)
85 begin
86 if rising_edge (clk) then
87 trigger_flag <= trigger;
88
89 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH);
90
91 case state_generate is
92 when INIT =>
93 state_generate <= CONFIG;
94
95 when CONFIG =>
96 config_started <= '1';
97 -- config config manager
98 config_start_cm <= '1';
99 if (config_started_cm = '1') then
100 state_generate <= CONFIG1;
101 end if;
102 when CONFIG1 =>
103 if (config_ready_cm = '1') then
104 config_started <= '0';
105 config_start_cm <= '0';
106 config_start_mm <= '1';
107 end if;
108 if (config_started_mm = '1') then
109 state_generate <= CONFIG2;
110 end if;
111 when CONFIG2 =>
112 if (config_ready_mm = '1') then
113 config_start_mm <= '0';
114 config_start_spi <= '1';
115 end if;
116 if (config_started_spi = '1') then
117 state_generate <= CONFIG3;
118 end if;
119 when CONFIG3 =>
120 if (config_ready_spi = '1') then
121 config_start_spi <= '0';
122 state_generate <= WRITE_DATA_IDLE;
123 end if;
124
125 when WRITE_DATA_IDLE =>
126 if (new_config = '1') then
127 state_generate <= CONFIG;
128 end if;
129 if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
130 -- stop drs, dwrite low
131 drs_dwrite <= '0';
132 -- start reading of drs stop cell
133 drs_read_s_cell <= '1';
134 -- enable adc output
135 adc_oeb <= '0';
136 -- switch on ADC_CLK
137 adc_clk_en <= '1';
138 start_addr <= ram_start_addr;
139 state_generate <= WRITE_HEADER;
140 evnt_cntr <= evnt_cntr + 1;
141 end if;
142 when WRITE_HEADER =>
143 write_ea <= "1";
144 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
145 addr_cntr <= addr_cntr + 3;
146 state_generate <= WRITE_BOARD_ID;
147 when WRITE_BOARD_ID => -- crate ID & board ID
148 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
149 addr_cntr <= addr_cntr + 1;
150 state_generate <= WRITE_TEMPERATURES;
151 when WRITE_TEMPERATURES => -- temperatures
152 if (sensor_ready = '1') then
153 data_out <= conv_std_logic_vector (sensor_array (3), 16)
154 & conv_std_logic_vector (sensor_array (2), 16)
155 & conv_std_logic_vector (sensor_array (1), 16)
156 & conv_std_logic_vector (sensor_array (0), 16);
157 addr_cntr <= addr_cntr + 1;
158 state_generate <= WRITE_DAC1;
159 end if;
160
161 when WRITE_DAC1 =>
162 data_out <= conv_std_logic_vector (dac_array (3), 16)
163 & conv_std_logic_vector (dac_array (2), 16)
164 & conv_std_logic_vector (dac_array (1), 16)
165 & conv_std_logic_vector (dac_array (0), 16);
166 addr_cntr <= addr_cntr + 1;
167 state_generate <= WRITE_DAC2;
168 when WRITE_DAC2 =>
169 data_out <= conv_std_logic_vector (dac_array (7), 16)
170 & conv_std_logic_vector (dac_array (6), 16)
171 & conv_std_logic_vector (dac_array (5), 16)
172 & conv_std_logic_vector (dac_array (4), 16);
173 addr_cntr <= addr_cntr + 1;
174 state_generate <= WAIT_FOR_STOP_CELL;
175
176 when WAIT_FOR_STOP_CELL =>
177 drs_read_s_cell <= '0';
178 if (drs_read_s_cell_ready = '1') then
179 state_generate <= START_DRS_READING;
180 end if;
181
182 when START_DRS_READING =>
183 --drs channel number
184 drs_channel_id <= conv_std_logic_vector (channel_id, 4);
185 --starte drs-clocking
186 --adc_oeb <= '0'; -- nur für Emulator
187 drs_clk_en <= '1';
188 adc_wait_cnt <= 0;
189 state_generate <= WRITE_CHANNEL_ID;
190
191 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs
192 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
193 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
194 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
195 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
196 addr_cntr <= addr_cntr + 1;
197 state_generate <= WRITE_START_CELL;
198 when WRITE_START_CELL => -- write start cells
199 data_out <= "000000" & drs_s_cell_array (3)
200 & "000000" & drs_s_cell_array (2)
201 & "000000" & drs_s_cell_array (1)
202 & "000000" & drs_s_cell_array (0);
203 addr_cntr <= addr_cntr + 1;
204 state_generate <= WRITE_ROI;
205 when WRITE_ROI => -- write ROI
206 data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11)
207 & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11)
208 & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11)
209 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
210 addr_cntr <= addr_cntr + 1;
211 state_generate <= WAIT_FOR_ADC;
212 when WAIT_FOR_ADC =>
213 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
214 if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
215 adc_wait_cnt <= adc_wait_cnt + 1;
216 else
217 state_generate <= WRITE_ADC_DATA;
218 end if;
219 when WRITE_ADC_DATA =>
220 if (data_cntr < roi_max (channel_id)) then
221 data_out <= "000" & adc_otr(3) & adc_data_array(3)
222 & "000" & adc_otr(2) & adc_data_array(2)
223 & "000" & adc_otr(1) & adc_data_array(1)
224 & "000" & adc_otr(0) & adc_data_array(0);
225-- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
226-- & "00010" & conv_std_logic_vector (data_cntr, 11)
227-- & "00100" & conv_std_logic_vector (data_cntr, 11)
228-- & "00110" & conv_std_logic_vector (data_cntr, 11) ;
229 addr_cntr <= addr_cntr + 1;
230 state_generate <= WRITE_ADC_DATA;
231 data_cntr <= data_cntr + 1;
232 else
233 drs_clk_en <= '0';
234 --adc_oeb <= '1'; -- nur für Emulator
235 if (channel_id = 8) then
236 state_generate <= WRITE_EXTERNAL_TRIGGER;
237 adc_oeb <= '1';
238 -- switch off ADC_CLK
239 adc_clk_en <= '0';
240 else
241 channel_id <= channel_id + 1; -- increment channel_id
242 state_generate <= START_DRS_READING;
243 data_cntr <= 0;
244 end if;
245 end if;
246
247
248 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID
249 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
250 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
251 state_generate <= WRITE_INTERNAL_TRIGGER;
252 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID
253 addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH);
254 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
255 state_generate <= WRITE_END_FLAG;
256 when WRITE_END_FLAG =>
257 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
258 addr_cntr <= addr_cntr + 1;
259 state_generate <= WRITE_DATA_END;
260 when WRITE_DATA_END =>
261 write_ea <= "0";
262 ram_write_ready <= '1';
263 state_generate <= WRITE_DATA_END_WAIT;
264 when WRITE_DATA_END_WAIT =>
265 state_generate <= WRITE_DATA_STOP;
266 when WRITE_DATA_STOP =>
267 drs_dwrite <= '1';
268 data_cntr <= 0;
269 addr_cntr <= 0;
270 channel_id <= 0;
271 ram_write_ready <= '0';
272 state_generate <= WRITE_DATA_IDLE;
273
274 when others =>
275 null;
276
277 end case; -- state_generate
278 end if; -- rising_edge (clk)
279 end process generate_data;
280
281end Behavioral;
282
283
Note: See TracBrowser for help on using the repository browser.