source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd@ 9912

Last change on this file since 9912 was 9912, checked in by neise, 12 years ago
most recent version quasi initial commit
File size: 2.7 KB
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1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3use IEEE.STD_LOGIC_ARITH.ALL;
4use IEEE.std_logic_signed.all;
5
6library fact_fad_lib;
7use fact_fad_lib.fad_definitions.all;
8
9
10ENTITY drs_pulser is
11 port (
12 CLK : in std_logic;
13
14 start_endless_mode : in std_logic;
15 start_read_stop_pos_mode : in std_logic;
16
17 SROUT_in_0 : in std_logic;
18 SROUT_in_1 : in std_logic;
19 SROUT_in_2 : in std_logic;
20 SROUT_in_3 : in std_logic;
21
22 stop_pos : out drs_s_cell_array_type;
23 stop_pos_valid : out std_logic := '0';
24
25 RSRLOAD : out std_logic := '0';
26 SRCLK : out std_logic := '0'
27 );
28end drs_pulser;
29
30
31ARCHITECTURE behavior of drs_pulser IS
32
33type state_main_type is (MAIN, READ_STOP_POS, ENDLESS_MODE);
34signal state_main : state_main_type := MAIN;
35signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0;
36
37signal stop_pos_int : drs_s_cell_array_type;
38signal RSRLOAD_EN, SRCLK_EN : std_logic := '0';
39
40begin
41
42
43 main_proc: process (clk) begin
44
45 RSRLOAD <= (clk and RSRLOAD_EN);
46 SRCLK <= (clk and SRCLK_EN);
47
48 if rising_edge(clk) then
49 case state_main is
50 when MAIN =>
51 if (start_read_stop_pos_mode = '1') then
52 RSRLOAD_EN <= '1';
53 stop_pos_valid <= '0';
54 state_main <= READ_STOP_POS;
55 end if;
56 if (start_endless_mode = '1') then
57 RSRLOAD_EN <= '1';
58 state_main <= ENDLESS_MODE;
59 end if;
60
61 when ENDLESS_MODE =>
62 RSRLOAD_EN <= '0';
63 if (wait_cntr = 3) then
64 SRCLK_EN <= '1';
65 else
66 wait_cntr <= wait_cntr + 1;
67 end if;
68 if (start_endless_mode = '0') then
69 SRCLK_EN <= '0';
70 wait_cntr <= 0;
71 state_main <= MAIN;
72 end if;
73
74 when READ_STOP_POS =>
75 RSRLOAD_EN <= '0';
76 if (stop_pos_cntr = 10) then
77 stop_pos (0) <= stop_pos_int (0);
78 stop_pos (1) <= stop_pos_int (1);
79 stop_pos (2) <= stop_pos_int (2);
80 stop_pos (3) <= stop_pos_int (3);
81 stop_pos_valid <= '1';
82 stop_pos_cntr <= 0;
83 SRCLK_EN <= '0';
84 state_main <= MAIN;
85 else
86 SRCLK_EN <= '1';
87 stop_pos_int (0) <= stop_pos_int (0) (8 downto 0) & SROUT_in_0;
88 stop_pos_int (1) <= stop_pos_int (1) (8 downto 0) & SROUT_in_1;
89 stop_pos_int (2) <= stop_pos_int (2) (8 downto 0) & SROUT_in_2;
90 stop_pos_int (3) <= stop_pos_int (3) (8 downto 0) & SROUT_in_3;
91 stop_pos_cntr <= stop_pos_cntr + 1;
92 end if;
93
94 end case; -- state_main
95 end if;
96
97 end process main_proc;
98
99end behavior;
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