source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd@ 10073

Last change on this file since 10073 was 10073, checked in by neise, 12 years ago
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1-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 17:00:27 03.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY FAD_Board IS
14 PORT(
15 A0_D : IN std_logic_vector (11 DOWNTO 0);
16 A1_D : IN std_logic_vector (11 DOWNTO 0);
17 A2_D : IN std_logic_vector (11 DOWNTO 0);
18 A3_D : IN std_logic_vector (11 DOWNTO 0);
19 A_OTR : IN std_logic_vector (3 DOWNTO 0);
20 D0_SROUT : IN std_logic;
21 D1_SROUT : IN std_logic;
22 D2_SROUT : IN std_logic;
23 D3_SROUT : IN std_logic;
24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0);
25 RS485_C_DI : IN std_logic;
26 RS485_E_DI : IN std_logic;
27 RS485_E_DO : IN std_logic;
28 TRG : IN STD_LOGIC;
29 W_INT : IN std_logic;
30 X_50M : IN STD_LOGIC;
31 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
32 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
33 A_CLK : OUT std_logic_vector (3 DOWNTO 0);
34 D0_SRCLK : OUT STD_LOGIC;
35 D1_SRCLK : OUT STD_LOGIC;
36 D2_SRCLK : OUT STD_LOGIC;
37 D3_SRCLK : OUT STD_LOGIC;
38 DAC_CS : OUT std_logic;
39 DENABLE : OUT std_logic := '0';
40 DWRITE : OUT std_logic := '0';
41 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
42 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
43 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
44 EE_CS : OUT std_logic;
45 LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1');
46 MOSI : OUT std_logic := '0';
47 OE_ADC : OUT STD_LOGIC;
48 RS485_C_DE : OUT std_logic;
49 RS485_C_DO : OUT std_logic;
50 RS485_C_RE : OUT std_logic;
51 RS485_E_DE : OUT std_logic;
52 RS485_E_RE : OUT std_logic;
53 RSRLOAD : OUT std_logic := '0';
54 SRIN : OUT std_logic := '0';
55 S_CLK : OUT std_logic;
56 T0_CS : OUT std_logic;
57 T1_CS : OUT std_logic;
58 T2_CS : OUT std_logic;
59 T3_CS : OUT std_logic;
60 TRG_V : OUT std_logic;
61 W_A : OUT std_logic_vector (9 DOWNTO 0);
62 W_CS : OUT std_logic := '1';
63 W_RD : OUT std_logic := '1';
64 W_RES : OUT std_logic := '1';
65 W_WR : OUT std_logic := '1';
66 MISO : INOUT std_logic;
67 W_D : INOUT std_logic_vector (15 DOWNTO 0)
68 );
69
70-- Declarations
71
72END FAD_Board ;
73
74--
75-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct
76--
77-- Created:
78-- by - dneise.UNKNOWN (E5B-LABOR6)
79-- at - 17:00:27 03.01.2011
80--
81-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
82--
83LIBRARY ieee;
84USE ieee.std_logic_1164.all;
85USE ieee.std_logic_arith.all;
86USE IEEE.NUMERIC_STD.all;
87USE ieee.std_logic_unsigned.all;
88
89LIBRARY FACT_FAD_lib;
90USE FACT_FAD_lib.fad_definitions.all;
91
92LIBRARY FACT_FAD_lib;
93
94ARCHITECTURE struct OF FAD_Board IS
95
96 -- Architecture declarations
97
98 -- Internal signal declarations
99 SIGNAL CLK25_OUT : std_logic;
100 SIGNAL CLK25_PSOUT : std_logic;
101 SIGNAL CLK50_OUT : std_logic;
102 SIGNAL CLK_25_PS : std_logic;
103 SIGNAL CLK_25_PS1 : std_logic;
104 SIGNAL CLK_50 : std_logic;
105 SIGNAL DCM_locked : std_logic;
106 SIGNAL LOCKED_extraOUT : std_logic;
107 SIGNAL PSCLK_OUT : std_logic;
108 SIGNAL PSDONE_extraOUT : std_logic;
109 SIGNAL PSEN_OUT : std_logic;
110 SIGNAL PSINCDEC_OUT : std_logic;
111 SIGNAL PS_DIR_IN : std_logic;
112 SIGNAL PS_DO_IN : std_logic;
113 SIGNAL SRCLK : std_logic := '0';
114 SIGNAL adc_clk_en : std_logic := '0';
115 SIGNAL adc_data_array : adc_data_array_type;
116 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
117 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
118 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
119 SIGNAL dummy : std_logic;
120 SIGNAL ready : std_logic := '0';
121 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
122 -- status:
123 SIGNAL shifting : std_logic := '0';
124
125
126 -- Component Declarations
127 COMPONENT FAD_main
128 GENERIC (
129 RAMADDRWIDTH64b : integer := 12
130 );
131 PORT (
132 CLK : IN std_logic ;
133 SROUT_in_0 : IN std_logic ;
134 SROUT_in_1 : IN std_logic ;
135 SROUT_in_2 : IN std_logic ;
136 SROUT_in_3 : IN std_logic ;
137 adc_data_array : IN adc_data_array_type ;
138 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
139 board_id : IN std_logic_vector (3 DOWNTO 0);
140 crate_id : IN std_logic_vector (1 DOWNTO 0);
141 trigger : IN std_logic ;
142 wiz_int : IN std_logic ;
143 CLK25_OUT : OUT std_logic ;
144 CLK25_PSOUT : OUT std_logic ;
145 CLK50_OUT : OUT std_logic ;
146 CLK_25_PS : OUT std_logic ;
147 CLK_50 : OUT std_logic ;
148 DCM_locked : OUT std_logic ;
149 LOCKED_extraOUT : OUT std_logic ;
150 PSCLK_OUT : OUT std_logic ;
151 PSDONE_extraOUT : OUT std_logic ;
152 PSEN_OUT : OUT std_logic ;
153 PSINCDEC_OUT : OUT std_logic ;
154 PS_DIR_IN : OUT std_logic ;
155 PS_DO_IN : OUT std_logic ;
156 RSRLOAD : OUT std_logic := '0';
157 SRCLK : OUT std_logic := '0';
158 SRIN_out : OUT std_logic := '0';
159 adc_clk_en : OUT std_logic := '0';
160 adc_oeb : OUT std_logic := '1';
161 dac_cs : OUT std_logic ;
162 denable : OUT std_logic := '0'; -- default domino wave off
163 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
164 drs_dwrite : OUT std_logic := '1';
165 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
166 mosi : OUT std_logic := '0';
167 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
168 ready : OUT std_logic := '0';
169 sclk : OUT std_logic ;
170 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
171 -- status:
172 shifting : OUT std_logic := '0';
173 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
174 wiz_cs : OUT std_logic := '1';
175 wiz_rd : OUT std_logic := '1';
176 wiz_reset : OUT std_logic := '1';
177 wiz_wr : OUT std_logic := '1';
178 sio : INOUT std_logic ;
179 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
180 );
181 END COMPONENT;
182
183 -- Optional embedded configurations
184 -- pragma synthesis_off
185 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
186 -- pragma synthesis_on
187
188
189BEGIN
190 -- Architecture concurrent statements
191 -- HDL Embedded Text Block 1 eb_ID
192 -- hard-wired IDs
193 board_id <= "0101";
194 crate_id <= "01";
195
196 -- HDL Embedded Text Block 2 ADC_CLK
197 -- ADC_CLK 2
198 A_CLK (0) <= CLK_25_PS;
199 A_CLK (1) <= CLK_25_PS;
200 A_CLK (2) <= CLK_25_PS;
201 A_CLK (3) <= CLK_25_PS;
202
203 -- HDL Embedded Text Block 3 ADC_DATA
204 -- ADC_DATA 3
205 adc_data_array (0) <= A0_D;
206 adc_data_array (1) <= A1_D;
207 adc_data_array (2) <= A2_D;
208 adc_data_array (3) <= A3_D;
209
210 -- HDL Embedded Text Block 4 SRCLK
211 -- SRCLK 4
212 D0_SRCLK <= SRCLK;
213 D1_SRCLK <= SRCLK;
214 D2_SRCLK <= SRCLK;
215 D3_SRCLK <= SRCLK;
216
217 -- HDL Embedded Text Block 5 T_CS
218 -- T_CS 5
219 T0_CS <= sensor_cs (0);
220 T1_CS <= sensor_cs (1);
221 T2_CS <= sensor_cs (2);
222 T3_CS <= sensor_cs (3);
223
224 -- HDL Embedded Text Block 6 MISC
225 -- MISC 6
226 TRG_V <= '0';
227 RS485_C_RE <= '0';
228 RS485_C_DE <= '0';
229 RS485_C_DO <= RS485_C_DI;
230
231 RS485_E_RE <= '0';
232 RS485_E_DE <= '0';
233 --RS485_E_DO <= RS485_E_DI;
234
235 -- DENABLE <= '0'; -- domino wave stopped
236 -- DENABLE <= '1'; -- domino wave running
237
238
239 EE_CS <= '1';
240 -- LEDs are low active
241 LED(0) <= '1';
242 LED(1) <= '0'; -- on
243 LED(2) <= '1';
244
245
246
247
248 -- HDL Embedded Text Block 7 eb1
249 D_T2 <= D_PLLLCK;
250
251 -- HDL Embedded Text Block 8 eb2
252 -- eb2 8
253 D_A <= drs_channel_id;
254
255 -- HDL Embedded Text Block 9 eb3
256 -- eb3 9
257 A0_T(0) <= CLK50_OUT;
258 A0_T(1) <= CLK25_OUT;
259 A0_T(2) <= CLK25_PSOUT;
260 A0_T(3) <= PS_DIR_IN;
261 A0_T(4) <= PS_DO_IN;
262 A0_T(5) <= PSINCDEC_OUT;
263 A0_T(6) <= PSEN_OUT;
264 A0_T(7) <= DCM_locked;
265
266 A1_T(0) <= ready;
267 A1_T(1) <= shifting;
268 A1_T(2) <= PSDONE_extraOUT;
269 A1_T(3) <= PSCLK_OUT;
270 A1_T(4) <= LOCKED_extraOUT;
271
272 A1_T(5) <= '0';
273 A1_T(6) <= '0';
274 A1_T(7) <= '0';
275
276
277 -- ModuleWare code(v1.9) for instance 'I0' of 'and'
278 CLK_25_PS <= adc_clk_en AND CLK_25_PS1;
279
280 -- ModuleWare code(v1.9) for instance 'I3' of 'assignment'
281 DAC_CS <= dummy;
282
283 -- Instance port mappings.
284 I_board_main : FAD_main
285 GENERIC MAP (
286 RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B
287 )
288 PORT MAP (
289 CLK => X_50M,
290 SROUT_in_0 => D0_SROUT,
291 SROUT_in_1 => D1_SROUT,
292 SROUT_in_2 => D2_SROUT,
293 SROUT_in_3 => D3_SROUT,
294 adc_data_array => adc_data_array,
295 adc_otr_array => A_OTR,
296 board_id => board_id,
297 crate_id => crate_id,
298 trigger => TRG,
299 wiz_int => W_INT,
300 CLK25_OUT => CLK25_OUT,
301 CLK25_PSOUT => CLK25_PSOUT,
302 CLK50_OUT => CLK50_OUT,
303 CLK_25_PS => CLK_25_PS1,
304 CLK_50 => CLK_50,
305 DCM_locked => DCM_locked,
306 LOCKED_extraOUT => LOCKED_extraOUT,
307 PSCLK_OUT => PSCLK_OUT,
308 PSDONE_extraOUT => PSDONE_extraOUT,
309 PSEN_OUT => PSEN_OUT,
310 PSINCDEC_OUT => PSINCDEC_OUT,
311 PS_DIR_IN => PS_DIR_IN,
312 PS_DO_IN => PS_DO_IN,
313 RSRLOAD => RSRLOAD,
314 SRCLK => SRCLK,
315 SRIN_out => SRIN,
316 adc_clk_en => adc_clk_en,
317 adc_oeb => OE_ADC,
318 dac_cs => dummy,
319 denable => DENABLE,
320 drs_channel_id => drs_channel_id,
321 drs_dwrite => DWRITE,
322 led => D_T,
323 mosi => MOSI,
324 offset => OPEN,
325 ready => ready,
326 sclk => S_CLK,
327 sensor_cs => sensor_cs,
328 shifting => shifting,
329 wiz_addr => W_A,
330 wiz_cs => W_CS,
331 wiz_rd => W_RD,
332 wiz_reset => W_RES,
333 wiz_wr => W_WR,
334 sio => MISO,
335 wiz_data => W_D
336 );
337
338END struct;
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