1   VHDL Entity FACT_FAD_lib.FAD_Board.symbol


2  


3   Created:


4   by  dneise.UNKNOWN (E5BLABOR6)


5   at  12:19:07 05.01.2011


6  


7   Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)


8  


9  LIBRARY ieee;


10  USE ieee.std_logic_1164.all;


11  USE ieee.std_logic_arith.all;


12 


13  ENTITY FAD_Board IS


14  PORT(


15  A0_D : IN std_logic_vector (11 DOWNTO 0);


16  A1_D : IN std_logic_vector (11 DOWNTO 0);


17  A2_D : IN std_logic_vector (11 DOWNTO 0);


18  A3_D : IN std_logic_vector (11 DOWNTO 0);


19  A_OTR : IN std_logic_vector (3 DOWNTO 0);


20  D0_SROUT : IN std_logic;


21  D1_SROUT : IN std_logic;


22  D2_SROUT : IN std_logic;


23  D3_SROUT : IN std_logic;


24  D_PLLLCK : IN std_logic_vector (3 DOWNTO 0);


25  RS485_C_DI : IN std_logic;


26  RS485_E_DI : IN std_logic;


27  RS485_E_DO : IN std_logic;


28  TRG : IN STD_LOGIC;


29  W_INT : IN std_logic;


30  X_50M : IN STD_LOGIC;


31  A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');


32  A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


33  AMBER_LED : OUT std_logic;


34  A_CLK : OUT std_logic_vector (3 DOWNTO 0);


35  D0_SRCLK : OUT STD_LOGIC;


36  D1_SRCLK : OUT STD_LOGIC;


37  D2_SRCLK : OUT STD_LOGIC;


38  D3_SRCLK : OUT STD_LOGIC;


39  DAC_CS : OUT std_logic;


40  DENABLE : OUT std_logic := '0';


41  DWRITE : OUT std_logic := '0';


42  D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');


43  D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


44  D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');


45  EE_CS : OUT std_logic;


46  GREEN_LED : OUT std_logic;


47  MOSI : OUT std_logic := '0';


48  OE_ADC : OUT STD_LOGIC;


49  RED_LED : OUT std_logic;


50  RS485_C_DE : OUT std_logic;


51  RS485_C_DO : OUT std_logic;


52  RS485_C_RE : OUT std_logic;


53  RS485_E_DE : OUT std_logic;


54  RS485_E_RE : OUT std_logic;


55  RSRLOAD : OUT std_logic := '0';


56  SRIN : OUT std_logic := '0';


57  S_CLK : OUT std_logic;


58  T0_CS : OUT std_logic;


59  T1_CS : OUT std_logic;


60  T2_CS : OUT std_logic;


61  T3_CS : OUT std_logic;


62  TRG_V : OUT std_logic;


63  W_A : OUT std_logic_vector (9 DOWNTO 0);


64  W_CS : OUT std_logic := '1';


65  W_RD : OUT std_logic := '1';


66  W_RES : OUT std_logic := '1';


67  W_WR : OUT std_logic := '1';


68  MISO : INOUT std_logic;


69  W_D : INOUT std_logic_vector (15 DOWNTO 0)


70  );


71 


72   Declarations


73 


74  END FAD_Board ;


75 


76  


77   VHDL Architecture FACT_FAD_lib.FAD_Board.struct


78  


79   Created:


80   by  dneise.UNKNOWN (E5BLABOR6)


81   at  12:19:08 05.01.2011


82  


83   Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)


84  


85  LIBRARY ieee;


86  USE ieee.std_logic_1164.all;


87  USE ieee.std_logic_arith.all;


88  USE IEEE.NUMERIC_STD.all;


89  USE ieee.std_logic_unsigned.all;


90 


91  LIBRARY FACT_FAD_lib;


92  USE FACT_FAD_lib.fad_definitions.all;


93 


94  LIBRARY FACT_FAD_lib;


95 


96  ARCHITECTURE struct OF FAD_Board IS


97 


98   Architecture declarations


99 


100   Internal signal declarations


101  SIGNAL CLK25_OUT : std_logic;


102  SIGNAL CLK25_PSOUT : std_logic;


103  SIGNAL CLK50_OUT : std_logic;


104  SIGNAL CLK_25_PS : std_logic;


105  SIGNAL CLK_25_PS1 : std_logic;


106  SIGNAL CLK_50 : std_logic;


107  SIGNAL DCM_locked : std_logic;


108  SIGNAL LOCKED_extraOUT : std_logic;


109  SIGNAL PSCLK_OUT : std_logic;


110  SIGNAL PSDONE_extraOUT : std_logic;


111  SIGNAL PSEN_OUT : std_logic;


112  SIGNAL PSINCDEC_OUT : std_logic;


113  SIGNAL PS_DIR_IN : std_logic;


114  SIGNAL PS_DO_IN : std_logic;


115  SIGNAL SRCLK : std_logic := '0';


116  SIGNAL adc_clk_en : std_logic := '0';


117  SIGNAL adc_data_array : adc_data_array_type;


118  SIGNAL board_id : std_logic_vector(3 DOWNTO 0);


119  SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);


120  SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');


121  SIGNAL dummy : std_logic;


122  SIGNAL ready : std_logic := '0';


123  SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);


124   status:


125  SIGNAL shifting : std_logic := '0';


126 


127 


128   Component Declarations


129  COMPONENT FAD_main


130  GENERIC (


131  RAMADDRWIDTH64b : integer := 12


132  );


133  PORT (


134  CLK : IN std_logic ;


135  SROUT_in_0 : IN std_logic ;


136  SROUT_in_1 : IN std_logic ;


137  SROUT_in_2 : IN std_logic ;


138  SROUT_in_3 : IN std_logic ;


139  adc_data_array : IN adc_data_array_type ;


140  adc_otr_array : IN std_logic_vector (3 DOWNTO 0);


141  board_id : IN std_logic_vector (3 DOWNTO 0);


142  crate_id : IN std_logic_vector (1 DOWNTO 0);


143  trigger : IN std_logic ;


144  wiz_int : IN std_logic ;


145  CLK25_OUT : OUT std_logic ;


146  CLK25_PSOUT : OUT std_logic ;


147  CLK50_OUT : OUT std_logic ;


148  CLK_25_PS : OUT std_logic ;


149  CLK_50 : OUT std_logic ;


150  DCM_locked : OUT std_logic ;


151  LOCKED_extraOUT : OUT std_logic ;


152  PSCLK_OUT : OUT std_logic ;


153  PSDONE_extraOUT : OUT std_logic ;


154  PSEN_OUT : OUT std_logic ;


155  PSINCDEC_OUT : OUT std_logic ;


156  PS_DIR_IN : OUT std_logic ;


157  PS_DO_IN : OUT std_logic ;


158  RSRLOAD : OUT std_logic := '0';


159  SRCLK : OUT std_logic := '0';


160  SRIN_out : OUT std_logic := '0';


161  adc_clk_en : OUT std_logic := '0';


162  adc_oeb : OUT std_logic := '1';


163  amber : OUT std_logic ;


164  dac_cs : OUT std_logic ;


165  denable : OUT std_logic := '0';  default domino wave off


166  drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');


167  drs_dwrite : OUT std_logic := '1';


168  green : OUT std_logic ;


169  led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


170  mosi : OUT std_logic := '0';


171  offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


172  ready : OUT std_logic := '0';


173  red : OUT std_logic ;


174  sclk : OUT std_logic ;


175  sensor_cs : OUT std_logic_vector (3 DOWNTO 0);


176   status:


177  shifting : OUT std_logic := '0';


178  wiz_addr : OUT std_logic_vector (9 DOWNTO 0);


179  wiz_cs : OUT std_logic := '1';


180  wiz_rd : OUT std_logic := '1';


181  wiz_reset : OUT std_logic := '1';


182  wiz_wr : OUT std_logic := '1';


183  sio : INOUT std_logic ;


184  wiz_data : INOUT std_logic_vector (15 DOWNTO 0)


185  );


186  END COMPONENT;


187 


188   Optional embedded configurations


189   pragma synthesis_off


190  FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;


191   pragma synthesis_on


192 


193 


194  BEGIN


195   Architecture concurrent statements


196   HDL Embedded Text Block 1 eb_ID


197   hardwired IDs


198  board_id <= "0101";


199  crate_id <= "01";


200 


201   HDL Embedded Text Block 2 ADC_CLK


202   ADC_CLK 2


203  A_CLK (0) <= CLK_25_PS;


204  A_CLK (1) <= CLK_25_PS;


205  A_CLK (2) <= CLK_25_PS;


206  A_CLK (3) <= CLK_25_PS;


207 


208   HDL Embedded Text Block 3 ADC_DATA


209   ADC_DATA 3


210  adc_data_array (0) <= A0_D;


211  adc_data_array (1) <= A1_D;


212  adc_data_array (2) <= A2_D;


213  adc_data_array (3) <= A3_D;


214 


215   HDL Embedded Text Block 4 SRCLK


216   SRCLK 4


217  D0_SRCLK <= SRCLK;


218  D1_SRCLK <= SRCLK;


219  D2_SRCLK <= SRCLK;


220  D3_SRCLK <= SRCLK;


221 


222   HDL Embedded Text Block 5 T_CS


223   T_CS 5


224  T0_CS <= sensor_cs (0);


225  T1_CS <= sensor_cs (1);


226  T2_CS <= sensor_cs (2);


227  T3_CS <= sensor_cs (3);


228 


229   HDL Embedded Text Block 6 MISC


230   MISC 6


231  TRG_V <= '0';


232  RS485_C_RE <= '0';


233  RS485_C_DE <= '0';


234  RS485_C_DO <= RS485_C_DI;


235 


236  RS485_E_RE <= '0';


237  RS485_E_DE <= '0';


238  RS485_E_DO <= RS485_E_DI;


239 


240   DENABLE <= '0';  domino wave stopped


241   DENABLE <= '1';  domino wave running


242 


243 


244  EE_CS <= '1';


245 


246   HDL Embedded Text Block 7 eb1


247  D_T2 <= D_PLLLCK;


248 


249   HDL Embedded Text Block 8 eb2


250   eb2 8


251  D_A <= drs_channel_id;


252 


253   HDL Embedded Text Block 9 eb3


254   eb3 9


255  A0_T(0) <= CLK50_OUT;


256  A0_T(1) <= CLK25_OUT;


257  A0_T(2) <= CLK25_PSOUT;


258  A0_T(3) <= PS_DIR_IN;


259  A0_T(4) <= PS_DO_IN;


260  A0_T(5) <= PSINCDEC_OUT;


261  A0_T(6) <= PSEN_OUT;


262  A0_T(7) <= DCM_locked;


263 


264  A1_T(0) <= ready;


265  A1_T(1) <= shifting;


266  A1_T(2) <= PSDONE_extraOUT;


267  A1_T(3) <= PSCLK_OUT;


268  A1_T(4) <= LOCKED_extraOUT;


269 


270  A1_T(5) <= '0';


271  A1_T(6) <= '0';


272  A1_T(7) <= '0';


273 


274 


275   ModuleWare code(v1.9) for instance 'I0' of 'and'


276  CLK_25_PS <= adc_clk_en AND CLK_25_PS1;


277 


278   ModuleWare code(v1.9) for instance 'I3' of 'assignment'


279  DAC_CS <= dummy;


280 


281   Instance port mappings.


282  I_board_main : FAD_main


283  GENERIC MAP (


284  RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B


285  )


286  PORT MAP (


287  CLK => X_50M,


288  SROUT_in_0 => D0_SROUT,


289  SROUT_in_1 => D1_SROUT,


290  SROUT_in_2 => D2_SROUT,


291  SROUT_in_3 => D3_SROUT,


292  adc_data_array => adc_data_array,


293  adc_otr_array => A_OTR,


294  board_id => board_id,


295  crate_id => crate_id,


296  trigger => TRG,


297  wiz_int => W_INT,


298  CLK25_OUT => CLK25_OUT,


299  CLK25_PSOUT => CLK25_PSOUT,


300  CLK50_OUT => CLK50_OUT,


301  CLK_25_PS => CLK_25_PS1,


302  CLK_50 => CLK_50,


303  DCM_locked => DCM_locked,


304  LOCKED_extraOUT => LOCKED_extraOUT,


305  PSCLK_OUT => PSCLK_OUT,


306  PSDONE_extraOUT => PSDONE_extraOUT,


307  PSEN_OUT => PSEN_OUT,


308  PSINCDEC_OUT => PSINCDEC_OUT,


309  PS_DIR_IN => PS_DIR_IN,


310  PS_DO_IN => PS_DO_IN,


311  RSRLOAD => RSRLOAD,


312  SRCLK => SRCLK,


313  SRIN_out => SRIN,


314  adc_clk_en => adc_clk_en,


315  adc_oeb => OE_ADC,


316  amber => AMBER_LED,


317  dac_cs => dummy,


318  denable => DENABLE,


319  drs_channel_id => drs_channel_id,


320  drs_dwrite => DWRITE,


321  green => RED_LED,


322  led => D_T,


323  mosi => MOSI,


324  offset => OPEN,


325  ready => ready,


326  red => GREEN_LED,


327  sclk => S_CLK,


328  sensor_cs => sensor_cs,


329  shifting => shifting,


330  wiz_addr => W_A,


331  wiz_cs => W_CS,


332  wiz_rd => W_RD,


333  wiz_reset => W_RES,


334  wiz_wr => W_WR,


335  sio => MISO,


336  wiz_data => W_D


337  );


338 


339  END struct;

