1   VHDL Entity FACT_FAD_lib.FAD_Board.symbol


2  


3   Created:


4   by  dneise.UNKNOWN (E5BLABOR6)


5   at  17:46:34 05.01.2011


6  


7   Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)


8  


9  LIBRARY ieee;


10  USE ieee.std_logic_1164.all;


11  USE ieee.std_logic_arith.all;


12 


13  ENTITY FAD_Board IS


14  PORT(


15  A0_D : IN std_logic_vector (11 DOWNTO 0);


16  A1_D : IN std_logic_vector (11 DOWNTO 0);


17  A2_D : IN std_logic_vector (11 DOWNTO 0);


18  A3_D : IN std_logic_vector (11 DOWNTO 0);


19  A_OTR : IN std_logic_vector (3 DOWNTO 0);


20  D0_SROUT : IN std_logic;


21  D1_SROUT : IN std_logic;


22  D2_SROUT : IN std_logic;


23  D3_SROUT : IN std_logic;


24  D_PLLLCK : IN std_logic_vector (3 DOWNTO 0);


25  RS485_C_DI : IN std_logic;


26  RS485_E_DI : IN std_logic;


27  RS485_E_DO : IN std_logic;


28  TRG : IN STD_LOGIC;


29  W_INT : IN std_logic;


30  X_50M : IN STD_LOGIC;


31  A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');


32  A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


33  AMBER_LED : OUT std_logic;


34  A_CLK : OUT std_logic_vector (3 DOWNTO 0);


35  D0_SRCLK : OUT STD_LOGIC;


36  D1_SRCLK : OUT STD_LOGIC;


37  D2_SRCLK : OUT STD_LOGIC;


38  D3_SRCLK : OUT STD_LOGIC;


39  DAC_CS : OUT std_logic;


40  DENABLE : OUT std_logic := '0';


41  DWRITE : OUT std_logic := '0';


42  D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');


43  D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


44  D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');


45  EE_CS : OUT std_logic;


46  GREEN_LED : OUT std_logic;


47  MOSI : OUT std_logic := '0';


48  OE_ADC : OUT STD_LOGIC;


49  RED_LED : OUT std_logic;


50  RS485_C_DE : OUT std_logic;


51  RS485_C_DO : OUT std_logic;


52  RS485_C_RE : OUT std_logic;


53  RS485_E_DE : OUT std_logic;


54  RS485_E_RE : OUT std_logic;


55  RSRLOAD : OUT std_logic := '0';


56  SRIN : OUT std_logic := '0';


57  S_CLK : OUT std_logic;


58  T0_CS : OUT std_logic;


59  T1_CS : OUT std_logic;


60  T2_CS : OUT std_logic;


61  T3_CS : OUT std_logic;


62  TRG_V : OUT std_logic;


63  W_A : OUT std_logic_vector (9 DOWNTO 0);


64  W_CS : OUT std_logic := '1';


65  W_RD : OUT std_logic := '1';


66  W_RES : OUT std_logic := '1';


67  W_WR : OUT std_logic := '1';


68  MISO : INOUT std_logic;


69  W_D : INOUT std_logic_vector (15 DOWNTO 0)


70  );


71 


72   Declarations


73 


74  END FAD_Board ;


75 


76  


77   VHDL Architecture FACT_FAD_lib.FAD_Board.struct


78  


79   Created:


80   by  dneise.UNKNOWN (E5BLABOR6)


81   at  17:46:35 05.01.2011


82  


83   Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)


84  


85  LIBRARY ieee;


86  USE ieee.std_logic_1164.all;


87  USE ieee.std_logic_arith.all;


88  USE IEEE.NUMERIC_STD.all;


89  USE ieee.std_logic_unsigned.all;


90 


91  LIBRARY FACT_FAD_lib;


92  USE FACT_FAD_lib.fad_definitions.all;


93 


94  LIBRARY FACT_FAD_lib;


95 


96  ARCHITECTURE struct OF FAD_Board IS


97 


98   Architecture declarations


99 


100   Internal signal declarations


101  SIGNAL CLK25_OUT : std_logic;


102  SIGNAL CLK25_PSOUT : std_logic;


103  SIGNAL CLK50_OUT : std_logic;


104  SIGNAL CLK_25_PS : std_logic;


105  SIGNAL CLK_25_PS1 : std_logic;


106  SIGNAL CLK_50 : std_logic;


107  SIGNAL DCM_locked : std_logic;


108  SIGNAL LOCKED_extraOUT : std_logic;


109  SIGNAL PSCLK_OUT : std_logic;


110  SIGNAL PSDONE_extraOUT : std_logic;


111  SIGNAL PSEN_OUT : std_logic;


112  SIGNAL PSINCDEC_OUT : std_logic;


113  SIGNAL PS_DIR_IN : std_logic;


114  SIGNAL PS_DO_IN : std_logic;


115  SIGNAL SRCLK : std_logic := '0';


116  SIGNAL adc_clk_en : std_logic := '0';


117  SIGNAL adc_data_array : adc_data_array_type;


118  SIGNAL board_id : std_logic_vector(3 DOWNTO 0);


119  SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);


120  SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');


121  SIGNAL dummy : std_logic;


122  SIGNAL ready : std_logic := '0';


123  SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);


124   status:


125  SIGNAL shifting : std_logic := '0';


126 


127   Implicit buffer signal declarations


128  SIGNAL SRIN_internal : std_logic;


129 


130 


131   Component Declarations


132  COMPONENT FAD_main


133  GENERIC (


134  RAMADDRWIDTH64b : integer := 12


135  );


136  PORT (


137  CLK : IN std_logic ;


138  SROUT_in_0 : IN std_logic ;


139  SROUT_in_1 : IN std_logic ;


140  SROUT_in_2 : IN std_logic ;


141  SROUT_in_3 : IN std_logic ;


142  adc_data_array : IN adc_data_array_type ;


143  adc_otr_array : IN std_logic_vector (3 DOWNTO 0);


144  board_id : IN std_logic_vector (3 DOWNTO 0);


145  crate_id : IN std_logic_vector (1 DOWNTO 0);


146  trigger : IN std_logic ;


147  wiz_int : IN std_logic ;


148  CLK25_OUT : OUT std_logic ;


149  CLK25_PSOUT : OUT std_logic ;


150  CLK50_OUT : OUT std_logic ;


151  CLK_25_PS : OUT std_logic ;


152  CLK_50 : OUT std_logic ;


153  DCM_locked : OUT std_logic ;


154  LOCKED_extraOUT : OUT std_logic ;


155  PSCLK_OUT : OUT std_logic ;


156  PSDONE_extraOUT : OUT std_logic ;


157  PSEN_OUT : OUT std_logic ;


158  PSINCDEC_OUT : OUT std_logic ;


159  PS_DIR_IN : OUT std_logic ;


160  PS_DO_IN : OUT std_logic ;


161  RSRLOAD : OUT std_logic := '0';


162  SRCLK : OUT std_logic := '0';


163  SRIN_out : OUT std_logic := '0';


164  adc_clk_en : OUT std_logic := '0';


165  adc_oeb : OUT std_logic := '1';


166  amber : OUT std_logic ;


167  dac_cs : OUT std_logic ;


168  denable : OUT std_logic := '0';  default domino wave off


169  drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');


170  drs_dwrite : OUT std_logic := '1';


171  green : OUT std_logic ;


172  led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


173  mosi : OUT std_logic := '0';


174  offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');


175  ready : OUT std_logic := '0';


176  red : OUT std_logic ;


177  sclk : OUT std_logic ;


178  sensor_cs : OUT std_logic_vector (3 DOWNTO 0);


179   status:


180  shifting : OUT std_logic := '0';


181  wiz_addr : OUT std_logic_vector (9 DOWNTO 0);


182  wiz_cs : OUT std_logic := '1';


183  wiz_rd : OUT std_logic := '1';


184  wiz_reset : OUT std_logic := '1';


185  wiz_wr : OUT std_logic := '1';


186  sio : INOUT std_logic ;


187  wiz_data : INOUT std_logic_vector (15 DOWNTO 0)


188  );


189  END COMPONENT;


190 


191   Optional embedded configurations


192   pragma synthesis_off


193  FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;


194   pragma synthesis_on


195 


196 


197  BEGIN


198   Architecture concurrent statements


199   HDL Embedded Text Block 1 eb_ID


200   hardwired IDs


201  board_id <= "0101";


202  crate_id <= "01";


203 


204   HDL Embedded Text Block 2 ADC_CLK


205   ADC_CLK 2


206  A_CLK (0) <= CLK_25_PS;


207  A_CLK (1) <= CLK_25_PS;


208  A_CLK (2) <= CLK_25_PS;


209  A_CLK (3) <= CLK_25_PS;


210 


211   HDL Embedded Text Block 3 ADC_DATA


212   ADC_DATA 3


213  adc_data_array (0) <= A0_D;


214  adc_data_array (1) <= A1_D;


215  adc_data_array (2) <= A2_D;


216  adc_data_array (3) <= A3_D;


217 


218   HDL Embedded Text Block 4 SRCLK


219   SRCLK 4


220  D0_SRCLK <= SRCLK;


221  D1_SRCLK <= SRCLK;


222  D2_SRCLK <= SRCLK;


223  D3_SRCLK <= SRCLK;


224 


225   HDL Embedded Text Block 5 T_CS


226   T_CS 5


227  T0_CS <= sensor_cs (0);


228  T1_CS <= sensor_cs (1);


229  T2_CS <= sensor_cs (2);


230  T3_CS <= sensor_cs (3);


231 


232   HDL Embedded Text Block 6 MISC


233   MISC 6


234  TRG_V <= '0';


235  RS485_C_RE <= '0';


236  RS485_C_DE <= '0';


237  RS485_C_DO <= RS485_C_DI;


238 


239  RS485_E_RE <= '0';


240  RS485_E_DE <= '0';


241  RS485_E_DO <= RS485_E_DI;


242 


243   DENABLE <= '0';  domino wave stopped


244   DENABLE <= '1';  domino wave running


245 


246 


247  EE_CS <= '1';


248 


249   HDL Embedded Text Block 7 eb1


250  D_T2 <= D_PLLLCK;


251 


252   HDL Embedded Text Block 8 eb2


253   eb2 8


254  D_A <= drs_channel_id;


255 


256   HDL Embedded Text Block 9 eb3


257   eb3 9


258  A0_T(0) <= ready;


259  A0_T(1) <= shifting;


260  A0_T(2) <= CLK25_PSOUT;


261  A0_T(3) <= PS_DIR_IN;


262  A0_T(4) <= PS_DO_IN;


263  A0_T(5) <= PSINCDEC_OUT;


264  A0_T(6) <= PSEN_OUT;


265  A0_T(7) <= DCM_locked;


266 


267  A1_T(0) <= SRIN_internal;


268  A1_T(1) <= PSDONE_extraOUT;


269  A1_T(2) <= PSCLK_OUT;


270  A1_T(3) <= LOCKED_extraOUT;


271 


272  A1_T(4) <= drs_channel_id(0);


273  A1_T(5) <= drs_channel_id(1);


274  A1_T(6) <= drs_channel_id(2);


275  A1_T(7) <= drs_channel_id(3);


276 


277 


278   ModuleWare code(v1.9) for instance 'I0' of 'and'


279  CLK_25_PS <= adc_clk_en AND CLK_25_PS1;


280 


281   ModuleWare code(v1.9) for instance 'I3' of 'assignment'


282  DAC_CS <= dummy;


283 


284   Instance port mappings.


285  I_board_main : FAD_main


286  GENERIC MAP (


287  RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B


288  )


289  PORT MAP (


290  CLK => X_50M,


291  SROUT_in_0 => D0_SROUT,


292  SROUT_in_1 => D1_SROUT,


293  SROUT_in_2 => D2_SROUT,


294  SROUT_in_3 => D3_SROUT,


295  adc_data_array => adc_data_array,


296  adc_otr_array => A_OTR,


297  board_id => board_id,


298  crate_id => crate_id,


299  trigger => TRG,


300  wiz_int => W_INT,


301  CLK25_OUT => CLK25_OUT,


302  CLK25_PSOUT => CLK25_PSOUT,


303  CLK50_OUT => CLK50_OUT,


304  CLK_25_PS => CLK_25_PS1,


305  CLK_50 => CLK_50,


306  DCM_locked => DCM_locked,


307  LOCKED_extraOUT => LOCKED_extraOUT,


308  PSCLK_OUT => PSCLK_OUT,


309  PSDONE_extraOUT => PSDONE_extraOUT,


310  PSEN_OUT => PSEN_OUT,


311  PSINCDEC_OUT => PSINCDEC_OUT,


312  PS_DIR_IN => PS_DIR_IN,


313  PS_DO_IN => PS_DO_IN,


314  RSRLOAD => RSRLOAD,


315  SRCLK => SRCLK,


316  SRIN_out => SRIN_internal,


317  adc_clk_en => adc_clk_en,


318  adc_oeb => OE_ADC,


319  amber => AMBER_LED,


320  dac_cs => dummy,


321  denable => DENABLE,


322  drs_channel_id => drs_channel_id,


323  drs_dwrite => DWRITE,


324  green => RED_LED,


325  led => D_T,


326  mosi => MOSI,


327  offset => OPEN,


328  ready => ready,


329  red => GREEN_LED,


330  sclk => S_CLK,


331  sensor_cs => sensor_cs,


332  shifting => shifting,


333  wiz_addr => W_A,


334  wiz_cs => W_CS,


335  wiz_rd => W_RD,


336  wiz_reset => W_RES,


337  wiz_wr => W_WR,


338  sio => MISO,


339  wiz_data => W_D


340  );


341 


342   Implicit buffered output assignments


343  SRIN <= SRIN_internal;


344 


345  END struct;

