source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd@ 10121

Last change on this file since 10121 was 10121, checked in by neise, 12 years ago
synchronous trigger handling added continous soft trigger generation. ---> control frequency via 'send 0x21??' each step increases trigger delay by 12.5ms 0x2100 = 40Hz 0x21FF = 0.3Hz
File size: 12.9 KB
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1-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 16:46:19 26.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY FAD_Board IS
14 PORT(
15 A0_D : IN std_logic_vector (11 DOWNTO 0);
16 A1_D : IN std_logic_vector (11 DOWNTO 0);
17 A2_D : IN std_logic_vector (11 DOWNTO 0);
18 A3_D : IN std_logic_vector (11 DOWNTO 0);
19 A_OTR : IN std_logic_vector (3 DOWNTO 0);
20 D0_SROUT : IN std_logic;
21 D1_SROUT : IN std_logic;
22 D2_SROUT : IN std_logic;
23 D3_SROUT : IN std_logic;
24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0);
25 POSITION_ID : IN std_logic_vector ( 5 DOWNTO 0 );
26 REFCLK : IN std_logic;
27 RS485_C_DI : IN std_logic;
28 RS485_E_DI : IN std_logic;
29 RS485_E_DO : IN std_logic;
30 TRG : IN STD_LOGIC;
31 W_INT : IN std_logic;
32 X_50M : IN STD_LOGIC;
33 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
34 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
35 AMBER_LED : OUT std_logic;
36 A_CLK : OUT std_logic_vector (3 DOWNTO 0);
37 D0_SRCLK : OUT STD_LOGIC;
38 D1_SRCLK : OUT STD_LOGIC;
39 D2_SRCLK : OUT STD_LOGIC;
40 D3_SRCLK : OUT STD_LOGIC;
41 DAC_CS : OUT std_logic;
42 DENABLE : OUT std_logic := '0';
43 DWRITE : OUT std_logic := '0';
44 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
45 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
46 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
47 EE_CS : OUT std_logic;
48 GREEN_LED : OUT std_logic;
49 MOSI : OUT std_logic := '0';
50 OE_ADC : OUT STD_LOGIC;
51 RED_LED : OUT std_logic;
52 RS485_C_DE : OUT std_logic;
53 RS485_C_DO : OUT std_logic;
54 RS485_C_RE : OUT std_logic;
55 RS485_E_DE : OUT std_logic;
56 RS485_E_RE : OUT std_logic;
57 RSRLOAD : OUT std_logic := '0';
58 SRIN : OUT std_logic := '0';
59 S_CLK : OUT std_logic;
60 T0_CS : OUT std_logic;
61 T1_CS : OUT std_logic;
62 T2_CS : OUT std_logic;
63 T3_CS : OUT std_logic;
64 TRG_V : OUT std_logic;
65 W_A : OUT std_logic_vector (9 DOWNTO 0);
66 W_CS : OUT std_logic := '1';
67 W_RD : OUT std_logic := '1';
68 W_RES : OUT std_logic := '1';
69 W_WR : OUT std_logic := '1';
70 MISO : INOUT std_logic;
71 W_D : INOUT std_logic_vector (15 DOWNTO 0)
72 );
73
74-- Declarations
75
76END FAD_Board ;
77
78--
79-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct
80--
81-- Created:
82-- by - dneise.UNKNOWN (E5B-LABOR6)
83-- at - 16:46:20 26.01.2011
84--
85-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
86--
87LIBRARY ieee;
88USE ieee.std_logic_1164.all;
89USE ieee.std_logic_arith.all;
90USE IEEE.NUMERIC_STD.all;
91USE ieee.std_logic_unsigned.all;
92
93LIBRARY FACT_FAD_lib;
94USE FACT_FAD_lib.fad_definitions.all;
95
96LIBRARY FACT_FAD_lib;
97
98ARCHITECTURE struct OF FAD_Board IS
99
100 -- Architecture declarations
101
102 -- Internal signal declarations
103 SIGNAL CLK25_OUT : std_logic;
104 SIGNAL CLK25_PSOUT : std_logic;
105 SIGNAL CLK50_OUT : std_logic;
106 SIGNAL CLK_25_PS : std_logic;
107 SIGNAL CLK_25_PS1 : std_logic;
108 SIGNAL CLK_50 : std_logic;
109 SIGNAL DCM_locked : std_logic;
110 SIGNAL LOCKED_extraOUT : std_logic;
111 SIGNAL PSCLK_OUT : std_logic;
112 SIGNAL PSDONE_extraOUT : std_logic;
113 SIGNAL PSINCDEC_OUT : std_logic;
114 SIGNAL PS_DIR_IN : std_logic;
115 SIGNAL SRCLK : std_logic := '0';
116 SIGNAL adc_clk_en : std_logic := '0';
117 SIGNAL adc_data_array : adc_data_array_type;
118 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
119 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
120 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
121 SIGNAL dummy : std_logic;
122 SIGNAL ready : std_logic := '0';
123 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
124 -- status:
125 SIGNAL shifting : std_logic := '0';
126
127 -- Implicit buffer signal declarations
128 SIGNAL SRIN_internal : std_logic;
129
130
131 -- Component Declarations
132 COMPONENT FAD_main
133 GENERIC (
134 RAMADDRWIDTH64b : integer := 12
135 );
136 PORT (
137 CLK : IN std_logic ;
138 SROUT_in_0 : IN std_logic ;
139 SROUT_in_1 : IN std_logic ;
140 SROUT_in_2 : IN std_logic ;
141 SROUT_in_3 : IN std_logic ;
142 adc_data_array : IN adc_data_array_type ;
143 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
144 board_id : IN std_logic_vector (3 DOWNTO 0);
145 crate_id : IN std_logic_vector (1 DOWNTO 0);
146 trigger : IN std_logic ;
147 wiz_int : IN std_logic ;
148 CLK25_OUT : OUT std_logic ;
149 CLK25_PSOUT : OUT std_logic ;
150 CLK50_OUT : OUT std_logic ;
151 CLK_25_PS : OUT std_logic ;
152 CLK_50 : OUT std_logic ;
153 DCM_locked : OUT std_logic ;
154 LOCKED_extraOUT : OUT std_logic ;
155 PSCLK_OUT : OUT std_logic ;
156 PSDONE_extraOUT : OUT std_logic ;
157 PSINCDEC_OUT : OUT std_logic ;
158 PS_DIR_IN : OUT std_logic ;
159 RSRLOAD : OUT std_logic := '0';
160 SRCLK : OUT std_logic := '0';
161 SRIN_out : OUT std_logic := '0';
162 adc_clk_en : OUT std_logic := '0';
163 adc_oeb : OUT std_logic := '1';
164 additional_flasher_out : OUT std_logic ;
165 amber : OUT std_logic ;
166 dac_cs : OUT std_logic ;
167 denable : OUT std_logic := '0'; -- default domino wave off
168 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
169 drs_dwrite : OUT std_logic := '1';
170 green : OUT std_logic ;
171 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
172 mosi : OUT std_logic := '0';
173 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
174 ready : OUT std_logic := '0';
175 red : OUT std_logic ;
176 sclk : OUT std_logic ;
177 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
178 -- status:
179 shifting : OUT std_logic := '0';
180 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
181 wiz_cs : OUT std_logic := '1';
182 wiz_rd : OUT std_logic := '1';
183 wiz_reset : OUT std_logic := '1';
184 wiz_wr : OUT std_logic := '1';
185 sio : INOUT std_logic ;
186 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
187 );
188 END COMPONENT;
189
190 -- Optional embedded configurations
191 -- pragma synthesis_off
192 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
193 -- pragma synthesis_on
194
195
196BEGIN
197 -- Architecture concurrent statements
198 -- HDL Embedded Text Block 1 eb_ID
199 -- hard-wired IDs
200 board_id <= "0101";
201 crate_id <= "01";
202
203 -- HDL Embedded Text Block 2 ADC_CLK
204 -- ADC_CLK 2
205 A_CLK (0) <= CLK_25_PS;
206 A_CLK (1) <= CLK_25_PS;
207 A_CLK (2) <= CLK_25_PS;
208 A_CLK (3) <= CLK_25_PS;
209
210 -- HDL Embedded Text Block 3 ADC_DATA
211 -- ADC_DATA 3
212 adc_data_array (0) <= A0_D;
213 adc_data_array (1) <= A1_D;
214 adc_data_array (2) <= A2_D;
215 adc_data_array (3) <= A3_D;
216
217 -- HDL Embedded Text Block 4 SRCLK
218 -- SRCLK 4
219 D0_SRCLK <= SRCLK;
220 D1_SRCLK <= SRCLK;
221 D2_SRCLK <= SRCLK;
222 D3_SRCLK <= SRCLK;
223
224 -- HDL Embedded Text Block 5 T_CS
225 -- T_CS 5
226 T0_CS <= sensor_cs (0);
227 T1_CS <= sensor_cs (1);
228 T2_CS <= sensor_cs (2);
229 T3_CS <= sensor_cs (3);
230
231 -- HDL Embedded Text Block 6 MISC
232 -- MISC 6
233
234 RS485_C_RE <= '0';
235 RS485_C_DE <= '0';
236 RS485_C_DO <= RS485_C_DI;
237
238
239
240 -- DENABLE <= '0'; -- domino wave stopped
241 -- DENABLE <= '1'; -- domino wave running
242
243
244 EE_CS <= '1';
245
246 -- HDL Embedded Text Block 8 eb2
247 -- eb2 8
248 D_A <= drs_channel_id;
249
250 -- HDL Embedded Text Block 9 eb3
251 -- eb3 9
252 --A0_T(0) <= ready;
253 --A0_T(1) <= shifting;
254 --A0_T(2) <= CLK25_PSOUT;
255 --A0_T(3) <= PS_DIR_IN;
256 --A0_T(4) <= PS_DO_IN;
257 --A0_T(5) <= PSINCDEC_OUT;
258
259
260
261 A1_T(0) <= SRIN_internal;
262 A1_T(1) <= PSDONE_extraOUT;
263 A1_T(2) <= PSCLK_OUT;
264 A1_T(3) <= LOCKED_extraOUT;
265
266 A1_T(4) <= drs_channel_id(0);
267 A1_T(5) <= drs_channel_id(1);
268 A1_T(6) <= drs_channel_id(2);
269 A1_T(7) <= drs_channel_id(3);
270
271 A0_T(5 downto 0) <= POSITION_ID;
272 A0_T(6) <= REFCLK;
273 A0_T(7) <= RS485_E_DI;
274 RS485_E_RE <= '0';
275 RS485_E_DE <= '0';
276
277 D_T2 <= D_PLLLCK;
278
279
280 -- ModuleWare code(v1.9) for instance 'I0' of 'and'
281 CLK_25_PS <= adc_clk_en AND CLK_25_PS1;
282
283 -- ModuleWare code(v1.9) for instance 'I3' of 'assignment'
284 DAC_CS <= dummy;
285
286 -- Instance port mappings.
287 I_board_main : FAD_main
288 GENERIC MAP (
289 RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B
290 )
291 PORT MAP (
292 CLK => X_50M,
293 SROUT_in_0 => D0_SROUT,
294 SROUT_in_1 => D1_SROUT,
295 SROUT_in_2 => D2_SROUT,
296 SROUT_in_3 => D3_SROUT,
297 adc_data_array => adc_data_array,
298 adc_otr_array => A_OTR,
299 board_id => board_id,
300 crate_id => crate_id,
301 trigger => TRG,
302 wiz_int => W_INT,
303 CLK25_OUT => CLK25_OUT,
304 CLK25_PSOUT => CLK25_PSOUT,
305 CLK50_OUT => CLK50_OUT,
306 CLK_25_PS => CLK_25_PS1,
307 CLK_50 => CLK_50,
308 DCM_locked => DCM_locked,
309 LOCKED_extraOUT => LOCKED_extraOUT,
310 PSCLK_OUT => PSCLK_OUT,
311 PSDONE_extraOUT => PSDONE_extraOUT,
312 PSINCDEC_OUT => PSINCDEC_OUT,
313 PS_DIR_IN => PS_DIR_IN,
314 RSRLOAD => RSRLOAD,
315 SRCLK => SRCLK,
316 SRIN_out => SRIN_internal,
317 adc_clk_en => adc_clk_en,
318 adc_oeb => OE_ADC,
319 additional_flasher_out => TRG_V,
320 amber => AMBER_LED,
321 dac_cs => dummy,
322 denable => DENABLE,
323 drs_channel_id => drs_channel_id,
324 drs_dwrite => DWRITE,
325 green => RED_LED,
326 led => D_T,
327 mosi => MOSI,
328 offset => OPEN,
329 ready => ready,
330 red => GREEN_LED,
331 sclk => S_CLK,
332 sensor_cs => sensor_cs,
333 shifting => shifting,
334 wiz_addr => W_A,
335 wiz_cs => W_CS,
336 wiz_rd => W_RD,
337 wiz_reset => W_RES,
338 wiz_wr => W_WR,
339 sio => MISO,
340 wiz_data => W_D
341 );
342
343 -- Implicit buffered output assignments
344 SRIN <= SRIN_internal;
345
346END struct;
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