source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd@ 10567

Last change on this file since 10567 was 10567, checked in by neise, 10 years ago
File size: 11.1 KB
Line 
1-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 15:22:10 04.05.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY FAD_Board IS
14 PORT(
15 A0_D : IN std_logic_vector (11 DOWNTO 0);
16 A1_D : IN std_logic_vector (11 DOWNTO 0);
17 A2_D : IN std_logic_vector (11 DOWNTO 0);
18 A3_D : IN std_logic_vector (11 DOWNTO 0);
19 A_OTR : IN std_logic_vector (3 DOWNTO 0);
20 D0_SROUT : IN std_logic;
21 D1_SROUT : IN std_logic;
22 D2_SROUT : IN std_logic;
23 D3_SROUT : IN std_logic;
24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0);
25 D_T_in : IN std_logic_vector (1 DOWNTO 0);
26 LINE : IN std_logic_vector ( 5 DOWNTO 0 );
27 REFCLK : IN std_logic;
28 RS485_C_DI : IN std_logic;
29 RS485_E_DI : IN std_logic;
30 TRG : IN STD_LOGIC;
31 W_INT : IN std_logic;
32 X_50M : IN STD_LOGIC;
33 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
34 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
35 AMBER_LED : OUT std_logic;
36 A_CLK : OUT std_logic_vector (3 DOWNTO 0);
37 DAC_CS : OUT std_logic;
38 DENABLE : OUT std_logic := '0';
39 DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
40 DWRITE : OUT std_logic := '0';
41 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
42 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
43 D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0');
44 EE_CS : OUT std_logic;
45 GREEN_LED : OUT std_logic;
46 MOSI : OUT std_logic := '0';
47 OE_ADC : OUT STD_LOGIC;
48 RED_LED : OUT std_logic;
49 RS485_C_DE : OUT std_logic;
50 RS485_C_DO : OUT std_logic;
51 RS485_C_RE : OUT std_logic;
52 RS485_E_DE : OUT std_logic;
53 RS485_E_DO : OUT std_logic;
54 RS485_E_RE : OUT std_logic;
55 RSRLOAD : OUT std_logic := '0';
56 SRIN : OUT std_logic := '0';
57 S_CLK : OUT std_logic;
58 TCS : OUT std_logic_vector (3 DOWNTO 0);
59 TRG_V : OUT std_logic := '0';
60 W_A : OUT std_logic_vector (9 DOWNTO 0);
61 W_CS : OUT std_logic := '1';
62 W_RD : OUT std_logic := '1';
63 W_RES : OUT std_logic := '1';
64 W_WR : OUT std_logic := '1';
65 MISO : INOUT std_logic;
66 W_D : INOUT std_logic_vector (15 DOWNTO 0)
67 );
68
69-- Declarations
70
71END FAD_Board ;
72
73--
74-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct
75--
76-- Created:
77-- by - daqct3.UNKNOWN (IHP110)
78-- at - 15:22:11 04.05.2011
79--
80-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
81--
82LIBRARY ieee;
83USE ieee.std_logic_1164.all;
84USE ieee.std_logic_arith.all;
85USE IEEE.NUMERIC_STD.all;
86USE ieee.std_logic_unsigned.all;
87
88LIBRARY FACT_FAD_lib;
89USE FACT_FAD_lib.fad_definitions.all;
90
91LIBRARY FACT_FAD_lib;
92
93ARCHITECTURE struct OF FAD_Board IS
94
95 -- Architecture declarations
96
97 -- Internal signal declarations
98 SIGNAL ADC_CLK : std_logic;
99 SIGNAL CLK_50 : std_logic;
100 SIGNAL SRCLK : std_logic := '0';
101 SIGNAL adc_data_array : adc_data_array_type;
102 SIGNAL alarm_refclk_too_high : std_logic := '0';
103 SIGNAL alarm_refclk_too_low : std_logic := '0';
104 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
105 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) := (others => '0');
106 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
107 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
108
109
110 -- Component Declarations
111 COMPONENT FAD_main
112 GENERIC (
113 RAMADDRWIDTH64b : integer := 12
114 );
115 PORT (
116 CLK : IN std_logic ;
117 D_T_in : IN std_logic_vector (1 DOWNTO 0);
118 FTM_RS485_rx_d : IN std_logic ;
119 SROUT_in_0 : IN std_logic ;
120 SROUT_in_1 : IN std_logic ;
121 SROUT_in_2 : IN std_logic ;
122 SROUT_in_3 : IN std_logic ;
123 adc_data_array : IN adc_data_array_type ;
124 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
125 board_id : IN std_logic_vector (3 DOWNTO 0);
126 crate_id : IN std_logic_vector (1 DOWNTO 0);
127 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit
128 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked
129 trigger : IN std_logic ;
130 wiz_int : IN std_logic ;
131 ADC_CLK : OUT std_logic ;
132 CLK_25_PS : OUT std_logic ;
133 CLK_50 : OUT std_logic ;
134 FTM_RS485_rx_en : OUT std_logic ;
135 FTM_RS485_tx_d : OUT std_logic ;
136 FTM_RS485_tx_en : OUT std_logic ;
137 RSRLOAD : OUT std_logic := '0';
138 SRCLK : OUT std_logic := '0';
139 SRIN_out : OUT std_logic := '0';
140 adc_oeb : OUT std_logic := '1';
141 alarm_refclk_too_high : OUT std_logic ;
142 alarm_refclk_too_low : OUT std_logic ;
143 amber : OUT std_logic ;
144 counter_result : OUT std_logic_vector (11 DOWNTO 0);
145 dac_cs : OUT std_logic ;
146 denable : OUT std_logic := '0'; -- default domino wave off
147 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
148 drs_dwrite : OUT std_logic := '1';
149 green : OUT std_logic ;
150 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
151 mosi : OUT std_logic := '0';
152 red : OUT std_logic ;
153 sclk : OUT std_logic ;
154 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
155 trigger_veto : OUT std_logic := '1';
156 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
157 wiz_cs : OUT std_logic := '1';
158 wiz_rd : OUT std_logic := '1';
159 wiz_reset : OUT std_logic := '1';
160 wiz_wr : OUT std_logic := '1';
161 sio : INOUT std_logic ;
162 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
163 );
164 END COMPONENT;
165
166 -- Optional embedded configurations
167 -- pragma synthesis_off
168 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
169 -- pragma synthesis_on
170
171
172BEGIN
173 -- Architecture concurrent statements
174 -- HDL Embedded Text Block 1 SRCLK
175 DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
176
177 -- HDL Embedded Text Block 2 ADC_CLK
178 A_CLK <= (
179 ADC_CLK,
180 ADC_CLK,
181 ADC_CLK,
182 ADC_CLK
183 );
184
185 -- HDL Embedded Text Block 3 ADC_DATA
186 adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );
187
188 -- HDL Embedded Text Block 4 eb_ID
189 -- hard-wired IDs
190 board_id <= LINE(5 downto 2);
191 crate_id <= LINE(1 downto 0);
192
193 -- HDL Embedded Text Block 9 eb3
194 -- testpins D_T2 are used as MAX3485 outputs.
195
196 --D_T <= (others => '0');
197 --D_T2 <= ( others => '0' );
198 D_T2(1) <= '0';
199 -- A0_T(7 downto 0) <= (others => '0');
200 --A1_T(7 downto 0) <= (others => '0');
201
202 A1_T <= counter_result ( 7 downto 0);
203 D_T(3 downto 0) <= counter_result ( 11 downto 8);
204 D_T(4) <= alarm_refclk_too_low;
205 D_T(5) <= alarm_refclk_too_high;
206 D_T(6) <= '0';
207 D_T(7) <= '0';
208
209 -- led output is driven by w5300 modul
210 -- for debugging only.
211 A0_T <= led;
212
213 -- additional MAX3485 is switched to shutdown mode
214 RS485_C_RE <= '1'; --inverted logic
215 RS485_C_DE <= '0';
216 RS485_C_DO <= '0';
217 -- MAX3485 receiver out pit is fed out... should be HIGH-Z
218 D_T2(0) <= RS485_C_DI;
219
220 -- EEPROM is not used on FAD. CS is always high.
221 EE_CS <= '1';
222
223
224 -- Instance port mappings.
225 I_board_main : FAD_main
226 GENERIC MAP (
227 RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B
228 )
229 PORT MAP (
230 CLK => X_50M,
231 D_T_in => D_T_in,
232 FTM_RS485_rx_d => RS485_E_DI,
233 SROUT_in_0 => D0_SROUT,
234 SROUT_in_1 => D1_SROUT,
235 SROUT_in_2 => D2_SROUT,
236 SROUT_in_3 => D3_SROUT,
237 adc_data_array => adc_data_array,
238 adc_otr_array => A_OTR,
239 board_id => board_id,
240 crate_id => crate_id,
241 drs_refclk_in => REFCLK,
242 plllock_in => D_PLLLCK,
243 trigger => TRG,
244 wiz_int => W_INT,
245 ADC_CLK => ADC_CLK,
246 CLK_25_PS => OPEN,
247 CLK_50 => CLK_50,
248 FTM_RS485_rx_en => RS485_E_RE,
249 FTM_RS485_tx_d => RS485_E_DO,
250 FTM_RS485_tx_en => RS485_E_DE,
251 RSRLOAD => RSRLOAD,
252 SRCLK => SRCLK,
253 SRIN_out => SRIN,
254 adc_oeb => OE_ADC,
255 alarm_refclk_too_high => alarm_refclk_too_high,
256 alarm_refclk_too_low => alarm_refclk_too_low,
257 amber => AMBER_LED,
258 counter_result => counter_result,
259 dac_cs => DAC_CS,
260 denable => DENABLE,
261 drs_channel_id => D_A,
262 drs_dwrite => DWRITE,
263 green => RED_LED,
264 led => led,
265 mosi => MOSI,
266 red => GREEN_LED,
267 sclk => S_CLK,
268 sensor_cs => TCS,
269 trigger_veto => TRG_V,
270 wiz_addr => W_A,
271 wiz_cs => W_CS,
272 wiz_rd => W_RD,
273 wiz_reset => W_RES,
274 wiz_wr => W_WR,
275 sio => MISO,
276 wiz_data => W_D
277 );
278
279END struct;
Note: See TracBrowser for help on using the repository browser.