source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 10073

Last change on this file since 10073 was 10073, checked in by neise, 12 years ago
File size: 31.4 KB
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1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 17:00:23 03.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 SROUT_in_0 : IN std_logic;
22 SROUT_in_1 : IN std_logic;
23 SROUT_in_2 : IN std_logic;
24 SROUT_in_3 : IN std_logic;
25 adc_data_array : IN adc_data_array_type;
26 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
27 board_id : IN std_logic_vector (3 DOWNTO 0);
28 crate_id : IN std_logic_vector (1 DOWNTO 0);
29 trigger : IN std_logic;
30 wiz_int : IN std_logic;
31 CLK25_OUT : OUT std_logic;
32 CLK25_PSOUT : OUT std_logic;
33 CLK50_OUT : OUT std_logic;
34 CLK_25_PS : OUT std_logic;
35 CLK_50 : OUT std_logic;
36 DCM_locked : OUT std_logic;
37 LOCKED_extraOUT : OUT std_logic;
38 PSCLK_OUT : OUT std_logic;
39 PSDONE_extraOUT : OUT std_logic;
40 PSEN_OUT : OUT std_logic;
41 PSINCDEC_OUT : OUT std_logic;
42 PS_DIR_IN : OUT std_logic;
43 PS_DO_IN : OUT std_logic;
44 RSRLOAD : OUT std_logic := '0';
45 SRCLK : OUT std_logic := '0';
46 SRIN_out : OUT std_logic := '0';
47 adc_clk_en : OUT std_logic := '0';
48 adc_oeb : OUT std_logic := '1';
49 dac_cs : OUT std_logic;
50 denable : OUT std_logic := '0'; -- default domino wave off
51 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
52 drs_dwrite : OUT std_logic := '1';
53 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
54 mosi : OUT std_logic := '0';
55 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
56 ready : OUT std_logic := '0';
57 sclk : OUT std_logic;
58 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
59 -- status:
60 shifting : OUT std_logic := '0';
61 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
62 wiz_cs : OUT std_logic := '1';
63 wiz_rd : OUT std_logic := '1';
64 wiz_reset : OUT std_logic := '1';
65 wiz_wr : OUT std_logic := '1';
66 sio : INOUT std_logic;
67 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
68 );
69
70-- Declarations
71
72END FAD_main ;
73
74--
75-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
76--
77-- Created:
78-- by - dneise.UNKNOWN (E5B-LABOR6)
79-- at - 17:00:24 03.01.2011
80--
81-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
82--
83library ieee;
84use ieee.std_logic_1164.all;
85use IEEE.STD_LOGIC_ARITH.all;
86use ieee.STD_LOGIC_UNSIGNED.all;
87
88library fact_fad_lib;
89use fact_fad_lib.fad_definitions.all;
90
91library UNISIM;
92use UNISIM.VComponents.all;
93USE IEEE.NUMERIC_STD.all;
94USE IEEE.std_logic_signed.all;
95
96LIBRARY FACT_FAD_lib;
97
98ARCHITECTURE struct OF FAD_main IS
99
100 -- Architecture declarations
101
102 -- Internal signal declarations
103 SIGNAL CLK_25 : std_logic;
104 SIGNAL SRCLK1 : std_logic := '0';
105 SIGNAL adc_data_array_int : adc_data_array_type;
106 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
107 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
108 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);
109 SIGNAL config_busy : std_logic;
110 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);
111 SIGNAL config_data_valid : std_logic;
112 SIGNAL config_rd_en : std_logic;
113 SIGNAL config_ready : std_logic;
114 SIGNAL config_ready_cm : std_logic;
115 SIGNAL config_ready_spi : std_logic;
116 -- --
117 SIGNAL config_rw_ack : std_logic := '0';
118 -- --
119 SIGNAL config_rw_ready : std_logic := '0';
120 SIGNAL config_start : std_logic := '0';
121 SIGNAL config_start_cm : std_logic;
122 SIGNAL config_start_spi : std_logic := '0';
123 SIGNAL config_started : std_logic;
124 SIGNAL config_started_cu : std_logic := '0';
125 SIGNAL config_started_mm : std_logic;
126 SIGNAL config_started_spi : std_logic := '0';
127 SIGNAL config_wr_en : std_logic;
128 SIGNAL dac_array : dac_array_type;
129 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
130 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0');
131 SIGNAL drs_address_mode : std_logic;
132 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0');
133 SIGNAL drs_clk_en : std_logic := '0';
134 SIGNAL drs_read_s_cell : std_logic := '0';
135 SIGNAL drs_read_s_cell_ready : std_logic;
136 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
137 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
138 SIGNAL dwrite : std_logic := '1';
139 SIGNAL dwrite_enable : std_logic := '1';
140 SIGNAL new_config : std_logic := '0';
141 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
142 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
143 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
144 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
145 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
146 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
147 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
148 SIGNAL ram_write_ea : std_logic;
149 SIGNAL ram_write_ready : std_logic := '0';
150 -- --
151 SIGNAL ram_write_ready_ack : std_logic := '0';
152 SIGNAL roi_array : roi_array_type;
153 SIGNAL roi_max : roi_max_type;
154 SIGNAL s_trigger : std_logic;
155 SIGNAL sclk1 : std_logic;
156 SIGNAL sclk_enable : std_logic;
157 SIGNAL sensor_array : sensor_array_type;
158 SIGNAL sensor_ready : std_logic;
159 SIGNAL srclk_enable : std_logic := '0';
160 SIGNAL srin_write_ack : std_logic := '0';
161 SIGNAL srin_write_ready : std_logic := '0';
162 SIGNAL start_srin_write_8b : std_logic;
163 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);
164 SIGNAL trigger_out : std_logic;
165 SIGNAL wiz_ack : std_logic;
166 SIGNAL wiz_busy : std_logic;
167 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
168 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
169 SIGNAL wiz_write_ea : std_logic := '0';
170 SIGNAL wiz_write_end : std_logic := '0';
171 SIGNAL wiz_write_header : std_logic := '0';
172 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
173 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
174
175 -- Implicit buffer signal declarations
176 SIGNAL CLK_25_PS_internal : std_logic;
177 SIGNAL CLK_50_internal : std_logic;
178
179
180 -- Component Declarations
181 COMPONENT adc_buffer
182 PORT (
183 adc_data_array : IN adc_data_array_type;
184 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
185 clk_ps : IN std_logic;
186 adc_data_array_int : OUT adc_data_array_type;
187 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
188 );
189 END COMPONENT;
190 COMPONENT clock_generator_var_ps
191 PORT (
192 CLK : IN std_logic ;
193 RST_IN : IN std_logic ;
194 direction : IN std_logic ;
195 do_shift : IN std_logic ;
196 CLK_25 : OUT std_logic ;
197 CLK_25_PS : OUT std_logic ;
198 CLK_50 : OUT std_logic ;
199 DCM_locked : OUT std_logic ;
200 LOCKED_extraOUT : OUT std_logic ;
201 PSCLK_OUT : OUT std_logic ;
202 PSDONE_extraOUT : OUT std_logic ;
203 PSEN_OUT : OUT std_logic ;
204 PSINCDEC_OUT : OUT std_logic ;
205 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
206 ready : OUT std_logic := '0';
207 -- status:
208 shifting : OUT std_logic := '0'
209 );
210 END COMPONENT;
211 COMPONENT control_unit
212 PORT (
213 clk : IN STD_LOGIC ;
214 config_addr : IN std_logic_vector (7 DOWNTO 0);
215 config_rd_en : IN std_logic ;
216 config_start : IN std_logic ;
217 config_wr_en : IN std_logic ;
218 config_busy : OUT std_logic ;
219 config_data_valid : OUT std_logic ;
220 config_ready : OUT std_logic ;
221 -- --
222 config_rw_ack : OUT std_logic := '0';
223 -- --
224 config_rw_ready : OUT std_logic := '0';
225 config_started : OUT std_logic := '0';
226 dac_array : OUT dac_array_type ;
227 roi_array : OUT roi_array_type ;
228 config_data : INOUT std_logic_vector (15 DOWNTO 0)
229 );
230 END COMPONENT;
231 COMPONENT dataRAM_64b_16b_width14_5
232 PORT (
233 clka : IN std_logic ;
234 dina : IN std_logic_VECTOR (63 DOWNTO 0);
235 addra : IN std_logic_VECTOR (14 DOWNTO 0);
236 wea : IN std_logic_VECTOR (0 DOWNTO 0);
237 clkb : IN std_logic ;
238 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
239 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
240 );
241 END COMPONENT;
242 COMPONENT data_generator
243 GENERIC (
244 RAM_ADDR_WIDTH : integer := 12
245 );
246 PORT (
247 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
248 clk : IN std_logic ;
249 data_out : OUT std_logic_vector (63 DOWNTO 0);
250 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
251 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";
252 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
253 ram_write_ea : IN std_logic ;
254 ram_write_ready : OUT std_logic := '0';
255 -- --
256 ram_write_ready_ack : IN std_logic ;
257 -- --
258 config_start_mm : OUT std_logic := '0';
259 -- --
260 config_start_cm : OUT std_logic := '0';
261 -- --
262 config_start_spi : OUT std_logic := '0';
263 config_ready_mm : IN std_logic ;
264 config_ready_cm : IN std_logic ;
265 config_ready_spi : IN std_logic ;
266 config_started_mm : IN std_logic ;
267 config_started_cm : IN std_logic ;
268 config_started_spi : IN std_logic ;
269 roi_array : IN roi_array_type ;
270 roi_max : IN roi_max_type ;
271 sensor_array : IN sensor_array_type ;
272 sensor_ready : IN std_logic ;
273 dac_array : IN dac_array_type ;
274 package_length : IN std_logic_vector (15 DOWNTO 0);
275 board_id : IN std_logic_vector (3 DOWNTO 0);
276 crate_id : IN std_logic_vector (1 DOWNTO 0);
277 trigger_id : IN std_logic_vector (47 DOWNTO 0);
278 trigger : IN std_logic ;
279 -- s_trigger : in std_logic;
280 new_config : IN std_logic ;
281 config_started : OUT std_logic := '0';
282 adc_data_array : IN adc_data_array_type ;
283 adc_oeb : OUT std_logic := '1';
284 adc_clk_en : OUT std_logic := '0';
285 adc_otr : IN std_logic_vector (3 DOWNTO 0);
286 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
287 drs_dwrite : OUT std_logic := '1';
288 drs_clk_en : OUT std_logic := '0';
289 drs_read_s_cell : OUT std_logic := '0';
290 drs_srin_write_8b : OUT std_logic := '0';
291 drs_srin_write_ack : IN std_logic ;
292 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
293 drs_srin_write_ready : IN std_logic ;
294 drs_read_s_cell_ready : IN std_logic ;
295 drs_s_cell_array : IN drs_s_cell_array_type
296 );
297 END COMPONENT;
298 COMPONENT drs_pulser
299 PORT (
300 CLK : IN std_logic;
301 SROUT_in_0 : IN std_logic;
302 SROUT_in_1 : IN std_logic;
303 SROUT_in_2 : IN std_logic;
304 SROUT_in_3 : IN std_logic;
305 srin_data : IN std_logic_vector (7 DOWNTO 0);
306 start_endless_mode : IN std_logic;
307 start_read_stop_pos_mode : IN std_logic;
308 start_srin_write_8b : IN std_logic;
309 RSRLOAD : OUT std_logic := '0';
310 SRCLK : OUT std_logic := '0';
311 SRIN_out : OUT std_logic := '0';
312 srin_write_ack : OUT std_logic := '0';
313 srin_write_ready : OUT std_logic := '0';
314 stop_pos : OUT drs_s_cell_array_type;
315 stop_pos_valid : OUT std_logic := '0'
316 );
317 END COMPONENT;
318 COMPONENT memory_manager
319 GENERIC (
320 RAM_ADDR_WIDTH_64B : integer := 12;
321 RAM_ADDR_WIDTH_16B : integer := 14
322 );
323 PORT (
324 clk : IN std_logic ;
325 config_start : IN std_logic ;
326 ram_write_ready : IN std_logic ;
327 -- --
328 ram_write_ready_ack : OUT std_logic := '0';
329 -- --
330 roi_array : IN roi_array_type ;
331 ram_write_ea : OUT std_logic := '0';
332 config_ready : OUT std_logic := '0';
333 config_started : OUT std_logic := '0';
334 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
335 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
336 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
337 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
338 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
339 wiz_write_ea : OUT std_logic := '0';
340 wiz_write_header : OUT std_logic := '0';
341 wiz_write_end : OUT std_logic := '0';
342 wiz_busy : IN std_logic ;
343 wiz_ack : IN std_logic ;
344 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
345 );
346 END COMPONENT;
347 COMPONENT spi_interface
348 PORT (
349 clk_50MHz : IN std_logic ;
350 config_start : IN std_logic ;
351 dac_array : IN dac_array_type ;
352 config_ready : OUT std_logic ;
353 config_started : OUT std_logic := '0';
354 dac_cs : OUT std_logic ;
355 mosi : OUT std_logic := '0';
356 sclk : OUT std_logic ;
357 sensor_array : OUT sensor_array_type ;
358 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
359 sensor_ready : OUT std_logic ;
360 miso : INOUT std_logic
361 );
362 END COMPONENT;
363 COMPONENT trigger_counter
364 PORT (
365 trigger_id : OUT std_logic_vector (47 DOWNTO 0);
366 trigger : IN std_logic ;
367 clk : IN std_logic
368 );
369 END COMPONENT;
370 COMPONENT w5300_modul
371 GENERIC (
372 RAM_ADDR_WIDTH : integer := 14
373 );
374 PORT (
375 clk : IN std_logic ;
376 wiz_reset : OUT std_logic := '1';
377 addr : OUT std_logic_vector (9 DOWNTO 0);
378 data : INOUT std_logic_vector (15 DOWNTO 0);
379 cs : OUT std_logic := '1';
380 wr : OUT std_logic := '1';
381 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
382 rd : OUT std_logic := '1';
383 int : IN std_logic ;
384 write_length : IN std_logic_vector (16 DOWNTO 0);
385 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
386 ram_data : IN std_logic_vector (15 DOWNTO 0);
387 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
388 data_valid : IN std_logic ;
389 data_valid_ack : OUT std_logic := '0';
390 busy : OUT std_logic := '1';
391 write_header_flag : IN std_logic ;
392 write_end_flag : IN std_logic ;
393 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
394 s_trigger : OUT std_logic := '0';
395 new_config : OUT std_logic := '0';
396 config_started : IN std_logic ;
397 config_addr : OUT std_logic_vector (7 DOWNTO 0);
398 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
399 config_wr_en : OUT std_logic := '0';
400 config_rd_en : OUT std_logic := '0';
401 -- --
402 config_rw_ack : IN std_logic ;
403 -- --
404 config_rw_ready : IN std_logic ;
405 -- --
406 config_busy : IN std_logic ;
407 denable : OUT std_logic := '0'; -- default domino wave off
408 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.
409 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
410 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
411 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
412 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
413 srclk_enable : OUT std_logic := '1' -- default SRCLK on.
414 );
415 END COMPONENT;
416
417 -- Optional embedded configurations
418 -- pragma synthesis_off
419 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
420 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
421 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
422 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
423 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
424 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
425 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
426 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
427 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
428 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
429 -- pragma synthesis_on
430
431
432BEGIN
433
434 -- ModuleWare code(v1.9) for instance 'I5' of 'and'
435 drs_dwrite <= dwrite AND dwrite_enable;
436
437 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
438 SRCLK <= SRCLK1 AND srclk_enable;
439
440 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
441 sclk <= sclk_enable AND sclk1;
442
443 -- ModuleWare code(v1.9) for instance 'U_3' of 'assignment'
444 PS_DO_IN <= ps_do_phase_shift;
445
446 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
447 PS_DIR_IN <= ps_direction;
448
449 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
450 CLK50_OUT <= CLK_50_internal;
451
452 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
453 CLK25_OUT <= CLK_25;
454
455 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
456 CLK25_PSOUT <= CLK_25_PS_internal;
457
458 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
459 u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
460 drs_address_mode)
461 BEGIN
462 CASE drs_address_mode IS
463 WHEN '0' => drs_channel_id <= drs_channel_internal;
464 WHEN '1' => drs_channel_id <= drs_address;
465 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
466 END CASE;
467 END PROCESS u_0combo_proc;
468
469 -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
470 trigger_out <= s_trigger OR trigger;
471
472 -- Instance port mappings.
473 I_main_adc_buffer : adc_buffer
474 PORT MAP (
475 clk_ps => CLK_25_PS_internal,
476 adc_data_array => adc_data_array,
477 adc_otr_array => adc_otr_array,
478 adc_data_array_int => adc_data_array_int,
479 adc_otr => adc_otr
480 );
481 U_2 : clock_generator_var_ps
482 PORT MAP (
483 CLK => CLK,
484 RST_IN => ps_reset,
485 direction => ps_direction,
486 do_shift => ps_do_phase_shift,
487 CLK_25 => CLK_25,
488 CLK_25_PS => CLK_25_PS_internal,
489 CLK_50 => CLK_50_internal,
490 DCM_locked => DCM_locked,
491 LOCKED_extraOUT => LOCKED_extraOUT,
492 PSCLK_OUT => PSCLK_OUT,
493 PSDONE_extraOUT => PSDONE_extraOUT,
494 PSEN_OUT => PSEN_OUT,
495 PSINCDEC_OUT => PSINCDEC_OUT,
496 offset => offset,
497 ready => ready,
498 shifting => shifting
499 );
500 I_main_control_unit : control_unit
501 PORT MAP (
502 clk => CLK_50_internal,
503 config_addr => config_addr,
504 config_rd_en => config_rd_en,
505 config_start => config_start_cm,
506 config_wr_en => config_wr_en,
507 config_busy => config_busy,
508 config_data_valid => config_data_valid,
509 config_ready => config_ready_cm,
510 config_rw_ack => config_rw_ack,
511 config_rw_ready => config_rw_ready,
512 config_started => config_started_cu,
513 dac_array => dac_array,
514 roi_array => roi_array,
515 config_data => config_data
516 );
517 U_4 : dataRAM_64b_16b_width14_5
518 PORT MAP (
519 clka => CLK_25,
520 dina => data_out,
521 addra => addr_out,
522 wea => write_ea,
523 clkb => CLK_50_internal,
524 addrb => ram_addr,
525 doutb => ram_data
526 );
527 I_main_data_generator : data_generator
528 GENERIC MAP (
529 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
530 )
531 PORT MAP (
532 clk => CLK_25,
533 data_out => data_out,
534 addr_out => addr_out,
535 write_ea => write_ea,
536 ram_start_addr => ram_start_addr,
537 ram_write_ea => ram_write_ea,
538 ram_write_ready => ram_write_ready,
539 ram_write_ready_ack => ram_write_ready_ack,
540 config_start_mm => config_start,
541 config_start_cm => config_start_cm,
542 config_start_spi => config_start_spi,
543 config_ready_mm => config_ready,
544 config_ready_cm => config_ready_cm,
545 config_ready_spi => config_ready_spi,
546 config_started_mm => config_started_mm,
547 config_started_cm => config_started_cu,
548 config_started_spi => config_started_spi,
549 roi_array => roi_array,
550 roi_max => roi_max,
551 sensor_array => sensor_array,
552 sensor_ready => sensor_ready,
553 dac_array => dac_array,
554 package_length => package_length,
555 board_id => board_id,
556 crate_id => crate_id,
557 trigger_id => trigger_id,
558 trigger => trigger_out,
559 new_config => new_config,
560 config_started => config_started,
561 adc_data_array => adc_data_array_int,
562 adc_oeb => adc_oeb,
563 adc_clk_en => adc_clk_en,
564 adc_otr => adc_otr,
565 drs_channel_id => drs_channel_internal,
566 drs_dwrite => dwrite,
567 drs_clk_en => drs_clk_en,
568 drs_read_s_cell => drs_read_s_cell,
569 drs_srin_write_8b => start_srin_write_8b,
570 drs_srin_write_ack => srin_write_ack,
571 drs_srin_data => drs_srin_data,
572 drs_srin_write_ready => srin_write_ready,
573 drs_read_s_cell_ready => drs_read_s_cell_ready,
574 drs_s_cell_array => drs_s_cell_array
575 );
576 I_main_drs_pulser : drs_pulser
577 PORT MAP (
578 CLK => CLK_25,
579 start_endless_mode => drs_clk_en,
580 start_read_stop_pos_mode => drs_read_s_cell,
581 SROUT_in_0 => SROUT_in_0,
582 SROUT_in_1 => SROUT_in_1,
583 SROUT_in_2 => SROUT_in_2,
584 SROUT_in_3 => SROUT_in_3,
585 stop_pos => drs_s_cell_array,
586 stop_pos_valid => drs_read_s_cell_ready,
587 start_srin_write_8b => start_srin_write_8b,
588 srin_write_ready => srin_write_ready,
589 srin_write_ack => srin_write_ack,
590 srin_data => drs_srin_data,
591 SRIN_out => SRIN_out,
592 RSRLOAD => RSRLOAD,
593 SRCLK => SRCLK1
594 );
595 I_main_memory_manager : memory_manager
596 GENERIC MAP (
597 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
598 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
599 )
600 PORT MAP (
601 clk => CLK_25,
602 config_start => config_start,
603 ram_write_ready => ram_write_ready,
604 ram_write_ready_ack => ram_write_ready_ack,
605 roi_array => roi_array,
606 ram_write_ea => ram_write_ea,
607 config_ready => config_ready,
608 config_started => config_started_mm,
609 roi_max => roi_max,
610 package_length => package_length,
611 wiz_ram_start_addr => wiz_ram_start_addr,
612 wiz_write_length => wiz_write_length,
613 wiz_number_of_channels => wiz_number_of_channels,
614 wiz_write_ea => wiz_write_ea,
615 wiz_write_header => wiz_write_header,
616 wiz_write_end => wiz_write_end,
617 wiz_busy => wiz_busy,
618 wiz_ack => wiz_ack,
619 ram_start_addr => ram_start_addr
620 );
621 I_main_SPI_interface : spi_interface
622 PORT MAP (
623 clk_50MHz => CLK_50_internal,
624 config_start => config_start_spi,
625 dac_array => dac_array,
626 config_ready => config_ready_spi,
627 config_started => config_started_spi,
628 dac_cs => dac_cs,
629 mosi => mosi,
630 sclk => sclk1,
631 sensor_array => sensor_array,
632 sensor_cs => sensor_cs,
633 sensor_ready => sensor_ready,
634 miso => sio
635 );
636 I_main_ext_trigger : trigger_counter
637 PORT MAP (
638 trigger_id => trigger_id,
639 trigger => trigger_out,
640 clk => CLK_25_PS_internal
641 );
642 I_main_ethernet : w5300_modul
643 GENERIC MAP (
644 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
645 )
646 PORT MAP (
647 clk => CLK_50_internal,
648 wiz_reset => wiz_reset,
649 addr => wiz_addr,
650 data => wiz_data,
651 cs => wiz_cs,
652 wr => wiz_wr,
653 led => led,
654 rd => wiz_rd,
655 int => wiz_int,
656 write_length => wiz_write_length,
657 ram_start_addr => wiz_ram_start_addr,
658 ram_data => ram_data,
659 ram_addr => ram_addr,
660 data_valid => wiz_write_ea,
661 data_valid_ack => wiz_ack,
662 busy => wiz_busy,
663 write_header_flag => wiz_write_header,
664 write_end_flag => wiz_write_end,
665 fifo_channels => wiz_number_of_channels,
666 s_trigger => s_trigger,
667 new_config => new_config,
668 config_started => config_started,
669 config_addr => config_addr,
670 config_data => config_data,
671 config_wr_en => config_wr_en,
672 config_rd_en => config_rd_en,
673 config_rw_ack => config_rw_ack,
674 config_rw_ready => config_rw_ready,
675 config_busy => config_busy,
676 denable => denable,
677 dwrite_enable => dwrite_enable,
678 sclk_enable => sclk_enable,
679 ps_direction => ps_direction,
680 ps_do_phase_shift => ps_do_phase_shift,
681 ps_reset => ps_reset,
682 srclk_enable => srclk_enable
683 );
684
685 -- Implicit buffered output assignments
686 CLK_25_PS <= CLK_25_PS_internal;
687 CLK_50 <= CLK_50_internal;
688
689END struct;
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