1 | -- VHDL Entity FACT_FAD_lib.FAD_main.symbol |
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2 | -- |
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3 | -- Created: |
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4 | -- by - dneise.UNKNOWN (E5B-LABOR6) |
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5 | -- at - 18:14:35 04.01.2011 |
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6 | -- |
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7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) |
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8 | -- |
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9 | LIBRARY ieee; |
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10 | USE ieee.std_logic_1164.all; |
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11 | USE ieee.std_logic_arith.all; |
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12 | LIBRARY FACT_FAD_lib; |
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13 | USE FACT_FAD_lib.fad_definitions.all; |
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14 | |
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15 | ENTITY FAD_main IS |
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16 | GENERIC( |
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17 | RAMADDRWIDTH64b : integer := 12 |
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18 | ); |
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19 | PORT( |
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20 | CLK : IN std_logic; |
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21 | SROUT_in_0 : IN std_logic; |
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22 | SROUT_in_1 : IN std_logic; |
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23 | SROUT_in_2 : IN std_logic; |
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24 | SROUT_in_3 : IN std_logic; |
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25 | adc_data_array : IN adc_data_array_type; |
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26 | adc_otr_array : IN std_logic_vector (3 DOWNTO 0); |
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27 | board_id : IN std_logic_vector (3 DOWNTO 0); |
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28 | crate_id : IN std_logic_vector (1 DOWNTO 0); |
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29 | trigger : IN std_logic; |
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30 | wiz_int : IN std_logic; |
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31 | CLK25_OUT : OUT std_logic; |
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32 | CLK25_PSOUT : OUT std_logic; |
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33 | CLK50_OUT : OUT std_logic; |
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34 | CLK_25_PS : OUT std_logic; |
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35 | CLK_50 : OUT std_logic; |
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36 | DCM_locked : OUT std_logic; |
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37 | LOCKED_extraOUT : OUT std_logic; |
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38 | PSCLK_OUT : OUT std_logic; |
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39 | PSDONE_extraOUT : OUT std_logic; |
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40 | PSEN_OUT : OUT std_logic; |
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41 | PSINCDEC_OUT : OUT std_logic; |
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42 | PS_DIR_IN : OUT std_logic; |
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43 | PS_DO_IN : OUT std_logic; |
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44 | RSRLOAD : OUT std_logic := '0'; |
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45 | SRCLK : OUT std_logic := '0'; |
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46 | SRIN_out : OUT std_logic := '0'; |
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47 | adc_clk_en : OUT std_logic := '0'; |
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48 | adc_oeb : OUT std_logic := '1'; |
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49 | amber : OUT std_logic; |
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50 | dac_cs : OUT std_logic; |
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51 | denable : OUT std_logic := '0'; -- default domino wave off |
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52 | drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); |
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53 | drs_dwrite : OUT std_logic := '1'; |
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54 | green : OUT std_logic; |
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55 | led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); |
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56 | mosi : OUT std_logic := '0'; |
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57 | offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); |
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58 | ready : OUT std_logic := '0'; |
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59 | red : OUT std_logic; |
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60 | sclk : OUT std_logic; |
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61 | sensor_cs : OUT std_logic_vector (3 DOWNTO 0); |
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62 | -- status: |
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63 | shifting : OUT std_logic := '0'; |
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64 | wiz_addr : OUT std_logic_vector (9 DOWNTO 0); |
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65 | wiz_cs : OUT std_logic := '1'; |
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66 | wiz_rd : OUT std_logic := '1'; |
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67 | wiz_reset : OUT std_logic := '1'; |
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68 | wiz_wr : OUT std_logic := '1'; |
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69 | sio : INOUT std_logic; |
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70 | wiz_data : INOUT std_logic_vector (15 DOWNTO 0) |
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71 | ); |
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72 | |
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73 | -- Declarations |
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74 | |
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75 | END FAD_main ; |
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76 | |
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77 | -- |
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78 | -- VHDL Architecture FACT_FAD_lib.FAD_main.struct |
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79 | -- |
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80 | -- Created: |
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81 | -- by - dneise.UNKNOWN (E5B-LABOR6) |
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82 | -- at - 18:14:36 04.01.2011 |
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83 | -- |
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84 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) |
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85 | -- |
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86 | library ieee; |
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87 | use ieee.std_logic_1164.all; |
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88 | use IEEE.STD_LOGIC_ARITH.all; |
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89 | use ieee.STD_LOGIC_UNSIGNED.all; |
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90 | |
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91 | library fact_fad_lib; |
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92 | use fact_fad_lib.fad_definitions.all; |
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93 | |
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94 | library UNISIM; |
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95 | use UNISIM.VComponents.all; |
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96 | USE IEEE.NUMERIC_STD.all; |
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97 | USE IEEE.std_logic_signed.all; |
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98 | |
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99 | LIBRARY FACT_FAD_lib; |
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100 | |
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101 | ARCHITECTURE struct OF FAD_main IS |
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102 | |
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103 | -- Architecture declarations |
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104 | |
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105 | -- Internal signal declarations |
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106 | SIGNAL CLK_25 : std_logic; |
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107 | SIGNAL SRCLK1 : std_logic := '0'; |
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108 | SIGNAL adc_data_array_int : adc_data_array_type; |
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109 | SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); |
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110 | SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); |
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111 | SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); |
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112 | SIGNAL config_busy : std_logic; |
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113 | SIGNAL config_data : std_logic_vector(15 DOWNTO 0); |
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114 | SIGNAL config_data_valid : std_logic; |
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115 | SIGNAL config_rd_en : std_logic; |
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116 | SIGNAL config_ready : std_logic; |
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117 | SIGNAL config_ready_cm : std_logic; |
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118 | SIGNAL config_ready_spi : std_logic; |
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119 | -- -- |
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120 | SIGNAL config_rw_ack : std_logic := '0'; |
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121 | -- -- |
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122 | SIGNAL config_rw_ready : std_logic := '0'; |
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123 | SIGNAL config_start : std_logic := '0'; |
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124 | SIGNAL config_start_cm : std_logic; |
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125 | SIGNAL config_start_spi : std_logic := '0'; |
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126 | SIGNAL config_started : std_logic; |
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127 | SIGNAL config_started_cu : std_logic := '0'; |
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128 | SIGNAL config_started_mm : std_logic; |
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129 | SIGNAL config_started_spi : std_logic := '0'; |
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130 | SIGNAL config_wr_en : std_logic; |
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131 | SIGNAL dac_array : dac_array_type; |
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132 | SIGNAL data_out : std_logic_vector(63 DOWNTO 0); |
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133 | SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0'); |
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134 | SIGNAL drs_address_mode : std_logic; |
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135 | SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0'); |
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136 | SIGNAL drs_clk_en : std_logic := '0'; |
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137 | SIGNAL drs_read_s_cell : std_logic := '0'; |
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138 | SIGNAL drs_read_s_cell_ready : std_logic; |
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139 | SIGNAL drs_s_cell_array : drs_s_cell_array_type; |
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140 | SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); |
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141 | SIGNAL dwrite : std_logic := '1'; |
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142 | SIGNAL dwrite_enable : std_logic := '1'; |
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143 | SIGNAL new_config : std_logic := '0'; |
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144 | SIGNAL package_length : std_logic_vector(15 DOWNTO 0); |
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145 | SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards |
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146 | SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once |
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147 | SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift |
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148 | SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); |
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149 | SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); |
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150 | SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); |
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151 | SIGNAL ram_write_ea : std_logic; |
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152 | SIGNAL ram_write_ready : std_logic := '0'; |
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153 | -- -- |
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154 | SIGNAL ram_write_ready_ack : std_logic := '0'; |
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155 | SIGNAL roi_array : roi_array_type; |
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156 | SIGNAL roi_max : roi_max_type; |
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157 | SIGNAL s_trigger : std_logic; |
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158 | SIGNAL sclk1 : std_logic; |
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159 | SIGNAL sclk_enable : std_logic; |
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160 | SIGNAL sensor_array : sensor_array_type; |
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161 | SIGNAL sensor_ready : std_logic; |
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162 | SIGNAL socks_connected : std_logic; |
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163 | SIGNAL socks_waiting : std_logic; |
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164 | SIGNAL srclk_enable : std_logic := '0'; |
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165 | SIGNAL srin_write_ack : std_logic := '0'; |
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166 | SIGNAL srin_write_ready : std_logic := '0'; |
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167 | SIGNAL start_srin_write_8b : std_logic; |
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168 | SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); |
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169 | SIGNAL trigger_out : std_logic; |
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170 | SIGNAL wiz_ack : std_logic; |
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171 | SIGNAL wiz_busy : std_logic; |
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172 | SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); |
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173 | SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); |
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174 | SIGNAL wiz_write_ea : std_logic := '0'; |
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175 | SIGNAL wiz_write_end : std_logic := '0'; |
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176 | SIGNAL wiz_write_header : std_logic := '0'; |
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177 | SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); |
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178 | SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; |
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179 | |
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180 | -- Implicit buffer signal declarations |
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181 | SIGNAL CLK_25_PS_internal : std_logic; |
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182 | SIGNAL CLK_50_internal : std_logic; |
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183 | |
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184 | |
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185 | -- Component Declarations |
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186 | COMPONENT adc_buffer |
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187 | PORT ( |
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188 | adc_data_array : IN adc_data_array_type; |
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189 | adc_otr_array : IN std_logic_vector (3 DOWNTO 0); |
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190 | clk_ps : IN std_logic; |
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191 | adc_data_array_int : OUT adc_data_array_type; |
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192 | adc_otr : OUT std_logic_vector (3 DOWNTO 0) |
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193 | ); |
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194 | END COMPONENT; |
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195 | COMPONENT clock_generator_var_ps |
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196 | PORT ( |
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197 | CLK : IN std_logic ; |
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198 | RST_IN : IN std_logic ; |
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199 | direction : IN std_logic ; |
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200 | do_shift : IN std_logic ; |
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201 | CLK_25 : OUT std_logic ; |
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202 | CLK_25_PS : OUT std_logic ; |
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203 | CLK_50 : OUT std_logic ; |
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204 | DCM_locked : OUT std_logic ; |
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205 | LOCKED_extraOUT : OUT std_logic ; |
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206 | PSCLK_OUT : OUT std_logic ; |
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207 | PSDONE_extraOUT : OUT std_logic ; |
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208 | PSEN_OUT : OUT std_logic ; |
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209 | PSINCDEC_OUT : OUT std_logic ; |
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210 | offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); |
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211 | ready : OUT std_logic := '0'; |
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212 | -- status: |
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213 | shifting : OUT std_logic := '0' |
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214 | ); |
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215 | END COMPONENT; |
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216 | COMPONENT control_unit |
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217 | PORT ( |
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218 | clk : IN STD_LOGIC ; |
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219 | config_addr : IN std_logic_vector (7 DOWNTO 0); |
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220 | config_rd_en : IN std_logic ; |
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221 | config_start : IN std_logic ; |
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222 | config_wr_en : IN std_logic ; |
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223 | config_busy : OUT std_logic ; |
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224 | config_data_valid : OUT std_logic ; |
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225 | config_ready : OUT std_logic ; |
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226 | -- -- |
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227 | config_rw_ack : OUT std_logic := '0'; |
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228 | -- -- |
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229 | config_rw_ready : OUT std_logic := '0'; |
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230 | config_started : OUT std_logic := '0'; |
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231 | dac_array : OUT dac_array_type ; |
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232 | roi_array : OUT roi_array_type ; |
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233 | config_data : INOUT std_logic_vector (15 DOWNTO 0) |
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234 | ); |
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235 | END COMPONENT; |
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236 | COMPONENT dataRAM_64b_16b_width14_5 |
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237 | PORT ( |
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238 | clka : IN std_logic ; |
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239 | dina : IN std_logic_VECTOR (63 DOWNTO 0); |
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240 | addra : IN std_logic_VECTOR (14 DOWNTO 0); |
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241 | wea : IN std_logic_VECTOR (0 DOWNTO 0); |
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242 | clkb : IN std_logic ; |
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243 | addrb : IN std_logic_VECTOR (16 DOWNTO 0); |
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244 | doutb : OUT std_logic_VECTOR (15 DOWNTO 0) |
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245 | ); |
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246 | END COMPONENT; |
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247 | COMPONENT data_generator |
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248 | GENERIC ( |
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249 | RAM_ADDR_WIDTH : integer := 12 |
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250 | ); |
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251 | PORT ( |
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252 | -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); |
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253 | clk : IN std_logic ; |
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254 | data_out : OUT std_logic_vector (63 DOWNTO 0); |
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255 | addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); |
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256 | write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; |
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257 | ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); |
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258 | ram_write_ea : IN std_logic ; |
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259 | ram_write_ready : OUT std_logic := '0'; |
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260 | -- -- |
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261 | ram_write_ready_ack : IN std_logic ; |
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262 | -- -- |
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263 | config_start_mm : OUT std_logic := '0'; |
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264 | -- -- |
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265 | config_start_cm : OUT std_logic := '0'; |
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266 | -- -- |
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267 | config_start_spi : OUT std_logic := '0'; |
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268 | config_ready_mm : IN std_logic ; |
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269 | config_ready_cm : IN std_logic ; |
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270 | config_ready_spi : IN std_logic ; |
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271 | config_started_mm : IN std_logic ; |
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272 | config_started_cm : IN std_logic ; |
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273 | config_started_spi : IN std_logic ; |
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274 | roi_array : IN roi_array_type ; |
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275 | roi_max : IN roi_max_type ; |
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276 | sensor_array : IN sensor_array_type ; |
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277 | sensor_ready : IN std_logic ; |
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278 | dac_array : IN dac_array_type ; |
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279 | package_length : IN std_logic_vector (15 DOWNTO 0); |
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280 | board_id : IN std_logic_vector (3 DOWNTO 0); |
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281 | crate_id : IN std_logic_vector (1 DOWNTO 0); |
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282 | trigger_id : IN std_logic_vector (47 DOWNTO 0); |
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283 | trigger : IN std_logic ; |
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284 | -- s_trigger : in std_logic; |
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285 | new_config : IN std_logic ; |
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286 | config_started : OUT std_logic := '0'; |
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287 | adc_data_array : IN adc_data_array_type ; |
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288 | adc_oeb : OUT std_logic := '1'; |
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289 | adc_clk_en : OUT std_logic := '0'; |
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290 | adc_otr : IN std_logic_vector (3 DOWNTO 0); |
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291 | drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); |
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292 | drs_dwrite : OUT std_logic := '1'; |
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293 | drs_clk_en : OUT std_logic := '0'; |
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294 | drs_read_s_cell : OUT std_logic := '0'; |
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295 | drs_srin_write_8b : OUT std_logic := '0'; |
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296 | drs_srin_write_ack : IN std_logic ; |
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297 | drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); |
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298 | drs_srin_write_ready : IN std_logic ; |
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299 | drs_read_s_cell_ready : IN std_logic ; |
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300 | drs_s_cell_array : IN drs_s_cell_array_type |
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301 | ); |
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302 | END COMPONENT; |
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303 | COMPONENT drs_pulser |
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304 | PORT ( |
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305 | CLK : IN std_logic; |
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306 | SROUT_in_0 : IN std_logic; |
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307 | SROUT_in_1 : IN std_logic; |
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308 | SROUT_in_2 : IN std_logic; |
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309 | SROUT_in_3 : IN std_logic; |
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310 | srin_data : IN std_logic_vector (7 DOWNTO 0); |
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311 | start_endless_mode : IN std_logic; |
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312 | start_read_stop_pos_mode : IN std_logic; |
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313 | start_srin_write_8b : IN std_logic; |
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314 | RSRLOAD : OUT std_logic := '0'; |
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315 | SRCLK : OUT std_logic := '0'; |
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316 | SRIN_out : OUT std_logic := '0'; |
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317 | srin_write_ack : OUT std_logic := '0'; |
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318 | srin_write_ready : OUT std_logic := '0'; |
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319 | stop_pos : OUT drs_s_cell_array_type; |
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320 | stop_pos_valid : OUT std_logic := '0' |
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321 | ); |
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322 | END COMPONENT; |
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323 | COMPONENT led_controller |
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324 | GENERIC ( |
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325 | HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz |
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326 | MAX_DELAY : integer := 100; |
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327 | WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz |
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328 | ); |
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329 | PORT ( |
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330 | CLK : IN std_logic; |
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331 | socks_connected : IN std_logic; |
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332 | socks_waiting : IN std_logic; |
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333 | trigger : IN std_logic; |
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334 | amber : OUT std_logic; |
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335 | green : OUT std_logic; |
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336 | red : OUT std_logic |
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337 | ); |
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338 | END COMPONENT; |
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339 | COMPONENT memory_manager |
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340 | GENERIC ( |
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341 | RAM_ADDR_WIDTH_64B : integer := 12; |
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342 | RAM_ADDR_WIDTH_16B : integer := 14 |
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343 | ); |
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344 | PORT ( |
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345 | clk : IN std_logic ; |
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346 | config_start : IN std_logic ; |
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347 | ram_write_ready : IN std_logic ; |
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348 | -- -- |
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349 | ram_write_ready_ack : OUT std_logic := '0'; |
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350 | -- -- |
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351 | roi_array : IN roi_array_type ; |
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352 | ram_write_ea : OUT std_logic := '0'; |
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353 | config_ready : OUT std_logic := '0'; |
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354 | config_started : OUT std_logic := '0'; |
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355 | roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); |
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356 | package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); |
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357 | wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); |
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358 | wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0'); |
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359 | wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); |
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360 | wiz_write_ea : OUT std_logic := '0'; |
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361 | wiz_write_header : OUT std_logic := '0'; |
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362 | wiz_write_end : OUT std_logic := '0'; |
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363 | wiz_busy : IN std_logic ; |
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364 | wiz_ack : IN std_logic ; |
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365 | ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') |
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366 | ); |
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367 | END COMPONENT; |
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368 | COMPONENT spi_interface |
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369 | PORT ( |
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370 | clk_50MHz : IN std_logic ; |
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371 | config_start : IN std_logic ; |
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372 | dac_array : IN dac_array_type ; |
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373 | config_ready : OUT std_logic ; |
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374 | config_started : OUT std_logic := '0'; |
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375 | dac_cs : OUT std_logic ; |
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376 | mosi : OUT std_logic := '0'; |
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377 | sclk : OUT std_logic ; |
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378 | sensor_array : OUT sensor_array_type ; |
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379 | sensor_cs : OUT std_logic_vector (3 DOWNTO 0); |
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380 | sensor_ready : OUT std_logic ; |
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381 | miso : INOUT std_logic |
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382 | ); |
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383 | END COMPONENT; |
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384 | COMPONENT trigger_counter |
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385 | PORT ( |
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386 | trigger_id : OUT std_logic_vector (47 DOWNTO 0); |
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387 | trigger : IN std_logic ; |
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388 | clk : IN std_logic |
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389 | ); |
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390 | END COMPONENT; |
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391 | COMPONENT w5300_modul |
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392 | GENERIC ( |
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393 | RAM_ADDR_WIDTH : integer := 14 |
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394 | ); |
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395 | PORT ( |
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396 | clk : IN std_logic ; |
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397 | wiz_reset : OUT std_logic := '1'; |
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398 | addr : OUT std_logic_vector (9 DOWNTO 0); |
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399 | data : INOUT std_logic_vector (15 DOWNTO 0); |
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400 | cs : OUT std_logic := '1'; |
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401 | wr : OUT std_logic := '1'; |
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402 | led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); |
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403 | rd : OUT std_logic := '1'; |
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404 | int : IN std_logic ; |
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405 | write_length : IN std_logic_vector (16 DOWNTO 0); |
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406 | ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); |
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407 | ram_data : IN std_logic_vector (15 DOWNTO 0); |
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408 | ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); |
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409 | data_valid : IN std_logic ; |
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410 | data_valid_ack : OUT std_logic := '0'; |
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411 | busy : OUT std_logic := '1'; |
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412 | write_header_flag : IN std_logic ; |
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413 | write_end_flag : IN std_logic ; |
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414 | fifo_channels : IN std_logic_vector (3 DOWNTO 0); |
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415 | s_trigger : OUT std_logic := '0'; |
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416 | new_config : OUT std_logic := '0'; |
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417 | config_started : IN std_logic ; |
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418 | config_addr : OUT std_logic_vector (7 DOWNTO 0); |
---|
419 | config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); |
---|
420 | config_wr_en : OUT std_logic := '0'; |
---|
421 | config_rd_en : OUT std_logic := '0'; |
---|
422 | -- -- |
---|
423 | config_rw_ack : IN std_logic ; |
---|
424 | -- -- |
---|
425 | config_rw_ready : IN std_logic ; |
---|
426 | -- -- |
---|
427 | config_busy : IN std_logic ; |
---|
428 | denable : OUT std_logic := '0'; -- default domino wave off |
---|
429 | dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. |
---|
430 | sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. |
---|
431 | ps_direction : OUT std_logic := '1'; -- default phase shift upwards |
---|
432 | ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once |
---|
433 | ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift |
---|
434 | srclk_enable : OUT std_logic := '1'; -- default SRCLK on. |
---|
435 | socks_waiting : OUT std_logic ; |
---|
436 | socks_connected : OUT std_logic |
---|
437 | ); |
---|
438 | END COMPONENT; |
---|
439 | |
---|
440 | -- Optional embedded configurations |
---|
441 | -- pragma synthesis_off |
---|
442 | FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; |
---|
443 | FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; |
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444 | FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit; |
---|
445 | FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; |
---|
446 | FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; |
---|
447 | FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; |
---|
448 | FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; |
---|
449 | FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; |
---|
450 | FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; |
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451 | FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; |
---|
452 | FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul; |
---|
453 | -- pragma synthesis_on |
---|
454 | |
---|
455 | |
---|
456 | BEGIN |
---|
457 | |
---|
458 | -- ModuleWare code(v1.9) for instance 'I5' of 'and' |
---|
459 | drs_dwrite <= dwrite AND dwrite_enable; |
---|
460 | |
---|
461 | -- ModuleWare code(v1.9) for instance 'I6' of 'and' |
---|
462 | SRCLK <= SRCLK1 AND srclk_enable; |
---|
463 | |
---|
464 | -- ModuleWare code(v1.9) for instance 'U_1' of 'and' |
---|
465 | sclk <= sclk_enable AND sclk1; |
---|
466 | |
---|
467 | -- ModuleWare code(v1.9) for instance 'U_3' of 'assignment' |
---|
468 | PS_DO_IN <= ps_do_phase_shift; |
---|
469 | |
---|
470 | -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment' |
---|
471 | PS_DIR_IN <= ps_direction; |
---|
472 | |
---|
473 | -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment' |
---|
474 | CLK50_OUT <= CLK_50_internal; |
---|
475 | |
---|
476 | -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment' |
---|
477 | CLK25_OUT <= CLK_25; |
---|
478 | |
---|
479 | -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment' |
---|
480 | CLK25_PSOUT <= CLK_25_PS_internal; |
---|
481 | |
---|
482 | -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' |
---|
483 | u_0combo_proc: PROCESS(drs_channel_internal, drs_address, |
---|
484 | drs_address_mode) |
---|
485 | BEGIN |
---|
486 | CASE drs_address_mode IS |
---|
487 | WHEN '0' => drs_channel_id <= drs_channel_internal; |
---|
488 | WHEN '1' => drs_channel_id <= drs_address; |
---|
489 | WHEN OTHERS => drs_channel_id <= (OTHERS => 'X'); |
---|
490 | END CASE; |
---|
491 | END PROCESS u_0combo_proc; |
---|
492 | |
---|
493 | -- ModuleWare code(v1.9) for instance 'U_9' of 'or' |
---|
494 | trigger_out <= s_trigger OR trigger; |
---|
495 | |
---|
496 | -- Instance port mappings. |
---|
497 | I_main_adc_buffer : adc_buffer |
---|
498 | PORT MAP ( |
---|
499 | clk_ps => CLK_25_PS_internal, |
---|
500 | adc_data_array => adc_data_array, |
---|
501 | adc_otr_array => adc_otr_array, |
---|
502 | adc_data_array_int => adc_data_array_int, |
---|
503 | adc_otr => adc_otr |
---|
504 | ); |
---|
505 | U_2 : clock_generator_var_ps |
---|
506 | PORT MAP ( |
---|
507 | CLK => CLK, |
---|
508 | RST_IN => ps_reset, |
---|
509 | direction => ps_direction, |
---|
510 | do_shift => ps_do_phase_shift, |
---|
511 | CLK_25 => CLK_25, |
---|
512 | CLK_25_PS => CLK_25_PS_internal, |
---|
513 | CLK_50 => CLK_50_internal, |
---|
514 | DCM_locked => DCM_locked, |
---|
515 | LOCKED_extraOUT => LOCKED_extraOUT, |
---|
516 | PSCLK_OUT => PSCLK_OUT, |
---|
517 | PSDONE_extraOUT => PSDONE_extraOUT, |
---|
518 | PSEN_OUT => PSEN_OUT, |
---|
519 | PSINCDEC_OUT => PSINCDEC_OUT, |
---|
520 | offset => offset, |
---|
521 | ready => ready, |
---|
522 | shifting => shifting |
---|
523 | ); |
---|
524 | I_main_control_unit : control_unit |
---|
525 | PORT MAP ( |
---|
526 | clk => CLK_50_internal, |
---|
527 | config_addr => config_addr, |
---|
528 | config_rd_en => config_rd_en, |
---|
529 | config_start => config_start_cm, |
---|
530 | config_wr_en => config_wr_en, |
---|
531 | config_busy => config_busy, |
---|
532 | config_data_valid => config_data_valid, |
---|
533 | config_ready => config_ready_cm, |
---|
534 | config_rw_ack => config_rw_ack, |
---|
535 | config_rw_ready => config_rw_ready, |
---|
536 | config_started => config_started_cu, |
---|
537 | dac_array => dac_array, |
---|
538 | roi_array => roi_array, |
---|
539 | config_data => config_data |
---|
540 | ); |
---|
541 | U_4 : dataRAM_64b_16b_width14_5 |
---|
542 | PORT MAP ( |
---|
543 | clka => CLK_25, |
---|
544 | dina => data_out, |
---|
545 | addra => addr_out, |
---|
546 | wea => write_ea, |
---|
547 | clkb => CLK_50_internal, |
---|
548 | addrb => ram_addr, |
---|
549 | doutb => ram_data |
---|
550 | ); |
---|
551 | I_main_data_generator : data_generator |
---|
552 | GENERIC MAP ( |
---|
553 | RAM_ADDR_WIDTH => RAMADDRWIDTH64b |
---|
554 | ) |
---|
555 | PORT MAP ( |
---|
556 | clk => CLK_25, |
---|
557 | data_out => data_out, |
---|
558 | addr_out => addr_out, |
---|
559 | write_ea => write_ea, |
---|
560 | ram_start_addr => ram_start_addr, |
---|
561 | ram_write_ea => ram_write_ea, |
---|
562 | ram_write_ready => ram_write_ready, |
---|
563 | ram_write_ready_ack => ram_write_ready_ack, |
---|
564 | config_start_mm => config_start, |
---|
565 | config_start_cm => config_start_cm, |
---|
566 | config_start_spi => config_start_spi, |
---|
567 | config_ready_mm => config_ready, |
---|
568 | config_ready_cm => config_ready_cm, |
---|
569 | config_ready_spi => config_ready_spi, |
---|
570 | config_started_mm => config_started_mm, |
---|
571 | config_started_cm => config_started_cu, |
---|
572 | config_started_spi => config_started_spi, |
---|
573 | roi_array => roi_array, |
---|
574 | roi_max => roi_max, |
---|
575 | sensor_array => sensor_array, |
---|
576 | sensor_ready => sensor_ready, |
---|
577 | dac_array => dac_array, |
---|
578 | package_length => package_length, |
---|
579 | board_id => board_id, |
---|
580 | crate_id => crate_id, |
---|
581 | trigger_id => trigger_id, |
---|
582 | trigger => trigger_out, |
---|
583 | new_config => new_config, |
---|
584 | config_started => config_started, |
---|
585 | adc_data_array => adc_data_array_int, |
---|
586 | adc_oeb => adc_oeb, |
---|
587 | adc_clk_en => adc_clk_en, |
---|
588 | adc_otr => adc_otr, |
---|
589 | drs_channel_id => drs_channel_internal, |
---|
590 | drs_dwrite => dwrite, |
---|
591 | drs_clk_en => drs_clk_en, |
---|
592 | drs_read_s_cell => drs_read_s_cell, |
---|
593 | drs_srin_write_8b => start_srin_write_8b, |
---|
594 | drs_srin_write_ack => srin_write_ack, |
---|
595 | drs_srin_data => drs_srin_data, |
---|
596 | drs_srin_write_ready => srin_write_ready, |
---|
597 | drs_read_s_cell_ready => drs_read_s_cell_ready, |
---|
598 | drs_s_cell_array => drs_s_cell_array |
---|
599 | ); |
---|
600 | I_main_drs_pulser : drs_pulser |
---|
601 | PORT MAP ( |
---|
602 | CLK => CLK_25, |
---|
603 | start_endless_mode => drs_clk_en, |
---|
604 | start_read_stop_pos_mode => drs_read_s_cell, |
---|
605 | SROUT_in_0 => SROUT_in_0, |
---|
606 | SROUT_in_1 => SROUT_in_1, |
---|
607 | SROUT_in_2 => SROUT_in_2, |
---|
608 | SROUT_in_3 => SROUT_in_3, |
---|
609 | stop_pos => drs_s_cell_array, |
---|
610 | stop_pos_valid => drs_read_s_cell_ready, |
---|
611 | start_srin_write_8b => start_srin_write_8b, |
---|
612 | srin_write_ready => srin_write_ready, |
---|
613 | srin_write_ack => srin_write_ack, |
---|
614 | srin_data => drs_srin_data, |
---|
615 | SRIN_out => SRIN_out, |
---|
616 | RSRLOAD => RSRLOAD, |
---|
617 | SRCLK => SRCLK1 |
---|
618 | ); |
---|
619 | U_10 : led_controller |
---|
620 | GENERIC MAP ( |
---|
621 | HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz |
---|
622 | MAX_DELAY => 100, |
---|
623 | WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz |
---|
624 | ) |
---|
625 | PORT MAP ( |
---|
626 | CLK => CLK_50_internal, |
---|
627 | green => green, |
---|
628 | amber => amber, |
---|
629 | red => red, |
---|
630 | trigger => trigger_out, |
---|
631 | socks_waiting => socks_waiting, |
---|
632 | socks_connected => socks_connected |
---|
633 | ); |
---|
634 | I_main_memory_manager : memory_manager |
---|
635 | GENERIC MAP ( |
---|
636 | RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, |
---|
637 | RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 |
---|
638 | ) |
---|
639 | PORT MAP ( |
---|
640 | clk => CLK_25, |
---|
641 | config_start => config_start, |
---|
642 | ram_write_ready => ram_write_ready, |
---|
643 | ram_write_ready_ack => ram_write_ready_ack, |
---|
644 | roi_array => roi_array, |
---|
645 | ram_write_ea => ram_write_ea, |
---|
646 | config_ready => config_ready, |
---|
647 | config_started => config_started_mm, |
---|
648 | roi_max => roi_max, |
---|
649 | package_length => package_length, |
---|
650 | wiz_ram_start_addr => wiz_ram_start_addr, |
---|
651 | wiz_write_length => wiz_write_length, |
---|
652 | wiz_number_of_channels => wiz_number_of_channels, |
---|
653 | wiz_write_ea => wiz_write_ea, |
---|
654 | wiz_write_header => wiz_write_header, |
---|
655 | wiz_write_end => wiz_write_end, |
---|
656 | wiz_busy => wiz_busy, |
---|
657 | wiz_ack => wiz_ack, |
---|
658 | ram_start_addr => ram_start_addr |
---|
659 | ); |
---|
660 | I_main_SPI_interface : spi_interface |
---|
661 | PORT MAP ( |
---|
662 | clk_50MHz => CLK_50_internal, |
---|
663 | config_start => config_start_spi, |
---|
664 | dac_array => dac_array, |
---|
665 | config_ready => config_ready_spi, |
---|
666 | config_started => config_started_spi, |
---|
667 | dac_cs => dac_cs, |
---|
668 | mosi => mosi, |
---|
669 | sclk => sclk1, |
---|
670 | sensor_array => sensor_array, |
---|
671 | sensor_cs => sensor_cs, |
---|
672 | sensor_ready => sensor_ready, |
---|
673 | miso => sio |
---|
674 | ); |
---|
675 | I_main_ext_trigger : trigger_counter |
---|
676 | PORT MAP ( |
---|
677 | trigger_id => trigger_id, |
---|
678 | trigger => trigger_out, |
---|
679 | clk => CLK_25_PS_internal |
---|
680 | ); |
---|
681 | I_main_ethernet : w5300_modul |
---|
682 | GENERIC MAP ( |
---|
683 | RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 |
---|
684 | ) |
---|
685 | PORT MAP ( |
---|
686 | clk => CLK_50_internal, |
---|
687 | wiz_reset => wiz_reset, |
---|
688 | addr => wiz_addr, |
---|
689 | data => wiz_data, |
---|
690 | cs => wiz_cs, |
---|
691 | wr => wiz_wr, |
---|
692 | led => led, |
---|
693 | rd => wiz_rd, |
---|
694 | int => wiz_int, |
---|
695 | write_length => wiz_write_length, |
---|
696 | ram_start_addr => wiz_ram_start_addr, |
---|
697 | ram_data => ram_data, |
---|
698 | ram_addr => ram_addr, |
---|
699 | data_valid => wiz_write_ea, |
---|
700 | data_valid_ack => wiz_ack, |
---|
701 | busy => wiz_busy, |
---|
702 | write_header_flag => wiz_write_header, |
---|
703 | write_end_flag => wiz_write_end, |
---|
704 | fifo_channels => wiz_number_of_channels, |
---|
705 | s_trigger => s_trigger, |
---|
706 | new_config => new_config, |
---|
707 | config_started => config_started, |
---|
708 | config_addr => config_addr, |
---|
709 | config_data => config_data, |
---|
710 | config_wr_en => config_wr_en, |
---|
711 | config_rd_en => config_rd_en, |
---|
712 | config_rw_ack => config_rw_ack, |
---|
713 | config_rw_ready => config_rw_ready, |
---|
714 | config_busy => config_busy, |
---|
715 | denable => denable, |
---|
716 | dwrite_enable => dwrite_enable, |
---|
717 | sclk_enable => sclk_enable, |
---|
718 | ps_direction => ps_direction, |
---|
719 | ps_do_phase_shift => ps_do_phase_shift, |
---|
720 | ps_reset => ps_reset, |
---|
721 | srclk_enable => srclk_enable, |
---|
722 | socks_waiting => socks_waiting, |
---|
723 | socks_connected => socks_connected |
---|
724 | ); |
---|
725 | |
---|
726 | -- Implicit buffered output assignments |
---|
727 | CLK_25_PS <= CLK_25_PS_internal; |
---|
728 | CLK_50 <= CLK_50_internal; |
---|
729 | |
---|
730 | END struct; |
---|