source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 10078

Last change on this file since 10078 was 10078, checked in by neise, 12 years ago
possible to choose, which socket is used for data transmission. only socket 0 for every event or sockets 1..7
File size: 32.9 KB
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1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 12:19:06 05.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 SROUT_in_0 : IN std_logic;
22 SROUT_in_1 : IN std_logic;
23 SROUT_in_2 : IN std_logic;
24 SROUT_in_3 : IN std_logic;
25 adc_data_array : IN adc_data_array_type;
26 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
27 board_id : IN std_logic_vector (3 DOWNTO 0);
28 crate_id : IN std_logic_vector (1 DOWNTO 0);
29 trigger : IN std_logic;
30 wiz_int : IN std_logic;
31 CLK25_OUT : OUT std_logic;
32 CLK25_PSOUT : OUT std_logic;
33 CLK50_OUT : OUT std_logic;
34 CLK_25_PS : OUT std_logic;
35 CLK_50 : OUT std_logic;
36 DCM_locked : OUT std_logic;
37 LOCKED_extraOUT : OUT std_logic;
38 PSCLK_OUT : OUT std_logic;
39 PSDONE_extraOUT : OUT std_logic;
40 PSEN_OUT : OUT std_logic;
41 PSINCDEC_OUT : OUT std_logic;
42 PS_DIR_IN : OUT std_logic;
43 PS_DO_IN : OUT std_logic;
44 RSRLOAD : OUT std_logic := '0';
45 SRCLK : OUT std_logic := '0';
46 SRIN_out : OUT std_logic := '0';
47 adc_clk_en : OUT std_logic := '0';
48 adc_oeb : OUT std_logic := '1';
49 amber : OUT std_logic;
50 dac_cs : OUT std_logic;
51 denable : OUT std_logic := '0'; -- default domino wave off
52 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
53 drs_dwrite : OUT std_logic := '1';
54 green : OUT std_logic;
55 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
56 mosi : OUT std_logic := '0';
57 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
58 ready : OUT std_logic := '0';
59 red : OUT std_logic;
60 sclk : OUT std_logic;
61 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
62 -- status:
63 shifting : OUT std_logic := '0';
64 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
65 wiz_cs : OUT std_logic := '1';
66 wiz_rd : OUT std_logic := '1';
67 wiz_reset : OUT std_logic := '1';
68 wiz_wr : OUT std_logic := '1';
69 sio : INOUT std_logic;
70 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
71 );
72
73-- Declarations
74
75END FAD_main ;
76
77--
78-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
79--
80-- Created:
81-- by - dneise.UNKNOWN (E5B-LABOR6)
82-- at - 12:19:07 05.01.2011
83--
84-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
85--
86library ieee;
87use ieee.std_logic_1164.all;
88use IEEE.STD_LOGIC_ARITH.all;
89use ieee.STD_LOGIC_UNSIGNED.all;
90
91library fact_fad_lib;
92use fact_fad_lib.fad_definitions.all;
93
94library UNISIM;
95use UNISIM.VComponents.all;
96USE IEEE.NUMERIC_STD.all;
97USE IEEE.std_logic_signed.all;
98
99LIBRARY FACT_FAD_lib;
100
101ARCHITECTURE struct OF FAD_main IS
102
103 -- Architecture declarations
104
105 -- Internal signal declarations
106 SIGNAL CLK_25 : std_logic;
107 SIGNAL SRCLK1 : std_logic := '0';
108 SIGNAL adc_data_array_int : adc_data_array_type;
109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
110 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
111 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);
112 SIGNAL config_busy : std_logic;
113 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);
114 SIGNAL config_data_valid : std_logic;
115 SIGNAL config_rd_en : std_logic;
116 SIGNAL config_ready : std_logic;
117 SIGNAL config_ready_cm : std_logic;
118 SIGNAL config_ready_spi : std_logic;
119 -- --
120 SIGNAL config_rw_ack : std_logic := '0';
121 -- --
122 SIGNAL config_rw_ready : std_logic := '0';
123 SIGNAL config_start : std_logic := '0';
124 SIGNAL config_start_cm : std_logic;
125 SIGNAL config_start_spi : std_logic := '0';
126 SIGNAL config_started : std_logic;
127 SIGNAL config_started_cu : std_logic := '0';
128 SIGNAL config_started_mm : std_logic;
129 SIGNAL config_started_spi : std_logic := '0';
130 SIGNAL config_wr_en : std_logic;
131 SIGNAL dac_array : dac_array_type;
132 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
133 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0');
134 SIGNAL drs_address_mode : std_logic;
135 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0');
136 SIGNAL drs_clk_en : std_logic := '0';
137 SIGNAL drs_read_s_cell : std_logic := '0';
138 SIGNAL drs_read_s_cell_ready : std_logic;
139 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
140 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
141 SIGNAL dwrite : std_logic := '1';
142 SIGNAL dwrite_enable : std_logic := '1';
143 SIGNAL new_config : std_logic := '0';
144 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
145 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
146 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
147 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
148 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
149 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
150 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
151 SIGNAL ram_write_ea : std_logic;
152 SIGNAL ram_write_ready : std_logic := '0';
153 -- --
154 SIGNAL ram_write_ready_ack : std_logic := '0';
155 SIGNAL roi_array : roi_array_type;
156 SIGNAL roi_max : roi_max_type;
157 SIGNAL s_trigger : std_logic;
158 SIGNAL sclk1 : std_logic;
159 SIGNAL sclk_enable : std_logic;
160 SIGNAL sensor_array : sensor_array_type;
161 SIGNAL sensor_ready : std_logic;
162 SIGNAL socks_connected : std_logic;
163 SIGNAL socks_waiting : std_logic;
164 SIGNAL srclk_enable : std_logic := '0';
165 SIGNAL srin_write_ack : std_logic := '0';
166 SIGNAL srin_write_ready : std_logic := '0';
167 SIGNAL start_srin_write_8b : std_logic;
168 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);
169 SIGNAL trigger_out : std_logic;
170 SIGNAL wiz_ack : std_logic;
171 SIGNAL wiz_busy : std_logic;
172 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
173 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
174 SIGNAL wiz_write_ea : std_logic := '0';
175 SIGNAL wiz_write_end : std_logic := '0';
176 SIGNAL wiz_write_header : std_logic := '0';
177 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
178 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
179
180 -- Implicit buffer signal declarations
181 SIGNAL CLK_25_PS_internal : std_logic;
182 SIGNAL CLK_50_internal : std_logic;
183
184
185 -- Component Declarations
186 COMPONENT adc_buffer
187 PORT (
188 adc_data_array : IN adc_data_array_type;
189 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
190 clk_ps : IN std_logic;
191 adc_data_array_int : OUT adc_data_array_type;
192 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
193 );
194 END COMPONENT;
195 COMPONENT clock_generator_var_ps
196 PORT (
197 CLK : IN std_logic ;
198 RST_IN : IN std_logic ;
199 direction : IN std_logic ;
200 do_shift : IN std_logic ;
201 CLK_25 : OUT std_logic ;
202 CLK_25_PS : OUT std_logic ;
203 CLK_50 : OUT std_logic ;
204 DCM_locked : OUT std_logic ;
205 LOCKED_extraOUT : OUT std_logic ;
206 PSCLK_OUT : OUT std_logic ;
207 PSDONE_extraOUT : OUT std_logic ;
208 PSEN_OUT : OUT std_logic ;
209 PSINCDEC_OUT : OUT std_logic ;
210 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
211 ready : OUT std_logic := '0';
212 -- status:
213 shifting : OUT std_logic := '0'
214 );
215 END COMPONENT;
216 COMPONENT control_unit
217 PORT (
218 clk : IN STD_LOGIC ;
219 config_addr : IN std_logic_vector (7 DOWNTO 0);
220 config_rd_en : IN std_logic ;
221 config_start : IN std_logic ;
222 config_wr_en : IN std_logic ;
223 config_busy : OUT std_logic ;
224 config_data_valid : OUT std_logic ;
225 config_ready : OUT std_logic ;
226 -- --
227 config_rw_ack : OUT std_logic := '0';
228 -- --
229 config_rw_ready : OUT std_logic := '0';
230 config_started : OUT std_logic := '0';
231 dac_array : OUT dac_array_type ;
232 roi_array : OUT roi_array_type ;
233 config_data : INOUT std_logic_vector (15 DOWNTO 0)
234 );
235 END COMPONENT;
236 COMPONENT dataRAM_64b_16b_width14_5
237 PORT (
238 clka : IN std_logic ;
239 dina : IN std_logic_VECTOR (63 DOWNTO 0);
240 addra : IN std_logic_VECTOR (14 DOWNTO 0);
241 wea : IN std_logic_VECTOR (0 DOWNTO 0);
242 clkb : IN std_logic ;
243 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
244 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
245 );
246 END COMPONENT;
247 COMPONENT data_generator
248 GENERIC (
249 RAM_ADDR_WIDTH : integer := 12
250 );
251 PORT (
252 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
253 clk : IN std_logic ;
254 data_out : OUT std_logic_vector (63 DOWNTO 0);
255 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
256 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";
257 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
258 ram_write_ea : IN std_logic ;
259 ram_write_ready : OUT std_logic := '0';
260 -- --
261 ram_write_ready_ack : IN std_logic ;
262 -- --
263 config_start_mm : OUT std_logic := '0';
264 -- --
265 config_start_cm : OUT std_logic := '0';
266 -- --
267 config_start_spi : OUT std_logic := '0';
268 config_ready_mm : IN std_logic ;
269 config_ready_cm : IN std_logic ;
270 config_ready_spi : IN std_logic ;
271 config_started_mm : IN std_logic ;
272 config_started_cm : IN std_logic ;
273 config_started_spi : IN std_logic ;
274 roi_array : IN roi_array_type ;
275 roi_max : IN roi_max_type ;
276 sensor_array : IN sensor_array_type ;
277 sensor_ready : IN std_logic ;
278 dac_array : IN dac_array_type ;
279 package_length : IN std_logic_vector (15 DOWNTO 0);
280 board_id : IN std_logic_vector (3 DOWNTO 0);
281 crate_id : IN std_logic_vector (1 DOWNTO 0);
282 trigger_id : IN std_logic_vector (47 DOWNTO 0);
283 trigger : IN std_logic ;
284 -- s_trigger : in std_logic;
285 new_config : IN std_logic ;
286 config_started : OUT std_logic := '0';
287 adc_data_array : IN adc_data_array_type ;
288 adc_oeb : OUT std_logic := '1';
289 adc_clk_en : OUT std_logic := '0';
290 adc_otr : IN std_logic_vector (3 DOWNTO 0);
291 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
292 drs_dwrite : OUT std_logic := '1';
293 drs_clk_en : OUT std_logic := '0';
294 drs_read_s_cell : OUT std_logic := '0';
295 drs_srin_write_8b : OUT std_logic := '0';
296 drs_srin_write_ack : IN std_logic ;
297 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
298 drs_srin_write_ready : IN std_logic ;
299 drs_read_s_cell_ready : IN std_logic ;
300 drs_s_cell_array : IN drs_s_cell_array_type
301 );
302 END COMPONENT;
303 COMPONENT drs_pulser
304 PORT (
305 CLK : IN std_logic;
306 SROUT_in_0 : IN std_logic;
307 SROUT_in_1 : IN std_logic;
308 SROUT_in_2 : IN std_logic;
309 SROUT_in_3 : IN std_logic;
310 srin_data : IN std_logic_vector (7 DOWNTO 0);
311 start_endless_mode : IN std_logic;
312 start_read_stop_pos_mode : IN std_logic;
313 start_srin_write_8b : IN std_logic;
314 RSRLOAD : OUT std_logic := '0';
315 SRCLK : OUT std_logic := '0';
316 SRIN_out : OUT std_logic := '0';
317 srin_write_ack : OUT std_logic := '0';
318 srin_write_ready : OUT std_logic := '0';
319 stop_pos : OUT drs_s_cell_array_type;
320 stop_pos_valid : OUT std_logic := '0'
321 );
322 END COMPONENT;
323 COMPONENT led_controller
324 GENERIC (
325 HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz
326 MAX_DELAY : integer := 100;
327 WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz
328 );
329 PORT (
330 CLK : IN std_logic;
331 socks_connected : IN std_logic;
332 socks_waiting : IN std_logic;
333 trigger : IN std_logic;
334 amber : OUT std_logic;
335 green : OUT std_logic;
336 red : OUT std_logic
337 );
338 END COMPONENT;
339 COMPONENT memory_manager
340 GENERIC (
341 RAM_ADDR_WIDTH_64B : integer := 12;
342 RAM_ADDR_WIDTH_16B : integer := 14
343 );
344 PORT (
345 clk : IN std_logic ;
346 config_start : IN std_logic ;
347 ram_write_ready : IN std_logic ;
348 -- --
349 ram_write_ready_ack : OUT std_logic := '0';
350 -- --
351 roi_array : IN roi_array_type ;
352 ram_write_ea : OUT std_logic := '0';
353 config_ready : OUT std_logic := '0';
354 config_started : OUT std_logic := '0';
355 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
356 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
357 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
358 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
359 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
360 wiz_write_ea : OUT std_logic := '0';
361 wiz_write_header : OUT std_logic := '0';
362 wiz_write_end : OUT std_logic := '0';
363 wiz_busy : IN std_logic ;
364 wiz_ack : IN std_logic ;
365 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
366 );
367 END COMPONENT;
368 COMPONENT spi_interface
369 PORT (
370 clk_50MHz : IN std_logic ;
371 config_start : IN std_logic ;
372 dac_array : IN dac_array_type ;
373 config_ready : OUT std_logic ;
374 config_started : OUT std_logic := '0';
375 dac_cs : OUT std_logic ;
376 mosi : OUT std_logic := '0';
377 sclk : OUT std_logic ;
378 sensor_array : OUT sensor_array_type ;
379 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
380 sensor_ready : OUT std_logic ;
381 miso : INOUT std_logic
382 );
383 END COMPONENT;
384 COMPONENT trigger_counter
385 PORT (
386 trigger_id : OUT std_logic_vector (47 DOWNTO 0);
387 trigger : IN std_logic ;
388 clk : IN std_logic
389 );
390 END COMPONENT;
391 COMPONENT w5300_modul
392 GENERIC (
393 RAM_ADDR_WIDTH : integer := 14
394 );
395 PORT (
396 clk : IN std_logic ;
397 wiz_reset : OUT std_logic := '1';
398 addr : OUT std_logic_vector (9 DOWNTO 0);
399 data : INOUT std_logic_vector (15 DOWNTO 0);
400 cs : OUT std_logic := '1';
401 wr : OUT std_logic := '1';
402 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
403 rd : OUT std_logic := '1';
404 int : IN std_logic ;
405 write_length : IN std_logic_vector (16 DOWNTO 0);
406 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
407 ram_data : IN std_logic_vector (15 DOWNTO 0);
408 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
409 data_valid : IN std_logic ;
410 data_valid_ack : OUT std_logic := '0';
411 busy : OUT std_logic := '1';
412 write_header_flag : IN std_logic ;
413 write_end_flag : IN std_logic ;
414 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
415 s_trigger : OUT std_logic := '0';
416 new_config : OUT std_logic := '0';
417 config_started : IN std_logic ;
418 config_addr : OUT std_logic_vector (7 DOWNTO 0);
419 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
420 config_wr_en : OUT std_logic := '0';
421 config_rd_en : OUT std_logic := '0';
422 -- --
423 config_rw_ack : IN std_logic ;
424 -- --
425 config_rw_ready : IN std_logic ;
426 -- --
427 config_busy : IN std_logic ;
428 denable : OUT std_logic := '0'; -- default domino wave off
429 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.
430 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
431 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
432 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
433 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
434 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.
435 socks_waiting : OUT std_logic ;
436 socks_connected : OUT std_logic
437 );
438 END COMPONENT;
439
440 -- Optional embedded configurations
441 -- pragma synthesis_off
442 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
443 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
444 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
445 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
446 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
447 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
448 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
449 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
450 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
451 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
452 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
453 -- pragma synthesis_on
454
455
456BEGIN
457
458 -- ModuleWare code(v1.9) for instance 'I5' of 'and'
459 drs_dwrite <= dwrite AND dwrite_enable;
460
461 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
462 SRCLK <= SRCLK1 AND srclk_enable;
463
464 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
465 sclk <= sclk_enable AND sclk1;
466
467 -- ModuleWare code(v1.9) for instance 'U_3' of 'assignment'
468 PS_DO_IN <= ps_do_phase_shift;
469
470 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
471 PS_DIR_IN <= ps_direction;
472
473 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
474 CLK50_OUT <= CLK_50_internal;
475
476 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
477 CLK25_OUT <= CLK_25;
478
479 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
480 CLK25_PSOUT <= CLK_25_PS_internal;
481
482 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
483 u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
484 drs_address_mode)
485 BEGIN
486 CASE drs_address_mode IS
487 WHEN '0' => drs_channel_id <= drs_channel_internal;
488 WHEN '1' => drs_channel_id <= drs_address;
489 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
490 END CASE;
491 END PROCESS u_0combo_proc;
492
493 -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
494 trigger_out <= s_trigger OR trigger;
495
496 -- Instance port mappings.
497 I_main_adc_buffer : adc_buffer
498 PORT MAP (
499 clk_ps => CLK_25_PS_internal,
500 adc_data_array => adc_data_array,
501 adc_otr_array => adc_otr_array,
502 adc_data_array_int => adc_data_array_int,
503 adc_otr => adc_otr
504 );
505 U_2 : clock_generator_var_ps
506 PORT MAP (
507 CLK => CLK,
508 RST_IN => ps_reset,
509 direction => ps_direction,
510 do_shift => ps_do_phase_shift,
511 CLK_25 => CLK_25,
512 CLK_25_PS => CLK_25_PS_internal,
513 CLK_50 => CLK_50_internal,
514 DCM_locked => DCM_locked,
515 LOCKED_extraOUT => LOCKED_extraOUT,
516 PSCLK_OUT => PSCLK_OUT,
517 PSDONE_extraOUT => PSDONE_extraOUT,
518 PSEN_OUT => PSEN_OUT,
519 PSINCDEC_OUT => PSINCDEC_OUT,
520 offset => offset,
521 ready => ready,
522 shifting => shifting
523 );
524 I_main_control_unit : control_unit
525 PORT MAP (
526 clk => CLK_50_internal,
527 config_addr => config_addr,
528 config_rd_en => config_rd_en,
529 config_start => config_start_cm,
530 config_wr_en => config_wr_en,
531 config_busy => config_busy,
532 config_data_valid => config_data_valid,
533 config_ready => config_ready_cm,
534 config_rw_ack => config_rw_ack,
535 config_rw_ready => config_rw_ready,
536 config_started => config_started_cu,
537 dac_array => dac_array,
538 roi_array => roi_array,
539 config_data => config_data
540 );
541 U_4 : dataRAM_64b_16b_width14_5
542 PORT MAP (
543 clka => CLK_25,
544 dina => data_out,
545 addra => addr_out,
546 wea => write_ea,
547 clkb => CLK_50_internal,
548 addrb => ram_addr,
549 doutb => ram_data
550 );
551 I_main_data_generator : data_generator
552 GENERIC MAP (
553 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
554 )
555 PORT MAP (
556 clk => CLK_25,
557 data_out => data_out,
558 addr_out => addr_out,
559 write_ea => write_ea,
560 ram_start_addr => ram_start_addr,
561 ram_write_ea => ram_write_ea,
562 ram_write_ready => ram_write_ready,
563 ram_write_ready_ack => ram_write_ready_ack,
564 config_start_mm => config_start,
565 config_start_cm => config_start_cm,
566 config_start_spi => config_start_spi,
567 config_ready_mm => config_ready,
568 config_ready_cm => config_ready_cm,
569 config_ready_spi => config_ready_spi,
570 config_started_mm => config_started_mm,
571 config_started_cm => config_started_cu,
572 config_started_spi => config_started_spi,
573 roi_array => roi_array,
574 roi_max => roi_max,
575 sensor_array => sensor_array,
576 sensor_ready => sensor_ready,
577 dac_array => dac_array,
578 package_length => package_length,
579 board_id => board_id,
580 crate_id => crate_id,
581 trigger_id => trigger_id,
582 trigger => trigger_out,
583 new_config => new_config,
584 config_started => config_started,
585 adc_data_array => adc_data_array_int,
586 adc_oeb => adc_oeb,
587 adc_clk_en => adc_clk_en,
588 adc_otr => adc_otr,
589 drs_channel_id => drs_channel_internal,
590 drs_dwrite => dwrite,
591 drs_clk_en => drs_clk_en,
592 drs_read_s_cell => drs_read_s_cell,
593 drs_srin_write_8b => start_srin_write_8b,
594 drs_srin_write_ack => srin_write_ack,
595 drs_srin_data => drs_srin_data,
596 drs_srin_write_ready => srin_write_ready,
597 drs_read_s_cell_ready => drs_read_s_cell_ready,
598 drs_s_cell_array => drs_s_cell_array
599 );
600 I_main_drs_pulser : drs_pulser
601 PORT MAP (
602 CLK => CLK_25,
603 start_endless_mode => drs_clk_en,
604 start_read_stop_pos_mode => drs_read_s_cell,
605 SROUT_in_0 => SROUT_in_0,
606 SROUT_in_1 => SROUT_in_1,
607 SROUT_in_2 => SROUT_in_2,
608 SROUT_in_3 => SROUT_in_3,
609 stop_pos => drs_s_cell_array,
610 stop_pos_valid => drs_read_s_cell_ready,
611 start_srin_write_8b => start_srin_write_8b,
612 srin_write_ready => srin_write_ready,
613 srin_write_ack => srin_write_ack,
614 srin_data => drs_srin_data,
615 SRIN_out => SRIN_out,
616 RSRLOAD => RSRLOAD,
617 SRCLK => SRCLK1
618 );
619 U_10 : led_controller
620 GENERIC MAP (
621 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz
622 MAX_DELAY => 100,
623 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz
624 )
625 PORT MAP (
626 CLK => CLK_50_internal,
627 green => green,
628 amber => amber,
629 red => red,
630 trigger => trigger_out,
631 socks_waiting => socks_waiting,
632 socks_connected => socks_connected
633 );
634 I_main_memory_manager : memory_manager
635 GENERIC MAP (
636 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
637 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
638 )
639 PORT MAP (
640 clk => CLK_25,
641 config_start => config_start,
642 ram_write_ready => ram_write_ready,
643 ram_write_ready_ack => ram_write_ready_ack,
644 roi_array => roi_array,
645 ram_write_ea => ram_write_ea,
646 config_ready => config_ready,
647 config_started => config_started_mm,
648 roi_max => roi_max,
649 package_length => package_length,
650 wiz_ram_start_addr => wiz_ram_start_addr,
651 wiz_write_length => wiz_write_length,
652 wiz_number_of_channels => wiz_number_of_channels,
653 wiz_write_ea => wiz_write_ea,
654 wiz_write_header => wiz_write_header,
655 wiz_write_end => wiz_write_end,
656 wiz_busy => wiz_busy,
657 wiz_ack => wiz_ack,
658 ram_start_addr => ram_start_addr
659 );
660 I_main_SPI_interface : spi_interface
661 PORT MAP (
662 clk_50MHz => CLK_50_internal,
663 config_start => config_start_spi,
664 dac_array => dac_array,
665 config_ready => config_ready_spi,
666 config_started => config_started_spi,
667 dac_cs => dac_cs,
668 mosi => mosi,
669 sclk => sclk1,
670 sensor_array => sensor_array,
671 sensor_cs => sensor_cs,
672 sensor_ready => sensor_ready,
673 miso => sio
674 );
675 I_main_ext_trigger : trigger_counter
676 PORT MAP (
677 trigger_id => trigger_id,
678 trigger => trigger_out,
679 clk => CLK_25_PS_internal
680 );
681 I_main_ethernet : w5300_modul
682 GENERIC MAP (
683 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
684 )
685 PORT MAP (
686 clk => CLK_50_internal,
687 wiz_reset => wiz_reset,
688 addr => wiz_addr,
689 data => wiz_data,
690 cs => wiz_cs,
691 wr => wiz_wr,
692 led => led,
693 rd => wiz_rd,
694 int => wiz_int,
695 write_length => wiz_write_length,
696 ram_start_addr => wiz_ram_start_addr,
697 ram_data => ram_data,
698 ram_addr => ram_addr,
699 data_valid => wiz_write_ea,
700 data_valid_ack => wiz_ack,
701 busy => wiz_busy,
702 write_header_flag => wiz_write_header,
703 write_end_flag => wiz_write_end,
704 fifo_channels => wiz_number_of_channels,
705 s_trigger => s_trigger,
706 new_config => new_config,
707 config_started => config_started,
708 config_addr => config_addr,
709 config_data => config_data,
710 config_wr_en => config_wr_en,
711 config_rd_en => config_rd_en,
712 config_rw_ack => config_rw_ack,
713 config_rw_ready => config_rw_ready,
714 config_busy => config_busy,
715 denable => denable,
716 dwrite_enable => dwrite_enable,
717 sclk_enable => sclk_enable,
718 ps_direction => ps_direction,
719 ps_do_phase_shift => ps_do_phase_shift,
720 ps_reset => ps_reset,
721 srclk_enable => srclk_enable,
722 socks_waiting => socks_waiting,
723 socks_connected => socks_connected
724 );
725
726 -- Implicit buffered output assignments
727 CLK_25_PS <= CLK_25_PS_internal;
728 CLK_50 <= CLK_50_internal;
729
730END struct;
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