source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 10081

Last change on this file since 10081 was 10081, checked in by neise, 12 years ago
DRS write shift register & write config register
File size: 33.1 KB
Line 
1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 17:46:33 05.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 SROUT_in_0 : IN std_logic;
22 SROUT_in_1 : IN std_logic;
23 SROUT_in_2 : IN std_logic;
24 SROUT_in_3 : IN std_logic;
25 adc_data_array : IN adc_data_array_type;
26 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
27 board_id : IN std_logic_vector (3 DOWNTO 0);
28 crate_id : IN std_logic_vector (1 DOWNTO 0);
29 trigger : IN std_logic;
30 wiz_int : IN std_logic;
31 CLK25_OUT : OUT std_logic;
32 CLK25_PSOUT : OUT std_logic;
33 CLK50_OUT : OUT std_logic;
34 CLK_25_PS : OUT std_logic;
35 CLK_50 : OUT std_logic;
36 DCM_locked : OUT std_logic;
37 LOCKED_extraOUT : OUT std_logic;
38 PSCLK_OUT : OUT std_logic;
39 PSDONE_extraOUT : OUT std_logic;
40 PSEN_OUT : OUT std_logic;
41 PSINCDEC_OUT : OUT std_logic;
42 PS_DIR_IN : OUT std_logic;
43 PS_DO_IN : OUT std_logic;
44 RSRLOAD : OUT std_logic := '0';
45 SRCLK : OUT std_logic := '0';
46 SRIN_out : OUT std_logic := '0';
47 adc_clk_en : OUT std_logic := '0';
48 adc_oeb : OUT std_logic := '1';
49 amber : OUT std_logic;
50 dac_cs : OUT std_logic;
51 denable : OUT std_logic := '0'; -- default domino wave off
52 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
53 drs_dwrite : OUT std_logic := '1';
54 green : OUT std_logic;
55 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
56 mosi : OUT std_logic := '0';
57 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
58 ready : OUT std_logic := '0';
59 red : OUT std_logic;
60 sclk : OUT std_logic;
61 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
62 -- status:
63 shifting : OUT std_logic := '0';
64 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
65 wiz_cs : OUT std_logic := '1';
66 wiz_rd : OUT std_logic := '1';
67 wiz_reset : OUT std_logic := '1';
68 wiz_wr : OUT std_logic := '1';
69 sio : INOUT std_logic;
70 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
71 );
72
73-- Declarations
74
75END FAD_main ;
76
77--
78-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
79--
80-- Created:
81-- by - dneise.UNKNOWN (E5B-LABOR6)
82-- at - 17:46:34 05.01.2011
83--
84-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
85--
86library ieee;
87use ieee.std_logic_1164.all;
88use IEEE.STD_LOGIC_ARITH.all;
89use ieee.STD_LOGIC_UNSIGNED.all;
90
91library fact_fad_lib;
92use fact_fad_lib.fad_definitions.all;
93
94library UNISIM;
95use UNISIM.VComponents.all;
96USE IEEE.NUMERIC_STD.all;
97USE IEEE.std_logic_signed.all;
98
99LIBRARY FACT_FAD_lib;
100
101ARCHITECTURE struct OF FAD_main IS
102
103 -- Architecture declarations
104
105 -- Internal signal declarations
106 SIGNAL CLK_25 : std_logic;
107 SIGNAL SRCLK1 : std_logic := '0';
108 SIGNAL adc_data_array_int : adc_data_array_type;
109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
110 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
111 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);
112 SIGNAL config_busy : std_logic;
113 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);
114 SIGNAL config_data_valid : std_logic;
115 SIGNAL config_rd_en : std_logic;
116 SIGNAL config_ready : std_logic;
117 SIGNAL config_ready_cm : std_logic;
118 SIGNAL config_ready_spi : std_logic;
119 -- --
120 SIGNAL config_rw_ack : std_logic := '0';
121 -- --
122 SIGNAL config_rw_ready : std_logic := '0';
123 SIGNAL config_start : std_logic := '0';
124 SIGNAL config_start_cm : std_logic;
125 SIGNAL config_start_spi : std_logic := '0';
126 SIGNAL config_started : std_logic;
127 SIGNAL config_started_cu : std_logic := '0';
128 SIGNAL config_started_mm : std_logic;
129 SIGNAL config_started_spi : std_logic := '0';
130 SIGNAL config_wr_en : std_logic;
131 SIGNAL dac_array : dac_array_type;
132 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
133 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0');
134 SIGNAL drs_address_mode : std_logic;
135 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0');
136 SIGNAL drs_clk_en : std_logic := '0';
137 SIGNAL drs_read_s_cell : std_logic := '0';
138 SIGNAL drs_read_s_cell_ready : std_logic;
139 SIGNAL drs_readout_started : std_logic;
140 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
141 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
142 SIGNAL dwrite : std_logic := '1';
143 SIGNAL dwrite_enable : std_logic := '1';
144 SIGNAL new_config : std_logic := '0';
145 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
146 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
147 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
148 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
149 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
150 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
151 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
152 SIGNAL ram_write_ea : std_logic;
153 SIGNAL ram_write_ready : std_logic := '0';
154 -- --
155 SIGNAL ram_write_ready_ack : std_logic := '0';
156 SIGNAL roi_array : roi_array_type;
157 SIGNAL roi_max : roi_max_type;
158 SIGNAL s_trigger : std_logic;
159 SIGNAL sclk1 : std_logic;
160 SIGNAL sclk_enable : std_logic;
161 SIGNAL sensor_array : sensor_array_type;
162 SIGNAL sensor_ready : std_logic;
163 SIGNAL socks_connected : std_logic;
164 SIGNAL socks_waiting : std_logic;
165 SIGNAL srclk_enable : std_logic := '0';
166 SIGNAL srin_write_ack : std_logic := '0';
167 SIGNAL srin_write_ready : std_logic := '0';
168 SIGNAL start_srin_write_8b : std_logic;
169 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);
170 SIGNAL trigger_out : std_logic;
171 SIGNAL wiz_ack : std_logic;
172 SIGNAL wiz_busy : std_logic;
173 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
174 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
175 SIGNAL wiz_write_ea : std_logic := '0';
176 SIGNAL wiz_write_end : std_logic := '0';
177 SIGNAL wiz_write_header : std_logic := '0';
178 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
179 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
180
181 -- Implicit buffer signal declarations
182 SIGNAL CLK_25_PS_internal : std_logic;
183 SIGNAL CLK_50_internal : std_logic;
184
185
186 -- Component Declarations
187 COMPONENT adc_buffer
188 PORT (
189 adc_data_array : IN adc_data_array_type;
190 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
191 clk_ps : IN std_logic;
192 adc_data_array_int : OUT adc_data_array_type;
193 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
194 );
195 END COMPONENT;
196 COMPONENT clock_generator_var_ps
197 PORT (
198 CLK : IN std_logic ;
199 RST_IN : IN std_logic ;
200 direction : IN std_logic ;
201 do_shift : IN std_logic ;
202 CLK_25 : OUT std_logic ;
203 CLK_25_PS : OUT std_logic ;
204 CLK_50 : OUT std_logic ;
205 DCM_locked : OUT std_logic ;
206 LOCKED_extraOUT : OUT std_logic ;
207 PSCLK_OUT : OUT std_logic ;
208 PSDONE_extraOUT : OUT std_logic ;
209 PSEN_OUT : OUT std_logic ;
210 PSINCDEC_OUT : OUT std_logic ;
211 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
212 ready : OUT std_logic := '0';
213 -- status:
214 shifting : OUT std_logic := '0'
215 );
216 END COMPONENT;
217 COMPONENT control_unit
218 PORT (
219 clk : IN STD_LOGIC ;
220 config_addr : IN std_logic_vector (7 DOWNTO 0);
221 config_rd_en : IN std_logic ;
222 config_start : IN std_logic ;
223 config_wr_en : IN std_logic ;
224 config_busy : OUT std_logic ;
225 config_data_valid : OUT std_logic ;
226 config_ready : OUT std_logic ;
227 -- --
228 config_rw_ack : OUT std_logic := '0';
229 -- --
230 config_rw_ready : OUT std_logic := '0';
231 config_started : OUT std_logic := '0';
232 dac_array : OUT dac_array_type ;
233 roi_array : OUT roi_array_type ;
234 config_data : INOUT std_logic_vector (15 DOWNTO 0)
235 );
236 END COMPONENT;
237 COMPONENT dataRAM_64b_16b_width14_5
238 PORT (
239 clka : IN std_logic ;
240 dina : IN std_logic_VECTOR (63 DOWNTO 0);
241 addra : IN std_logic_VECTOR (14 DOWNTO 0);
242 wea : IN std_logic_VECTOR (0 DOWNTO 0);
243 clkb : IN std_logic ;
244 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
245 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
246 );
247 END COMPONENT;
248 COMPONENT data_generator
249 GENERIC (
250 RAM_ADDR_WIDTH : integer := 12
251 );
252 PORT (
253 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
254 clk : IN std_logic ;
255 data_out : OUT std_logic_vector (63 DOWNTO 0);
256 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
257 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";
258 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
259 ram_write_ea : IN std_logic ;
260 ram_write_ready : OUT std_logic := '0';
261 -- --
262 ram_write_ready_ack : IN std_logic ;
263 -- --
264 config_start_mm : OUT std_logic := '0';
265 -- --
266 config_start_cm : OUT std_logic := '0';
267 -- --
268 config_start_spi : OUT std_logic := '0';
269 config_ready_mm : IN std_logic ;
270 config_ready_cm : IN std_logic ;
271 config_ready_spi : IN std_logic ;
272 config_started_mm : IN std_logic ;
273 config_started_cm : IN std_logic ;
274 config_started_spi : IN std_logic ;
275 roi_array : IN roi_array_type ;
276 roi_max : IN roi_max_type ;
277 sensor_array : IN sensor_array_type ;
278 sensor_ready : IN std_logic ;
279 dac_array : IN dac_array_type ;
280 package_length : IN std_logic_vector (15 DOWNTO 0);
281 board_id : IN std_logic_vector (3 DOWNTO 0);
282 crate_id : IN std_logic_vector (1 DOWNTO 0);
283 trigger_id : IN std_logic_vector (47 DOWNTO 0);
284 trigger : IN std_logic ;
285 -- s_trigger : in std_logic;
286 new_config : IN std_logic ;
287 config_started : OUT std_logic := '0';
288 adc_data_array : IN adc_data_array_type ;
289 adc_oeb : OUT std_logic := '1';
290 adc_clk_en : OUT std_logic := '0';
291 adc_otr : IN std_logic_vector (3 DOWNTO 0);
292 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
293 drs_dwrite : OUT std_logic := '1';
294 drs_clk_en : OUT std_logic := '0';
295 drs_read_s_cell : OUT std_logic := '0';
296 drs_srin_write_8b : OUT std_logic := '0';
297 drs_srin_write_ack : IN std_logic ;
298 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
299 drs_srin_write_ready : IN std_logic ;
300 drs_read_s_cell_ready : IN std_logic ;
301 drs_s_cell_array : IN drs_s_cell_array_type ;
302 drs_readout_started : OUT std_logic
303 );
304 END COMPONENT;
305 COMPONENT drs_pulser
306 PORT (
307 CLK : IN std_logic;
308 SROUT_in_0 : IN std_logic;
309 SROUT_in_1 : IN std_logic;
310 SROUT_in_2 : IN std_logic;
311 SROUT_in_3 : IN std_logic;
312 srin_data : IN std_logic_vector (7 DOWNTO 0);
313 start_endless_mode : IN std_logic;
314 start_read_stop_pos_mode : IN std_logic;
315 start_srin_write_8b : IN std_logic;
316 RSRLOAD : OUT std_logic := '0';
317 SRCLK : OUT std_logic := '0';
318 SRIN_out : OUT std_logic := '0';
319 srin_write_ack : OUT std_logic := '0';
320 srin_write_ready : OUT std_logic := '0';
321 stop_pos : OUT drs_s_cell_array_type;
322 stop_pos_valid : OUT std_logic := '0'
323 );
324 END COMPONENT;
325 COMPONENT led_controller
326 GENERIC (
327 HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz
328 MAX_DELAY : integer := 100;
329 WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz
330 );
331 PORT (
332 CLK : IN std_logic;
333 socks_connected : IN std_logic;
334 socks_waiting : IN std_logic;
335 trigger : IN std_logic;
336 amber : OUT std_logic;
337 green : OUT std_logic;
338 red : OUT std_logic
339 );
340 END COMPONENT;
341 COMPONENT memory_manager
342 GENERIC (
343 RAM_ADDR_WIDTH_64B : integer := 12;
344 RAM_ADDR_WIDTH_16B : integer := 14
345 );
346 PORT (
347 clk : IN std_logic ;
348 config_start : IN std_logic ;
349 ram_write_ready : IN std_logic ;
350 -- --
351 ram_write_ready_ack : OUT std_logic := '0';
352 -- --
353 roi_array : IN roi_array_type ;
354 ram_write_ea : OUT std_logic := '0';
355 config_ready : OUT std_logic := '0';
356 config_started : OUT std_logic := '0';
357 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
358 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
359 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
360 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
361 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
362 wiz_write_ea : OUT std_logic := '0';
363 wiz_write_header : OUT std_logic := '0';
364 wiz_write_end : OUT std_logic := '0';
365 wiz_busy : IN std_logic ;
366 wiz_ack : IN std_logic ;
367 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
368 );
369 END COMPONENT;
370 COMPONENT spi_interface
371 PORT (
372 clk_50MHz : IN std_logic ;
373 config_start : IN std_logic ;
374 dac_array : IN dac_array_type ;
375 config_ready : OUT std_logic ;
376 config_started : OUT std_logic := '0';
377 dac_cs : OUT std_logic ;
378 mosi : OUT std_logic := '0';
379 sclk : OUT std_logic ;
380 sensor_array : OUT sensor_array_type ;
381 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
382 sensor_ready : OUT std_logic ;
383 miso : INOUT std_logic
384 );
385 END COMPONENT;
386 COMPONENT trigger_counter
387 PORT (
388 trigger_id : OUT std_logic_vector (47 DOWNTO 0);
389 trigger : IN std_logic ;
390 clk : IN std_logic
391 );
392 END COMPONENT;
393 COMPONENT w5300_modul
394 GENERIC (
395 RAM_ADDR_WIDTH : integer := 14
396 );
397 PORT (
398 clk : IN std_logic ;
399 wiz_reset : OUT std_logic := '1';
400 addr : OUT std_logic_vector (9 DOWNTO 0);
401 data : INOUT std_logic_vector (15 DOWNTO 0);
402 cs : OUT std_logic := '1';
403 wr : OUT std_logic := '1';
404 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
405 rd : OUT std_logic := '1';
406 int : IN std_logic ;
407 write_length : IN std_logic_vector (16 DOWNTO 0);
408 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
409 ram_data : IN std_logic_vector (15 DOWNTO 0);
410 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
411 data_valid : IN std_logic ;
412 data_valid_ack : OUT std_logic := '0';
413 busy : OUT std_logic := '1';
414 write_header_flag : IN std_logic ;
415 write_end_flag : IN std_logic ;
416 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
417 s_trigger : OUT std_logic := '0';
418 new_config : OUT std_logic := '0';
419 config_started : IN std_logic ;
420 config_addr : OUT std_logic_vector (7 DOWNTO 0);
421 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
422 config_wr_en : OUT std_logic := '0';
423 config_rd_en : OUT std_logic := '0';
424 -- --
425 config_rw_ack : IN std_logic ;
426 -- --
427 config_rw_ready : IN std_logic ;
428 -- --
429 config_busy : IN std_logic ;
430 denable : OUT std_logic := '0'; -- default domino wave off
431 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.
432 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
433 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
434 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
435 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
436 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.
437 socks_waiting : OUT std_logic ;
438 socks_connected : OUT std_logic
439 );
440 END COMPONENT;
441
442 -- Optional embedded configurations
443 -- pragma synthesis_off
444 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
445 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
446 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
447 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
448 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
449 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
450 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
451 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
452 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
453 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
454 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
455 -- pragma synthesis_on
456
457
458BEGIN
459
460 -- ModuleWare code(v1.9) for instance 'I5' of 'and'
461 drs_dwrite <= dwrite AND dwrite_enable;
462
463 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
464 SRCLK <= SRCLK1 AND srclk_enable;
465
466 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
467 sclk <= sclk_enable AND sclk1;
468
469 -- ModuleWare code(v1.9) for instance 'U_3' of 'assignment'
470 PS_DO_IN <= ps_do_phase_shift;
471
472 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
473 PS_DIR_IN <= ps_direction;
474
475 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
476 CLK50_OUT <= CLK_50_internal;
477
478 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
479 CLK25_OUT <= CLK_25;
480
481 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
482 CLK25_PSOUT <= CLK_25_PS_internal;
483
484 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
485 u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
486 drs_address_mode)
487 BEGIN
488 CASE drs_address_mode IS
489 WHEN '0' => drs_channel_id <= drs_channel_internal;
490 WHEN '1' => drs_channel_id <= drs_address;
491 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
492 END CASE;
493 END PROCESS u_0combo_proc;
494
495 -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
496 trigger_out <= s_trigger OR trigger;
497
498 -- Instance port mappings.
499 I_main_adc_buffer : adc_buffer
500 PORT MAP (
501 clk_ps => CLK_25_PS_internal,
502 adc_data_array => adc_data_array,
503 adc_otr_array => adc_otr_array,
504 adc_data_array_int => adc_data_array_int,
505 adc_otr => adc_otr
506 );
507 U_2 : clock_generator_var_ps
508 PORT MAP (
509 CLK => CLK,
510 RST_IN => ps_reset,
511 direction => ps_direction,
512 do_shift => ps_do_phase_shift,
513 CLK_25 => CLK_25,
514 CLK_25_PS => CLK_25_PS_internal,
515 CLK_50 => CLK_50_internal,
516 DCM_locked => DCM_locked,
517 LOCKED_extraOUT => LOCKED_extraOUT,
518 PSCLK_OUT => PSCLK_OUT,
519 PSDONE_extraOUT => PSDONE_extraOUT,
520 PSEN_OUT => PSEN_OUT,
521 PSINCDEC_OUT => PSINCDEC_OUT,
522 offset => offset,
523 ready => ready,
524 shifting => shifting
525 );
526 I_main_control_unit : control_unit
527 PORT MAP (
528 clk => CLK_50_internal,
529 config_addr => config_addr,
530 config_rd_en => config_rd_en,
531 config_start => config_start_cm,
532 config_wr_en => config_wr_en,
533 config_busy => config_busy,
534 config_data_valid => config_data_valid,
535 config_ready => config_ready_cm,
536 config_rw_ack => config_rw_ack,
537 config_rw_ready => config_rw_ready,
538 config_started => config_started_cu,
539 dac_array => dac_array,
540 roi_array => roi_array,
541 config_data => config_data
542 );
543 U_4 : dataRAM_64b_16b_width14_5
544 PORT MAP (
545 clka => CLK_25,
546 dina => data_out,
547 addra => addr_out,
548 wea => write_ea,
549 clkb => CLK_50_internal,
550 addrb => ram_addr,
551 doutb => ram_data
552 );
553 I_main_data_generator : data_generator
554 GENERIC MAP (
555 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
556 )
557 PORT MAP (
558 clk => CLK_25,
559 data_out => data_out,
560 addr_out => addr_out,
561 write_ea => write_ea,
562 ram_start_addr => ram_start_addr,
563 ram_write_ea => ram_write_ea,
564 ram_write_ready => ram_write_ready,
565 ram_write_ready_ack => ram_write_ready_ack,
566 config_start_mm => config_start,
567 config_start_cm => config_start_cm,
568 config_start_spi => config_start_spi,
569 config_ready_mm => config_ready,
570 config_ready_cm => config_ready_cm,
571 config_ready_spi => config_ready_spi,
572 config_started_mm => config_started_mm,
573 config_started_cm => config_started_cu,
574 config_started_spi => config_started_spi,
575 roi_array => roi_array,
576 roi_max => roi_max,
577 sensor_array => sensor_array,
578 sensor_ready => sensor_ready,
579 dac_array => dac_array,
580 package_length => package_length,
581 board_id => board_id,
582 crate_id => crate_id,
583 trigger_id => trigger_id,
584 trigger => trigger_out,
585 new_config => new_config,
586 config_started => config_started,
587 adc_data_array => adc_data_array_int,
588 adc_oeb => adc_oeb,
589 adc_clk_en => adc_clk_en,
590 adc_otr => adc_otr,
591 drs_channel_id => drs_channel_internal,
592 drs_dwrite => dwrite,
593 drs_clk_en => drs_clk_en,
594 drs_read_s_cell => drs_read_s_cell,
595 drs_srin_write_8b => start_srin_write_8b,
596 drs_srin_write_ack => srin_write_ack,
597 drs_srin_data => drs_srin_data,
598 drs_srin_write_ready => srin_write_ready,
599 drs_read_s_cell_ready => drs_read_s_cell_ready,
600 drs_s_cell_array => drs_s_cell_array,
601 drs_readout_started => drs_readout_started
602 );
603 I_main_drs_pulser : drs_pulser
604 PORT MAP (
605 CLK => CLK_25,
606 start_endless_mode => drs_clk_en,
607 start_read_stop_pos_mode => drs_read_s_cell,
608 SROUT_in_0 => SROUT_in_0,
609 SROUT_in_1 => SROUT_in_1,
610 SROUT_in_2 => SROUT_in_2,
611 SROUT_in_3 => SROUT_in_3,
612 stop_pos => drs_s_cell_array,
613 stop_pos_valid => drs_read_s_cell_ready,
614 start_srin_write_8b => start_srin_write_8b,
615 srin_write_ready => srin_write_ready,
616 srin_write_ack => srin_write_ack,
617 srin_data => drs_srin_data,
618 SRIN_out => SRIN_out,
619 RSRLOAD => RSRLOAD,
620 SRCLK => SRCLK1
621 );
622 U_10 : led_controller
623 GENERIC MAP (
624 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz
625 MAX_DELAY => 100,
626 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz
627 )
628 PORT MAP (
629 CLK => CLK_50_internal,
630 green => green,
631 amber => amber,
632 red => red,
633 trigger => drs_readout_started,
634 socks_waiting => socks_waiting,
635 socks_connected => socks_connected
636 );
637 I_main_memory_manager : memory_manager
638 GENERIC MAP (
639 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
640 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
641 )
642 PORT MAP (
643 clk => CLK_25,
644 config_start => config_start,
645 ram_write_ready => ram_write_ready,
646 ram_write_ready_ack => ram_write_ready_ack,
647 roi_array => roi_array,
648 ram_write_ea => ram_write_ea,
649 config_ready => config_ready,
650 config_started => config_started_mm,
651 roi_max => roi_max,
652 package_length => package_length,
653 wiz_ram_start_addr => wiz_ram_start_addr,
654 wiz_write_length => wiz_write_length,
655 wiz_number_of_channels => wiz_number_of_channels,
656 wiz_write_ea => wiz_write_ea,
657 wiz_write_header => wiz_write_header,
658 wiz_write_end => wiz_write_end,
659 wiz_busy => wiz_busy,
660 wiz_ack => wiz_ack,
661 ram_start_addr => ram_start_addr
662 );
663 I_main_SPI_interface : spi_interface
664 PORT MAP (
665 clk_50MHz => CLK_50_internal,
666 config_start => config_start_spi,
667 dac_array => dac_array,
668 config_ready => config_ready_spi,
669 config_started => config_started_spi,
670 dac_cs => dac_cs,
671 mosi => mosi,
672 sclk => sclk1,
673 sensor_array => sensor_array,
674 sensor_cs => sensor_cs,
675 sensor_ready => sensor_ready,
676 miso => sio
677 );
678 I_main_ext_trigger : trigger_counter
679 PORT MAP (
680 trigger_id => trigger_id,
681 trigger => trigger_out,
682 clk => CLK_25_PS_internal
683 );
684 I_main_ethernet : w5300_modul
685 GENERIC MAP (
686 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
687 )
688 PORT MAP (
689 clk => CLK_50_internal,
690 wiz_reset => wiz_reset,
691 addr => wiz_addr,
692 data => wiz_data,
693 cs => wiz_cs,
694 wr => wiz_wr,
695 led => led,
696 rd => wiz_rd,
697 int => wiz_int,
698 write_length => wiz_write_length,
699 ram_start_addr => wiz_ram_start_addr,
700 ram_data => ram_data,
701 ram_addr => ram_addr,
702 data_valid => wiz_write_ea,
703 data_valid_ack => wiz_ack,
704 busy => wiz_busy,
705 write_header_flag => wiz_write_header,
706 write_end_flag => wiz_write_end,
707 fifo_channels => wiz_number_of_channels,
708 s_trigger => s_trigger,
709 new_config => new_config,
710 config_started => config_started,
711 config_addr => config_addr,
712 config_data => config_data,
713 config_wr_en => config_wr_en,
714 config_rd_en => config_rd_en,
715 config_rw_ack => config_rw_ack,
716 config_rw_ready => config_rw_ready,
717 config_busy => config_busy,
718 denable => denable,
719 dwrite_enable => dwrite_enable,
720 sclk_enable => sclk_enable,
721 ps_direction => ps_direction,
722 ps_do_phase_shift => ps_do_phase_shift,
723 ps_reset => ps_reset,
724 srclk_enable => srclk_enable,
725 socks_waiting => socks_waiting,
726 socks_connected => socks_connected
727 );
728
729 -- Implicit buffered output assignments
730 CLK_25_PS <= CLK_25_PS_internal;
731 CLK_50 <= CLK_50_internal;
732
733END struct;
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