source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 10121

Last change on this file since 10121 was 10121, checked in by neise, 12 years ago
synchronous trigger handling added continous soft trigger generation. ---> control frequency via 'send 0x21??' each step increases trigger delay by 12.5ms 0x2100 = 40Hz 0x21FF = 0.3Hz
File size: 36.3 KB
Line 
1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 16:46:18 26.01.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 SROUT_in_0 : IN std_logic;
22 SROUT_in_1 : IN std_logic;
23 SROUT_in_2 : IN std_logic;
24 SROUT_in_3 : IN std_logic;
25 adc_data_array : IN adc_data_array_type;
26 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
27 board_id : IN std_logic_vector (3 DOWNTO 0);
28 crate_id : IN std_logic_vector (1 DOWNTO 0);
29 trigger : IN std_logic;
30 wiz_int : IN std_logic;
31 CLK25_OUT : OUT std_logic;
32 CLK25_PSOUT : OUT std_logic;
33 CLK50_OUT : OUT std_logic;
34 CLK_25_PS : OUT std_logic;
35 CLK_50 : OUT std_logic;
36 DCM_locked : OUT std_logic;
37 LOCKED_extraOUT : OUT std_logic;
38 PSCLK_OUT : OUT std_logic;
39 PSDONE_extraOUT : OUT std_logic;
40 PSINCDEC_OUT : OUT std_logic;
41 PS_DIR_IN : OUT std_logic;
42 RSRLOAD : OUT std_logic := '0';
43 SRCLK : OUT std_logic := '0';
44 SRIN_out : OUT std_logic := '0';
45 adc_clk_en : OUT std_logic := '0';
46 adc_oeb : OUT std_logic := '1';
47 additional_flasher_out : OUT std_logic;
48 amber : OUT std_logic;
49 dac_cs : OUT std_logic;
50 denable : OUT std_logic := '0'; -- default domino wave off
51 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
52 drs_dwrite : OUT std_logic := '1';
53 green : OUT std_logic;
54 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
55 mosi : OUT std_logic := '0';
56 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
57 ready : OUT std_logic := '0';
58 red : OUT std_logic;
59 sclk : OUT std_logic;
60 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
61 -- status:
62 shifting : OUT std_logic := '0';
63 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
64 wiz_cs : OUT std_logic := '1';
65 wiz_rd : OUT std_logic := '1';
66 wiz_reset : OUT std_logic := '1';
67 wiz_wr : OUT std_logic := '1';
68 sio : INOUT std_logic;
69 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
70 );
71
72-- Declarations
73
74END FAD_main ;
75
76--
77-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
78--
79-- Created:
80-- by - dneise.UNKNOWN (E5B-LABOR6)
81-- at - 16:46:19 26.01.2011
82--
83-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
84--
85library ieee;
86use ieee.std_logic_1164.all;
87use IEEE.STD_LOGIC_ARITH.all;
88use ieee.STD_LOGIC_UNSIGNED.all;
89
90library fact_fad_lib;
91use fact_fad_lib.fad_definitions.all;
92
93library UNISIM;
94--use UNISIM.VComponents.all;
95USE IEEE.NUMERIC_STD.all;
96USE IEEE.std_logic_signed.all;
97
98LIBRARY FACT_FAD_lib;
99
100ARCHITECTURE struct OF FAD_main IS
101
102 -- Architecture declarations
103
104 -- Internal signal declarations
105 SIGNAL CLK_25 : std_logic;
106 SIGNAL SRCLK1 : std_logic := '0';
107 SIGNAL adc_data_array_int : adc_data_array_type;
108 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
109 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
110 SIGNAL c_trigger_enable : std_logic := '0';
111 SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1'); --subject to changes
112 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);
113 SIGNAL config_busy : std_logic;
114 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);
115 SIGNAL config_data_valid : std_logic;
116 SIGNAL config_rd_en : std_logic;
117 SIGNAL config_ready : std_logic;
118 SIGNAL config_ready_cm : std_logic;
119 SIGNAL config_ready_spi : std_logic;
120 -- --
121 SIGNAL config_rw_ack : std_logic := '0';
122 -- --
123 SIGNAL config_rw_ready : std_logic := '0';
124 SIGNAL config_start : std_logic := '0';
125 SIGNAL config_start_cm : std_logic;
126 SIGNAL config_start_spi : std_logic := '0';
127 SIGNAL config_started : std_logic;
128 SIGNAL config_started_cu : std_logic := '0';
129 SIGNAL config_started_mm : std_logic;
130 SIGNAL config_started_spi : std_logic := '0';
131 SIGNAL config_wr_en : std_logic;
132 SIGNAL dac_array : dac_array_type;
133 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
134 SIGNAL dout : std_logic;
135 SIGNAL dout1 : std_logic;
136 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0');
137 SIGNAL drs_address_mode : std_logic;
138 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0');
139 SIGNAL drs_clk_en : std_logic := '0';
140 SIGNAL drs_read_s_cell : std_logic := '0';
141 SIGNAL drs_read_s_cell_ready : std_logic;
142 -- --
143-- drs_dwrite : out std_logic := '1';
144 SIGNAL drs_readout_ready : std_logic := '0';
145 SIGNAL drs_readout_ready_ack : std_logic;
146 SIGNAL drs_readout_started : std_logic;
147 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
148 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
149 SIGNAL dwrite : std_logic := '1';
150 SIGNAL dwrite_enable : std_logic := '1';
151 SIGNAL new_config : std_logic := '0';
152 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
153 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
154 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
155 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
156 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
157 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
158 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
159 SIGNAL ram_write_ea : std_logic;
160 SIGNAL ram_write_ready : std_logic := '0';
161 -- --
162 SIGNAL ram_write_ready_ack : std_logic := '0';
163 SIGNAL roi_array : roi_array_type;
164 SIGNAL roi_max : roi_max_type;
165 SIGNAL s_trigger : std_logic;
166 SIGNAL s_trigger_0 : std_logic;
167 SIGNAL sclk1 : std_logic;
168 SIGNAL sclk_enable : std_logic;
169 SIGNAL sensor_array : sensor_array_type;
170 SIGNAL sensor_ready : std_logic;
171 SIGNAL socks_connected : std_logic;
172 SIGNAL socks_waiting : std_logic;
173 SIGNAL srclk_enable : std_logic := '0';
174 SIGNAL srin_write_ack : std_logic := '0';
175 SIGNAL srin_write_ready : std_logic := '0';
176 SIGNAL start_srin_write_8b : std_logic;
177 SIGNAL trigger1 : std_logic;
178 SIGNAL trigger_enable : std_logic;
179 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);
180 SIGNAL trigger_out : std_logic;
181 SIGNAL wiz_ack : std_logic;
182 SIGNAL wiz_busy : std_logic;
183 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
184 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
185 SIGNAL wiz_write_ea : std_logic := '0';
186 SIGNAL wiz_write_end : std_logic := '0';
187 SIGNAL wiz_write_header : std_logic := '0';
188 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
189 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
190
191 -- Implicit buffer signal declarations
192 SIGNAL CLK_25_PS_internal : std_logic;
193 SIGNAL CLK_50_internal : std_logic;
194
195
196 -- Component Declarations
197 COMPONENT adc_buffer
198 PORT (
199 adc_data_array : IN adc_data_array_type;
200 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
201 clk_ps : IN std_logic;
202 adc_data_array_int : OUT adc_data_array_type;
203 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
204 );
205 END COMPONENT;
206 COMPONENT clock_generator_var_ps
207 PORT (
208 CLK : IN std_logic ;
209 RST_IN : IN std_logic ;
210 direction : IN std_logic ;
211 do_shift : IN std_logic ;
212 CLK_25 : OUT std_logic ;
213 CLK_25_PS : OUT std_logic ;
214 CLK_50 : OUT std_logic ;
215 DCM_locked : OUT std_logic ;
216 LOCKED_extraOUT : OUT std_logic ;
217 PSCLK_OUT : OUT std_logic ;
218 PSDONE_extraOUT : OUT std_logic ;
219 PSINCDEC_OUT : OUT std_logic ;
220 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
221 ready : OUT std_logic := '0';
222 -- status:
223 shifting : OUT std_logic := '0'
224 );
225 END COMPONENT;
226 COMPONENT continous_pulser
227 GENERIC (
228 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000
229 );
230 PORT (
231 CLK : IN std_logic;
232 enable : IN std_logic;
233 multiplier : IN std_logic_vector (7 DOWNTO 0);
234 trigger : OUT std_logic
235 );
236 END COMPONENT;
237 COMPONENT control_unit
238 PORT (
239 clk : IN STD_LOGIC ;
240 config_addr : IN std_logic_vector (7 DOWNTO 0);
241 config_rd_en : IN std_logic ;
242 config_start : IN std_logic ;
243 config_wr_en : IN std_logic ;
244 config_busy : OUT std_logic ;
245 config_data_valid : OUT std_logic ;
246 config_ready : OUT std_logic ;
247 -- --
248 config_rw_ack : OUT std_logic := '0';
249 -- --
250 config_rw_ready : OUT std_logic := '0';
251 config_started : OUT std_logic := '0';
252 dac_array : OUT dac_array_type ;
253 roi_array : OUT roi_array_type ;
254 config_data : INOUT std_logic_vector (15 DOWNTO 0)
255 );
256 END COMPONENT;
257 COMPONENT dataRAM_64b_16b_width14_5
258 PORT (
259 clka : IN std_logic ;
260 dina : IN std_logic_VECTOR (63 DOWNTO 0);
261 addra : IN std_logic_VECTOR (14 DOWNTO 0);
262 wea : IN std_logic_VECTOR (0 DOWNTO 0);
263 clkb : IN std_logic ;
264 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
265 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
266 );
267 END COMPONENT;
268 COMPONENT data_generator
269 GENERIC (
270 RAM_ADDR_WIDTH : integer := 12
271 );
272 PORT (
273 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
274 clk : IN std_logic ;
275 data_out : OUT std_logic_vector (63 DOWNTO 0);
276 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
277 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";
278 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
279 ram_write_ea : IN std_logic ;
280 ram_write_ready : OUT std_logic := '0';
281 -- --
282 ram_write_ready_ack : IN std_logic ;
283 -- --
284 config_start_mm : OUT std_logic := '0';
285 -- --
286 config_start_cm : OUT std_logic := '0';
287 -- --
288 config_start_spi : OUT std_logic := '0';
289 config_ready_mm : IN std_logic ;
290 config_ready_cm : IN std_logic ;
291 config_ready_spi : IN std_logic ;
292 config_started_mm : IN std_logic ;
293 config_started_cm : IN std_logic ;
294 config_started_spi : IN std_logic ;
295 roi_array : IN roi_array_type ;
296 roi_max : IN roi_max_type ;
297 sensor_array : IN sensor_array_type ;
298 sensor_ready : IN std_logic ;
299 dac_array : IN dac_array_type ;
300 package_length : IN std_logic_vector (15 DOWNTO 0);
301 board_id : IN std_logic_vector (3 DOWNTO 0);
302 crate_id : IN std_logic_vector (1 DOWNTO 0);
303 trigger_id : IN std_logic_vector (47 DOWNTO 0);
304 trigger : IN std_logic ;
305 -- s_trigger : in std_logic;
306 new_config : IN std_logic ;
307 config_started : OUT std_logic := '0';
308 adc_data_array : IN adc_data_array_type ;
309 adc_oeb : OUT std_logic := '1';
310 adc_clk_en : OUT std_logic := '0';
311 adc_otr : IN std_logic_vector (3 DOWNTO 0);
312 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
313 -- --
314 -- drs_dwrite : out std_logic := '1';
315 drs_readout_ready : OUT std_logic := '0';
316 drs_readout_ready_ack : IN std_logic ;
317 -- --
318 drs_clk_en : OUT std_logic := '0';
319 -- --
320 drs_read_s_cell : OUT std_logic := '0';
321 drs_srin_write_8b : OUT std_logic := '0';
322 drs_srin_write_ack : IN std_logic ;
323 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
324 drs_srin_write_ready : IN std_logic ;
325 drs_read_s_cell_ready : IN std_logic ;
326 drs_s_cell_array : IN drs_s_cell_array_type ;
327 drs_readout_started : OUT std_logic := '0'
328 );
329 END COMPONENT;
330 COMPONENT drs_pulser
331 PORT (
332 CLK : IN std_logic;
333 SROUT_in_0 : IN std_logic;
334 SROUT_in_1 : IN std_logic;
335 SROUT_in_2 : IN std_logic;
336 SROUT_in_3 : IN std_logic;
337 srin_data : IN std_logic_vector (7 DOWNTO 0);
338 start_endless_mode : IN std_logic;
339 start_read_stop_pos_mode : IN std_logic;
340 start_srin_write_8b : IN std_logic;
341 RSRLOAD : OUT std_logic := '0';
342 SRCLK : OUT std_logic := '0';
343 SRIN_out : OUT std_logic := '0';
344 srin_write_ack : OUT std_logic := '0';
345 srin_write_ready : OUT std_logic := '0';
346 stop_pos : OUT drs_s_cell_array_type;
347 stop_pos_valid : OUT std_logic := '0'
348 );
349 END COMPONENT;
350 COMPONENT led_controller
351 GENERIC (
352 HEARTBEAT_PWM_DIVIDER : integer := 500;
353 MAX_DELAY : integer := 100; --not used anymore at all :-(
354 WAITING_DIVIDER : integer := 500000000
355 );
356 PORT (
357 CLK : IN std_logic;
358 socks_connected : IN std_logic;
359 socks_waiting : IN std_logic;
360 trigger : IN std_logic;
361 additional_flasher_out : OUT std_logic;
362 amber : OUT std_logic;
363 green : OUT std_logic;
364 red : OUT std_logic
365 );
366 END COMPONENT;
367 COMPONENT memory_manager
368 GENERIC (
369 RAM_ADDR_WIDTH_64B : integer := 12;
370 RAM_ADDR_WIDTH_16B : integer := 14
371 );
372 PORT (
373 clk : IN std_logic ;
374 config_start : IN std_logic ;
375 ram_write_ready : IN std_logic ;
376 -- --
377 ram_write_ready_ack : OUT std_logic := '0';
378 -- --
379 roi_array : IN roi_array_type ;
380 ram_write_ea : OUT std_logic := '0';
381 config_ready : OUT std_logic := '0';
382 config_started : OUT std_logic := '0';
383 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
384 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
385 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
386 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
387 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
388 wiz_write_ea : OUT std_logic := '0';
389 wiz_write_header : OUT std_logic := '0';
390 wiz_write_end : OUT std_logic := '0';
391 wiz_busy : IN std_logic ;
392 wiz_ack : IN std_logic ;
393 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
394 );
395 END COMPONENT;
396 COMPONENT spi_interface
397 PORT (
398 clk_50MHz : IN std_logic ;
399 config_start : IN std_logic ;
400 dac_array : IN dac_array_type ;
401 config_ready : OUT std_logic ;
402 config_started : OUT std_logic := '0';
403 dac_cs : OUT std_logic ;
404 mosi : OUT std_logic := '0';
405 sclk : OUT std_logic ;
406 sensor_array : OUT sensor_array_type ;
407 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
408 sensor_ready : OUT std_logic ;
409 miso : INOUT std_logic
410 );
411 END COMPONENT;
412 COMPONENT trigger_counter
413 PORT (
414 trigger_id : OUT std_logic_vector (47 DOWNTO 0);
415 trigger : IN std_logic ;
416 clk : IN std_logic
417 );
418 END COMPONENT;
419 COMPONENT trigger_manager
420 PORT (
421 clk : IN std_logic;
422 drs_readout_ready : IN std_logic;
423 trigger_in : IN std_logic;
424 drs_readout_ready_ack : OUT std_logic := '0';
425 drs_write : OUT std_logic := '1';
426 trigger_out : OUT std_logic := '0'
427 );
428 END COMPONENT;
429 COMPONENT w5300_modul
430 GENERIC (
431 RAM_ADDR_WIDTH : integer := 14
432 );
433 PORT (
434 clk : IN std_logic ;
435 wiz_reset : OUT std_logic := '1';
436 addr : OUT std_logic_vector (9 DOWNTO 0);
437 data : INOUT std_logic_vector (15 DOWNTO 0);
438 cs : OUT std_logic := '1';
439 wr : OUT std_logic := '1';
440 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
441 rd : OUT std_logic := '1';
442 int : IN std_logic ;
443 write_length : IN std_logic_vector (16 DOWNTO 0);
444 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
445 ram_data : IN std_logic_vector (15 DOWNTO 0);
446 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
447 data_valid : IN std_logic ;
448 data_valid_ack : OUT std_logic := '0';
449 busy : OUT std_logic := '1';
450 write_header_flag : IN std_logic ;
451 write_end_flag : IN std_logic ;
452 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
453 -- softtrigger:
454 s_trigger : OUT std_logic := '0';
455 c_trigger_enable : OUT std_logic := '0';
456 c_trigger_mult : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject TO changes
457 --
458 new_config : OUT std_logic := '0';
459 config_started : IN std_logic ;
460 config_addr : OUT std_logic_vector (7 DOWNTO 0);
461 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
462 config_wr_en : OUT std_logic := '0';
463 config_rd_en : OUT std_logic := '0';
464 -- --
465 config_rw_ack : IN std_logic ;
466 -- --
467 config_rw_ready : IN std_logic ;
468 -- --
469 config_busy : IN std_logic ;
470 denable : OUT std_logic := '0'; -- default domino wave off
471 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.
472 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
473 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
474 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
475 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
476 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.
477 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted
478 socks_waiting : OUT std_logic ;
479 socks_connected : OUT std_logic
480 );
481 END COMPONENT;
482
483 -- Optional embedded configurations
484 -- pragma synthesis_off
485 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
486 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
487 FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser;
488 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
489 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
490 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
491 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
492 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
493 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
494 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
495 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
496 FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager;
497 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
498 -- pragma synthesis_on
499
500
501BEGIN
502
503 -- ModuleWare code(v1.9) for instance 'I5' of 'and'
504 drs_dwrite <= dwrite AND dwrite_enable;
505
506 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
507 SRCLK <= SRCLK1 AND srclk_enable;
508
509 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
510 sclk <= sclk_enable AND sclk1;
511
512 -- ModuleWare code(v1.9) for instance 'U_11' of 'and'
513 dout1 <= dout AND trigger_enable;
514
515 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
516 PS_DIR_IN <= ps_direction;
517
518 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
519 CLK50_OUT <= CLK_50_internal;
520
521 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
522 CLK25_OUT <= CLK_25;
523
524 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
525 CLK25_PSOUT <= CLK_25_PS_internal;
526
527 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
528 u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
529 drs_address_mode)
530 BEGIN
531 CASE drs_address_mode IS
532 WHEN '0' => drs_channel_id <= drs_channel_internal;
533 WHEN '1' => drs_channel_id <= drs_address;
534 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
535 END CASE;
536 END PROCESS u_0combo_proc;
537
538 -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
539 dout <= s_trigger OR trigger;
540
541 -- ModuleWare code(v1.9) for instance 'U_13' of 'or'
542 s_trigger <= s_trigger_0 OR trigger1;
543
544 -- Instance port mappings.
545 I_main_adc_buffer : adc_buffer
546 PORT MAP (
547 clk_ps => CLK_25_PS_internal,
548 adc_data_array => adc_data_array,
549 adc_otr_array => adc_otr_array,
550 adc_data_array_int => adc_data_array_int,
551 adc_otr => adc_otr
552 );
553 U_2 : clock_generator_var_ps
554 PORT MAP (
555 CLK => CLK,
556 RST_IN => ps_reset,
557 direction => ps_direction,
558 do_shift => ps_do_phase_shift,
559 CLK_25 => CLK_25,
560 CLK_25_PS => CLK_25_PS_internal,
561 CLK_50 => CLK_50_internal,
562 DCM_locked => DCM_locked,
563 LOCKED_extraOUT => LOCKED_extraOUT,
564 PSCLK_OUT => PSCLK_OUT,
565 PSDONE_extraOUT => PSDONE_extraOUT,
566 PSINCDEC_OUT => PSINCDEC_OUT,
567 offset => offset,
568 ready => ready,
569 shifting => shifting
570 );
571 U_3 : continous_pulser
572 GENERIC MAP (
573 MINIMAL_TRIGGER_WAIT_TIME => 250000
574 )
575 PORT MAP (
576 CLK => CLK_25,
577 enable => c_trigger_enable,
578 multiplier => c_trigger_mult,
579 trigger => trigger1
580 );
581 I_main_control_unit : control_unit
582 PORT MAP (
583 clk => CLK_50_internal,
584 config_addr => config_addr,
585 config_rd_en => config_rd_en,
586 config_start => config_start_cm,
587 config_wr_en => config_wr_en,
588 config_busy => config_busy,
589 config_data_valid => config_data_valid,
590 config_ready => config_ready_cm,
591 config_rw_ack => config_rw_ack,
592 config_rw_ready => config_rw_ready,
593 config_started => config_started_cu,
594 dac_array => dac_array,
595 roi_array => roi_array,
596 config_data => config_data
597 );
598 U_4 : dataRAM_64b_16b_width14_5
599 PORT MAP (
600 clka => CLK_25,
601 dina => data_out,
602 addra => addr_out,
603 wea => write_ea,
604 clkb => CLK_50_internal,
605 addrb => ram_addr,
606 doutb => ram_data
607 );
608 I_main_data_generator : data_generator
609 GENERIC MAP (
610 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
611 )
612 PORT MAP (
613 clk => CLK_25,
614 data_out => data_out,
615 addr_out => addr_out,
616 write_ea => write_ea,
617 ram_start_addr => ram_start_addr,
618 ram_write_ea => ram_write_ea,
619 ram_write_ready => ram_write_ready,
620 ram_write_ready_ack => ram_write_ready_ack,
621 config_start_mm => config_start,
622 config_start_cm => config_start_cm,
623 config_start_spi => config_start_spi,
624 config_ready_mm => config_ready,
625 config_ready_cm => config_ready_cm,
626 config_ready_spi => config_ready_spi,
627 config_started_mm => config_started_mm,
628 config_started_cm => config_started_cu,
629 config_started_spi => config_started_spi,
630 roi_array => roi_array,
631 roi_max => roi_max,
632 sensor_array => sensor_array,
633 sensor_ready => sensor_ready,
634 dac_array => dac_array,
635 package_length => package_length,
636 board_id => board_id,
637 crate_id => crate_id,
638 trigger_id => trigger_id,
639 trigger => trigger_out,
640 new_config => new_config,
641 config_started => config_started,
642 adc_data_array => adc_data_array_int,
643 adc_oeb => adc_oeb,
644 adc_clk_en => adc_clk_en,
645 adc_otr => adc_otr,
646 drs_channel_id => drs_channel_internal,
647 drs_readout_ready => drs_readout_ready,
648 drs_readout_ready_ack => drs_readout_ready_ack,
649 drs_clk_en => drs_clk_en,
650 drs_read_s_cell => drs_read_s_cell,
651 drs_srin_write_8b => start_srin_write_8b,
652 drs_srin_write_ack => srin_write_ack,
653 drs_srin_data => drs_srin_data,
654 drs_srin_write_ready => srin_write_ready,
655 drs_read_s_cell_ready => drs_read_s_cell_ready,
656 drs_s_cell_array => drs_s_cell_array,
657 drs_readout_started => drs_readout_started
658 );
659 I_main_drs_pulser : drs_pulser
660 PORT MAP (
661 CLK => CLK_25,
662 start_endless_mode => drs_clk_en,
663 start_read_stop_pos_mode => drs_read_s_cell,
664 SROUT_in_0 => SROUT_in_0,
665 SROUT_in_1 => SROUT_in_1,
666 SROUT_in_2 => SROUT_in_2,
667 SROUT_in_3 => SROUT_in_3,
668 stop_pos => drs_s_cell_array,
669 stop_pos_valid => drs_read_s_cell_ready,
670 start_srin_write_8b => start_srin_write_8b,
671 srin_write_ready => srin_write_ready,
672 srin_write_ack => srin_write_ack,
673 srin_data => drs_srin_data,
674 SRIN_out => SRIN_out,
675 RSRLOAD => RSRLOAD,
676 SRCLK => SRCLK1
677 );
678 U_10 : led_controller
679 GENERIC MAP (
680 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz
681 MAX_DELAY => 100,
682 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz
683 )
684 PORT MAP (
685 CLK => CLK_50_internal,
686 green => green,
687 amber => amber,
688 red => red,
689 additional_flasher_out => additional_flasher_out,
690 trigger => drs_readout_started,
691 socks_waiting => socks_waiting,
692 socks_connected => socks_connected
693 );
694 I_main_memory_manager : memory_manager
695 GENERIC MAP (
696 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
697 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
698 )
699 PORT MAP (
700 clk => CLK_25,
701 config_start => config_start,
702 ram_write_ready => ram_write_ready,
703 ram_write_ready_ack => ram_write_ready_ack,
704 roi_array => roi_array,
705 ram_write_ea => ram_write_ea,
706 config_ready => config_ready,
707 config_started => config_started_mm,
708 roi_max => roi_max,
709 package_length => package_length,
710 wiz_ram_start_addr => wiz_ram_start_addr,
711 wiz_write_length => wiz_write_length,
712 wiz_number_of_channels => wiz_number_of_channels,
713 wiz_write_ea => wiz_write_ea,
714 wiz_write_header => wiz_write_header,
715 wiz_write_end => wiz_write_end,
716 wiz_busy => wiz_busy,
717 wiz_ack => wiz_ack,
718 ram_start_addr => ram_start_addr
719 );
720 I_main_SPI_interface : spi_interface
721 PORT MAP (
722 clk_50MHz => CLK_50_internal,
723 config_start => config_start_spi,
724 dac_array => dac_array,
725 config_ready => config_ready_spi,
726 config_started => config_started_spi,
727 dac_cs => dac_cs,
728 mosi => mosi,
729 sclk => sclk1,
730 sensor_array => sensor_array,
731 sensor_cs => sensor_cs,
732 sensor_ready => sensor_ready,
733 miso => sio
734 );
735 I_main_ext_trigger : trigger_counter
736 PORT MAP (
737 trigger_id => trigger_id,
738 trigger => trigger_out,
739 clk => CLK_25_PS_internal
740 );
741 U_12 : trigger_manager
742 PORT MAP (
743 clk => CLK_25,
744 trigger_in => dout1,
745 trigger_out => trigger_out,
746 drs_write => dwrite,
747 drs_readout_ready => drs_readout_ready,
748 drs_readout_ready_ack => drs_readout_ready_ack
749 );
750 I_main_ethernet : w5300_modul
751 GENERIC MAP (
752 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
753 )
754 PORT MAP (
755 clk => CLK_50_internal,
756 wiz_reset => wiz_reset,
757 addr => wiz_addr,
758 data => wiz_data,
759 cs => wiz_cs,
760 wr => wiz_wr,
761 led => led,
762 rd => wiz_rd,
763 int => wiz_int,
764 write_length => wiz_write_length,
765 ram_start_addr => wiz_ram_start_addr,
766 ram_data => ram_data,
767 ram_addr => ram_addr,
768 data_valid => wiz_write_ea,
769 data_valid_ack => wiz_ack,
770 busy => wiz_busy,
771 write_header_flag => wiz_write_header,
772 write_end_flag => wiz_write_end,
773 fifo_channels => wiz_number_of_channels,
774 s_trigger => s_trigger_0,
775 c_trigger_enable => c_trigger_enable,
776 c_trigger_mult => c_trigger_mult,
777 new_config => new_config,
778 config_started => config_started,
779 config_addr => config_addr,
780 config_data => config_data,
781 config_wr_en => config_wr_en,
782 config_rd_en => config_rd_en,
783 config_rw_ack => config_rw_ack,
784 config_rw_ready => config_rw_ready,
785 config_busy => config_busy,
786 denable => denable,
787 dwrite_enable => dwrite_enable,
788 sclk_enable => sclk_enable,
789 ps_direction => ps_direction,
790 ps_do_phase_shift => ps_do_phase_shift,
791 ps_reset => ps_reset,
792 srclk_enable => srclk_enable,
793 trigger_enable => trigger_enable,
794 socks_waiting => socks_waiting,
795 socks_connected => socks_connected
796 );
797
798 -- Implicit buffered output assignments
799 CLK_25_PS <= CLK_25_PS_internal;
800 CLK_50 <= CLK_50_internal;
801
802END struct;
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