source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 10503

Last change on this file since 10503 was 10503, checked in by neise, 10 years ago
File size: 46.8 KB
Line 
1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 11:13:34 02.05.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 D_T_in : IN std_logic_vector (1 DOWNTO 0);
22 FTM_RS485_rx_d : IN std_logic;
23 SROUT_in_0 : IN std_logic;
24 SROUT_in_1 : IN std_logic;
25 SROUT_in_2 : IN std_logic;
26 SROUT_in_3 : IN std_logic;
27 adc_data_array : IN adc_data_array_type;
28 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
29 board_id : IN std_logic_vector (3 DOWNTO 0);
30 crate_id : IN std_logic_vector (1 DOWNTO 0);
31 drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
32 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked
33 trigger : IN std_logic;
34 wiz_int : IN std_logic;
35 ADC_CLK : OUT std_logic;
36 CLK_25_PS : OUT std_logic;
37 CLK_50 : OUT std_logic;
38 FTM_RS485_rx_en : OUT std_logic;
39 FTM_RS485_tx_d : OUT std_logic;
40 FTM_RS485_tx_en : OUT std_logic;
41 RSRLOAD : OUT std_logic := '0';
42 SRCLK : OUT std_logic := '0';
43 SRIN_out : OUT std_logic := '0';
44 adc_oeb : OUT std_logic := '1';
45 alarm_refclk_too_high : OUT std_logic;
46 alarm_refclk_too_low : OUT std_logic;
47 amber : OUT std_logic;
48 counter_result : OUT std_logic_vector (11 DOWNTO 0);
49 dac_cs : OUT std_logic;
50 denable : OUT std_logic := '0'; -- default domino wave off
51 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
52 drs_dwrite : OUT std_logic := '1';
53 green : OUT std_logic;
54 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
55 mosi : OUT std_logic := '0';
56 red : OUT std_logic;
57 sclk : OUT std_logic;
58 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
59 trigger_veto : OUT std_logic := '1';
60 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
61 wiz_cs : OUT std_logic := '1';
62 wiz_rd : OUT std_logic := '1';
63 wiz_reset : OUT std_logic := '1';
64 wiz_wr : OUT std_logic := '1';
65 sio : INOUT std_logic;
66 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
67 );
68
69-- Declarations
70
71END FAD_main ;
72
73--
74-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
75--
76-- Created:
77-- by - daqct3.UNKNOWN (IHP110)
78-- at - 11:13:34 02.05.2011
79--
80-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
81--
82library ieee;
83use ieee.std_logic_1164.all;
84use IEEE.STD_LOGIC_ARITH.all;
85use ieee.STD_LOGIC_UNSIGNED.all;
86
87library fact_fad_lib;
88use fact_fad_lib.fad_definitions.all;
89
90library UNISIM;
91--use UNISIM.VComponents.all;
92USE IEEE.NUMERIC_STD.all;
93USE IEEE.std_logic_signed.all;
94USE fact_fad_lib.fad_rs485_constants.all;
95
96LIBRARY FACT_FAD_lib;
97
98ARCHITECTURE struct OF FAD_main IS
99
100 -- Architecture declarations
101
102 -- Internal signal declarations
103 SIGNAL CLK_25 : std_logic;
104 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
105 SIGNAL DCM_locked_status : std_logic;
106 SIGNAL DCM_ready_status : std_logic;
107 --
108
109-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ...
110-- during EVT header wrinting, this field is left out ... and only written into event header,
111-- when the DRS chip were read out already.
112 SIGNAL FTM_RS485_ready : std_logic;
113 SIGNAL I_really_want_dwrite : STD_LOGIC;
114 SIGNAL SRCLK1 : std_logic := '0';
115 SIGNAL adc_clk_en : std_logic;
116 SIGNAL adc_data_array_int : adc_data_array_type;
117 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
118 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
119 SIGNAL c_trigger_enable : std_logic := '0';
120 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0);
121 SIGNAL cont_trigger : std_logic;
122 SIGNAL current_dac_array : dac_array_type := ( others => 0);
123 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd
124 SIGNAL data_generator_config_start : std_logic := '0';
125 SIGNAL data_generator_config_valid : std_logic;
126 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
127 SIGNAL data_ram_empty : std_logic;
128 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off
129 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off
130 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off
131 SIGNAL din1 : std_logic := '0'; -- default domino wave off
132 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0');
133 SIGNAL dout : STD_LOGIC;
134 SIGNAL dout0 : STD_LOGIC;
135 SIGNAL dout1 : STD_LOGIC;
136 SIGNAL dout2 : STD_LOGIC;
137 SIGNAL dout3 : STD_LOGIC;
138 SIGNAL dout4 : STD_LOGIC;
139 SIGNAL drs_clk_en : std_logic := '0';
140 SIGNAL drs_read_s_cell : std_logic := '0';
141 SIGNAL drs_read_s_cell_ready : std_logic;
142 -- --
143-- drs_dwrite : out std_logic := '1';
144 SIGNAL drs_readout_ready : std_logic := '0';
145 SIGNAL drs_readout_ready_ack : std_logic;
146 SIGNAL drs_readout_started : std_logic;
147 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
148 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
149 SIGNAL dwrite_enable_w5300 : std_logic := '1';
150 SIGNAL dwrite_global_enable : std_logic := '1';
151 SIGNAL dwrite_trigger_manager : std_logic := '1';
152 SIGNAL enable_i : std_logic;
153 SIGNAL enabled_trigger_or_s_trigger : std_logic;
154 SIGNAL memory_manager_config_start : std_logic := '0';
155 SIGNAL memory_manager_config_valid : std_logic;
156 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
157 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
158 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
159 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
160 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
161 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
162 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
163 SIGNAL ram_write_ea : std_logic;
164 SIGNAL ram_write_ready : std_logic := '0';
165 -- --
166 SIGNAL ram_write_ready_ack : std_logic := '0';
167 SIGNAL ready : STD_LOGIC := '0';
168 SIGNAL rec_timeout_occured : std_logic := '0';
169 SIGNAL reset_synch_i : std_logic;
170 SIGNAL reset_trigger_id : std_logic := '0';
171 SIGNAL roi_max : roi_max_type;
172 SIGNAL roi_setting : roi_array_type;
173 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte
174 SIGNAL runnumber : std_logic_vector(31 DOWNTO 0) := conv_std_logic_vector(0 ,31);
175 SIGNAL s_trigger : std_logic;
176 SIGNAL s_trigger_or_cont_trigger : std_logic;
177 SIGNAL sclk_enable : std_logic;
178 SIGNAL sensor_array : sensor_array_type;
179 SIGNAL sensor_ready : std_logic;
180 SIGNAL socks_connected : std_logic;
181 SIGNAL socks_waiting : std_logic;
182 SIGNAL spi_interface_config_start : std_logic := '0';
183 SIGNAL spi_interface_config_valid : std_logic;
184 SIGNAL srclk_enable : std_logic := '0';
185 SIGNAL srin_write_ack : std_logic := '0';
186 SIGNAL srin_write_ready : std_logic := '0';
187 SIGNAL start_srin_write_8b : std_logic;
188 SIGNAL time : std_logic_vector(31 DOWNTO 0);
189 SIGNAL trigger_enable : std_logic;
190 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0);
191 SIGNAL trigger_or_s_trigger : std_logic;
192 SIGNAL trigger_out : std_logic;
193 SIGNAL wiz_ack : std_logic;
194 SIGNAL wiz_busy : std_logic;
195 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
196 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
197 SIGNAL wiz_write_ea : std_logic := '0';
198 SIGNAL wiz_write_end : std_logic := '0';
199 SIGNAL wiz_write_header : std_logic := '0';
200 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
201 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
202
203 -- Implicit buffer signal declarations
204 SIGNAL CLK_25_PS_internal : std_logic;
205 SIGNAL CLK_50_internal : std_logic;
206 SIGNAL alarm_refclk_too_high_internal : std_logic;
207 SIGNAL alarm_refclk_too_low_internal : std_logic;
208 SIGNAL counter_result_internal : std_logic_vector (11 DOWNTO 0);
209
210
211 -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'split'
212 SIGNAL mw_U_0temp_din : std_logic_vector(3 DOWNTO 0);
213
214 -- Component Declarations
215 COMPONENT FAD_rs485_receiver
216 GENERIC (
217 -- defined in fad_rs485_definitions.fad_rs485_constants
218 RX_BYTES : integer := RS485_MESSAGE_LEN_BYTES; -- no. of bytes to receive
219 RX_WIDTH : integer := RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive
220 );
221 PORT (
222 rec_clk : IN std_logic;
223 rec_start : IN std_logic;
224 rx_d : IN std_logic;
225 rec_dout : OUT std_logic_vector (RX_WIDTH - 1 DOWNTO 0) := (others => '0');
226 rec_timeout_occured : OUT std_logic := '0';
227 rec_valid : OUT std_logic := '0';
228 rx_en : OUT std_logic;
229 tx_d : OUT std_logic;
230 tx_en : OUT std_logic
231 );
232 END COMPONENT;
233 COMPONENT REFCLK_counter
234 PORT (
235 clk : IN std_logic;
236 refclk_in : IN std_logic;
237 alarm_refclk_too_high : OUT std_logic := '0';
238 alarm_refclk_too_low : OUT std_logic := '0';
239 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0')
240 );
241 END COMPONENT;
242 COMPONENT adc_buffer
243 PORT (
244 adc_data_array : IN adc_data_array_type;
245 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
246 clk_ps : IN std_logic;
247 adc_data_array_int : OUT adc_data_array_type;
248 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
249 );
250 END COMPONENT;
251 COMPONENT clock_generator_var_ps
252 PORT (
253 CLK : IN std_logic ;
254 RST_IN : IN std_logic ;
255 direction : IN std_logic ;
256 do_shift : IN std_logic ;
257 CLK_25 : OUT std_logic ;
258 CLK_25_PS : OUT std_logic ;
259 CLK_50 : OUT std_logic ;
260 locked_status_o : OUT std_logic ;
261 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
262 ready_status_o : OUT std_logic
263 );
264 END COMPONENT;
265 COMPONENT continous_pulser
266 GENERIC (
267 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000;
268 TRIGGER_WIDTH : integer := 5
269 );
270 PORT (
271 CLK : IN std_logic;
272 enable : IN std_logic;
273 multiplier : IN std_logic_vector (15 DOWNTO 0);
274 trigger : OUT std_logic
275 );
276 END COMPONENT;
277 COMPONENT dataRAM_64b_16b_width14_5
278 PORT (
279 clka : IN std_logic ;
280 dina : IN std_logic_VECTOR (63 DOWNTO 0);
281 addra : IN std_logic_VECTOR (14 DOWNTO 0);
282 wea : IN std_logic_VECTOR (0 DOWNTO 0);
283 clkb : IN std_logic ;
284 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
285 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
286 );
287 END COMPONENT;
288 COMPONENT data_generator
289 GENERIC (
290 RAM_ADDR_WIDTH : integer := 12
291 );
292 PORT (
293 clk : IN std_logic ; -- CLK_25.
294 data_out : OUT std_logic_vector (63 DOWNTO 0);
295 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
296 dataRAM_write_ea_o : OUT std_logic_vector (0 DOWNTO 0) := "0";
297 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
298 ram_write_ea : IN std_logic ;
299 ram_write_ready : OUT std_logic := '0';
300 ram_write_ready_ack : IN std_logic ;
301 roi_array : IN roi_array_type ;
302 roi_max : IN roi_max_type ;
303 sensor_array : IN sensor_array_type ;
304 sensor_ready : IN std_logic ;
305 dac_array : IN dac_array_type ;
306 config_start : IN std_logic ;
307 config_done : OUT std_logic := '0';
308 -- EVT HEADER - part 1
309 package_length : IN std_logic_vector (15 DOWNTO 0);
310 pll_lock : IN std_logic_vector ( 3 DOWNTO 0);
311 dwrite_enable_in : IN std_logic ;
312 denable_enable_in : IN std_logic ;
313 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ...
314 -- during EVT header wrinting, this field is left out ... and only written into event header,
315 -- when the DRS chip were read out already.
316 FTM_RS485_ready : IN std_logic ;
317 FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte
318 FTM_receiver_status : IN std_logic ;
319 -- EVT HEADER - part 3
320 fad_event_counter : IN std_logic_vector (31 DOWNTO 0);
321 refclk_counter : IN std_logic_vector (11 DOWNTO 0);
322 refclk_too_high : IN std_logic ;
323 refclk_too_low : IN std_logic ;
324 -- EVT HEADER - part 4
325 board_id : IN std_logic_vector (3 DOWNTO 0);
326 crate_id : IN std_logic_vector (1 DOWNTO 0);
327 DCM_PS_status : IN std_logic_vector (7 DOWNTO 0);
328 DCM_locked_status : IN std_logic ;
329 DCM_ready_status : IN std_logic ;
330 SPI_SCLK_enable_status : IN std_logic ;
331 TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0);
332 -- EVT HEADER - part 5
333 dna : IN std_logic_vector (63 DOWNTO 0);
334 -- EVT HEADER - part 6
335 runnumber : IN std_logic_vector (31 DOWNTO 0);
336 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us
337 trigger : IN std_logic ;
338 adc_data_array : IN adc_data_array_type ;
339 adc_output_enable_inverted : OUT std_logic := '1';
340 adc_clk_en : OUT std_logic := '0';
341 adc_otr : IN std_logic_vector (3 DOWNTO 0);
342 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
343 --drs_dwrite : out std_logic := '1';
344 drs_readout_ready : OUT std_logic := '0';
345 drs_readout_ready_ack : IN std_logic ;
346 drs_clk_en : OUT std_logic := '0';
347 start_read_drs_stop_cell : OUT std_logic := '0';
348 drs_srin_write_8b : OUT std_logic := '0';
349 drs_srin_write_ack : IN std_logic ;
350 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
351 drs_srin_write_ready : IN std_logic ;
352 drs_read_s_cell_ready : IN std_logic ;
353 drs_s_cell_array : IN drs_s_cell_array_type ;
354 drs_readout_started : OUT std_logic := '0';
355 trigger_veto : OUT std_logic := '1'
356 );
357 END COMPONENT;
358 COMPONENT dna_gen
359 PORT (
360 clk : IN STD_LOGIC ;
361 dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0');
362 ready : OUT STD_LOGIC := '0'
363 );
364 END COMPONENT;
365 COMPONENT drs_pulser
366 PORT (
367 CLK : IN std_logic;
368 SROUT_in_0 : IN std_logic;
369 SROUT_in_1 : IN std_logic;
370 SROUT_in_2 : IN std_logic;
371 SROUT_in_3 : IN std_logic;
372 srin_data : IN std_logic_vector (7 DOWNTO 0);
373 start_endless_mode : IN std_logic;
374 start_read_stop_pos_mode : IN std_logic;
375 start_srin_write_8b : IN std_logic;
376 RSRLOAD : OUT std_logic := '0';
377 SRCLK : OUT std_logic := '0';
378 SRIN_out : OUT std_logic := '0';
379 srin_write_ack : OUT std_logic := '0';
380 srin_write_ready : OUT std_logic := '0';
381 stop_pos : OUT drs_s_cell_array_type;
382 stop_pos_valid : OUT std_logic := '0'
383 );
384 END COMPONENT;
385 COMPONENT led_controller
386 GENERIC (
387 HEARTBEAT_PWM_DIVIDER : integer := 500;
388 WAITING_DIVIDER : integer := 500000000
389 );
390 PORT (
391 CLK : IN std_logic;
392 refclk_too_high : IN std_logic;
393 refclk_too_low : IN std_logic;
394 socks_connected : IN std_logic;
395 socks_waiting : IN std_logic;
396 trigger : IN std_logic;
397 additional_flasher_out : OUT std_logic;
398 amber : OUT std_logic;
399 green : OUT std_logic;
400 red : OUT std_logic
401 );
402 END COMPONENT;
403 COMPONENT memory_manager
404 GENERIC (
405 RAM_ADDR_WIDTH_64B : integer := 12;
406 RAM_ADDR_WIDTH_16B : integer := 14
407 );
408 PORT (
409 clk : IN std_logic ;
410 config_start : IN std_logic ;
411 ram_write_ready : IN std_logic ;
412 -- --
413 ram_write_ready_ack : OUT std_logic := '0';
414 -- --
415 roi_array : IN roi_array_type ;
416 ram_write_ea : OUT std_logic := '0';
417 config_ready : OUT std_logic := '1';
418 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
419 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
420 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
421 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
422 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
423 wiz_write_ea : OUT std_logic := '0';
424 wiz_write_header : OUT std_logic := '0';
425 wiz_write_end : OUT std_logic := '0';
426 wiz_busy : IN std_logic ;
427 wiz_ack : IN std_logic ;
428 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0');
429 data_ram_empty : OUT std_logic
430 );
431 END COMPONENT;
432 COMPONENT spi_interface
433 PORT (
434 clk_50MHz : IN std_logic ;
435 config_start : IN std_logic ;
436 dac_array : IN dac_array_type ;
437 sclk_enable_i : IN std_logic ;
438 config_ready : OUT std_logic ;
439 current_dac_array : OUT dac_array_type := ( others => 0);
440 dac_cs : OUT std_logic ;
441 mosi : OUT std_logic := '0';
442 sclk : OUT std_logic ;
443 sensor_array : OUT sensor_array_type ;
444 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
445 sensor_ready : OUT std_logic ;
446 miso : INOUT std_logic
447 );
448 END COMPONENT;
449 COMPONENT timer
450 GENERIC (
451 TIMER_WIDTH : integer := 32;
452 PRESCALER : integer := 5000
453 );
454 PORT (
455 clk : IN std_logic;
456 enable_i : IN std_logic;
457 reset_synch_i : IN std_logic;
458 synch_i : IN std_logic;
459 synched_o : OUT std_logic := '0';
460 time_o : OUT std_logic_vector ( TIMER_WIDTH-1 DOWNTO 0)
461 );
462 END COMPONENT;
463 COMPONENT trigger_counter
464 PORT (
465 trigger_id : OUT std_logic_vector (31 DOWNTO 0);
466 trigger : IN std_logic ;
467 reset : IN std_logic ;
468 clk : IN std_logic
469 );
470 END COMPONENT;
471 COMPONENT trigger_manager
472 PORT (
473 clk : IN std_logic;
474 drs_readout_ready : IN std_logic;
475 trigger_in : IN std_logic;
476 drs_readout_ready_ack : OUT std_logic := '0';
477 drs_write : OUT std_logic := '1';
478 trigger_out : OUT std_logic := '0'
479 );
480 END COMPONENT;
481 COMPONENT w5300_modul
482 GENERIC (
483 RAM_ADDR_WIDTH : integer := 14
484 );
485 PORT (
486 clk : IN std_logic ;
487 wiz_reset : OUT std_logic := '1';
488 addr : OUT std_logic_vector (9 DOWNTO 0);
489 data : INOUT std_logic_vector (15 DOWNTO 0);
490 cs : OUT std_logic := '1';
491 wr : OUT std_logic := '1';
492 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
493 rd : OUT std_logic := '1';
494 int : IN std_logic ;
495 write_length : IN std_logic_vector (16 DOWNTO 0);
496 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
497 ram_data : IN std_logic_vector (15 DOWNTO 0);
498 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
499 data_valid : IN std_logic ;
500 data_valid_ack : OUT std_logic := '0';
501 busy : OUT std_logic := '1';
502 write_header_flag : IN std_logic ;
503 write_end_flag : IN std_logic ;
504 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
505 -- softtrigger:
506 s_trigger : OUT std_logic := '0';
507 c_trigger_enable : OUT std_logic := '0';
508 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject TO changes
509 -- FAD configuration signals:
510 ------------------------------------------------------------------------------
511 memory_manager_config_start_o : OUT std_logic := '0';
512 memory_manager_config_valid_i : IN std_logic ;
513 spi_interface_config_start_o : OUT std_logic := '0';
514 spi_interface_config_valid_i : IN std_logic ;
515 data_generator_config_start_o : OUT std_logic := '0';
516 data_generator_config_valid_i : IN std_logic ;
517 dac_setting : OUT dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd
518 roi_setting : OUT roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd
519 runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,31);
520 reset_trigger_id : OUT std_logic := '0';
521 data_ram_empty : IN std_logic ;
522 ------------------------------------------------------------------------------
523
524 -- MAC/IP calculation signals:
525 ------------------------------------------------------------------------------
526 MAC_jumper : IN std_logic_vector (1 DOWNTO 0);
527 BoardID : IN std_logic_vector (3 DOWNTO 0);
528 CrateID : IN std_logic_vector (1 DOWNTO 0);
529 ------------------------------------------------------------------------------
530
531 -- user controllable enable signals
532 ------------------------------------------------------------------------------
533 trigger_enable : OUT std_logic ;
534 denable : OUT std_logic := '0'; -- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override.
535 dwrite_enable : OUT std_logic := '1'; -- default DWRITE low.
536 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
537 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.
538 ------------------------------------------------------------------------------
539
540 -- ADC CLK generator, is able to shift phase with respect to X_50M
541 -- these signals control the behavior of the digital clock manager (DCM)
542 ------------------------------------------------------------------------------
543 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
544 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
545 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
546 ps_ready : IN std_logic ;
547 ------------------------------------------------------------------------------
548
549 -- signals used to control FAD LED bahavior:
550 -- one of the three LEDs is used for com-status info
551 ------------------------------------------------------------------------------
552 socks_waiting : OUT std_logic ;
553 socks_connected : OUT std_logic
554 ------------------------------------------------------------------------------
555 );
556 END COMPONENT;
557
558 -- Optional embedded configurations
559 -- pragma synthesis_off
560 FOR ALL : FAD_rs485_receiver USE ENTITY FACT_FAD_lib.FAD_rs485_receiver;
561 FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
562 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
563 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
564 FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser;
565 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
566 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
567 FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen;
568 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
569 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
570 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
571 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
572 FOR ALL : timer USE ENTITY FACT_FAD_lib.timer;
573 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
574 FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager;
575 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
576 -- pragma synthesis_on
577
578
579BEGIN
580
581 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
582 SRCLK <= SRCLK1 AND srclk_enable;
583
584 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
585 dout <= dout0 AND dout1 AND dout2 AND dout3;
586
587 -- ModuleWare code(v1.9) for instance 'U_4' of 'and'
588 dwrite_global_enable <= dwrite_enable_w5300 AND dout4;
589
590 -- ModuleWare code(v1.9) for instance 'and_1' of 'and'
591 ADC_CLK <= adc_clk_en AND CLK_25_PS_internal;
592
593 -- ModuleWare code(v1.9) for instance 'and_2' of 'and'
594 denable_sig <= denable_prim AND din1;
595
596 -- ModuleWare code(v1.9) for instance 'and_4' of 'and'
597 enabled_trigger_or_s_trigger <= trigger_or_s_trigger
598 AND trigger_enable;
599
600 -- ModuleWare code(v1.9) for instance 'and_5' of 'and'
601 drs_dwrite <= dwrite_trigger_manager AND dwrite_global_enable;
602
603 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
604 denable <= denable_sig;
605
606 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd'
607 reset_synch_i <= '0';
608
609 -- ModuleWare code(v1.9) for instance 'inverter_1' of 'inv'
610 din1 <= NOT(denable_inhibit);
611
612 -- ModuleWare code(v1.9) for instance 'U_2' of 'or'
613 dout4 <= dout OR I_really_want_dwrite;
614
615 -- ModuleWare code(v1.9) for instance 'or_1' of 'or'
616 s_trigger_or_cont_trigger <= s_trigger OR cont_trigger;
617
618 -- ModuleWare code(v1.9) for instance 'or_2' of 'or'
619 denable_inhibit <= alarm_refclk_too_low_internal
620 OR alarm_refclk_too_high_internal;
621
622 -- ModuleWare code(v1.9) for instance 'or_5' of 'or'
623 trigger_or_s_trigger <= s_trigger_or_cont_trigger OR trigger;
624
625 -- ModuleWare code(v1.9) for instance 'U_0' of 'split'
626 mw_U_0temp_din <= plllock_in;
627 u_0combo_proc: PROCESS (mw_U_0temp_din)
628 VARIABLE temp_din: std_logic_vector(3 DOWNTO 0);
629 BEGIN
630 temp_din := mw_U_0temp_din(3 DOWNTO 0);
631 dout0 <= temp_din(0);
632 dout1 <= temp_din(1);
633 dout2 <= temp_din(2);
634 dout3 <= temp_din(3);
635 END PROCESS u_0combo_proc;
636
637 -- ModuleWare code(v1.9) for instance 'U_3' of 'vdd'
638 I_really_want_dwrite <= '1';
639
640 -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd'
641 enable_i <= '1';
642
643 -- Instance port mappings.
644 U_7 : FAD_rs485_receiver
645 GENERIC MAP (
646 RX_BYTES => RS485_MESSAGE_LEN_BYTES, -- no. of bytes to receive
647 RX_WIDTH => RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive
648 )
649 PORT MAP (
650 rec_clk => CLK_50_internal,
651 rx_d => FTM_RS485_rx_d,
652 rx_en => FTM_RS485_rx_en,
653 tx_d => FTM_RS485_tx_d,
654 tx_en => FTM_RS485_tx_en,
655 rec_start => drs_readout_started,
656 rec_timeout_occured => rec_timeout_occured,
657 rec_dout => rs465_data,
658 rec_valid => FTM_RS485_ready
659 );
660 REFCLK_counter_main : REFCLK_counter
661 PORT MAP (
662 clk => CLK_50_internal,
663 refclk_in => drs_refclk_in,
664 counter_result => counter_result_internal,
665 alarm_refclk_too_high => alarm_refclk_too_high_internal,
666 alarm_refclk_too_low => alarm_refclk_too_low_internal
667 );
668 I_main_adc_buffer : adc_buffer
669 PORT MAP (
670 clk_ps => CLK_25_PS_internal,
671 adc_data_array => adc_data_array,
672 adc_otr_array => adc_otr_array,
673 adc_data_array_int => adc_data_array_int,
674 adc_otr => adc_otr
675 );
676 clock_generator_instance : clock_generator_var_ps
677 PORT MAP (
678 CLK => CLK,
679 RST_IN => ps_reset,
680 direction => ps_direction,
681 do_shift => ps_do_phase_shift,
682 CLK_25 => CLK_25,
683 CLK_25_PS => CLK_25_PS_internal,
684 CLK_50 => CLK_50_internal,
685 locked_status_o => DCM_locked_status,
686 offset => DCM_PS_status,
687 ready_status_o => DCM_ready_status
688 );
689 continous_pulser_instance : continous_pulser
690 GENERIC MAP (
691 MINIMAL_TRIGGER_WAIT_TIME => 250000,
692 TRIGGER_WIDTH => 5
693 )
694 PORT MAP (
695 CLK => CLK_25,
696 enable => c_trigger_enable,
697 multiplier => c_trigger_mult,
698 trigger => cont_trigger
699 );
700 dataRAM_instance : dataRAM_64b_16b_width14_5
701 PORT MAP (
702 clka => CLK_25,
703 dina => data_out,
704 addra => addr_out,
705 wea => write_ea,
706 clkb => CLK_50_internal,
707 addrb => ram_addr,
708 doutb => ram_data
709 );
710 I_main_data_generator : data_generator
711 GENERIC MAP (
712 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
713 )
714 PORT MAP (
715 clk => CLK_25,
716 data_out => data_out,
717 addr_out => addr_out,
718 dataRAM_write_ea_o => write_ea,
719 ram_start_addr => ram_start_addr,
720 ram_write_ea => ram_write_ea,
721 ram_write_ready => ram_write_ready,
722 ram_write_ready_ack => ram_write_ready_ack,
723 roi_array => roi_setting,
724 roi_max => roi_max,
725 sensor_array => sensor_array,
726 sensor_ready => sensor_ready,
727 dac_array => current_dac_array,
728 config_start => data_generator_config_start,
729 config_done => data_generator_config_valid,
730 package_length => package_length,
731 pll_lock => plllock_in,
732 dwrite_enable_in => dwrite_enable_w5300,
733 denable_enable_in => denable_sig,
734 FTM_RS485_ready => FTM_RS485_ready,
735 FTM_trigger_info => rs465_data,
736 FTM_receiver_status => rec_timeout_occured,
737 fad_event_counter => trigger_id,
738 refclk_counter => counter_result_internal,
739 refclk_too_high => alarm_refclk_too_high_internal,
740 refclk_too_low => alarm_refclk_too_low_internal,
741 board_id => board_id,
742 crate_id => crate_id,
743 DCM_PS_status => DCM_PS_status,
744 DCM_locked_status => DCM_locked_status,
745 DCM_ready_status => DCM_ready_status,
746 SPI_SCLK_enable_status => sclk_enable,
747 TRG_GEN_div => c_trigger_mult,
748 dna => dna,
749 runnumber => runnumber,
750 timer_value => time,
751 trigger => trigger_out,
752 adc_data_array => adc_data_array_int,
753 adc_output_enable_inverted => adc_oeb,
754 adc_clk_en => adc_clk_en,
755 adc_otr => adc_otr,
756 drs_channel_id => drs_channel_id,
757 drs_readout_ready => drs_readout_ready,
758 drs_readout_ready_ack => drs_readout_ready_ack,
759 drs_clk_en => drs_clk_en,
760 start_read_drs_stop_cell => drs_read_s_cell,
761 drs_srin_write_8b => start_srin_write_8b,
762 drs_srin_write_ack => srin_write_ack,
763 drs_srin_data => drs_srin_data,
764 drs_srin_write_ready => srin_write_ready,
765 drs_read_s_cell_ready => drs_read_s_cell_ready,
766 drs_s_cell_array => drs_s_cell_array,
767 drs_readout_started => drs_readout_started,
768 trigger_veto => trigger_veto
769 );
770 dna_gen_instance : dna_gen
771 PORT MAP (
772 clk => CLK_25,
773 dna => dna,
774 ready => ready
775 );
776 I_main_drs_pulser : drs_pulser
777 PORT MAP (
778 CLK => CLK_25,
779 start_endless_mode => drs_clk_en,
780 start_read_stop_pos_mode => drs_read_s_cell,
781 SROUT_in_0 => SROUT_in_0,
782 SROUT_in_1 => SROUT_in_1,
783 SROUT_in_2 => SROUT_in_2,
784 SROUT_in_3 => SROUT_in_3,
785 stop_pos => drs_s_cell_array,
786 stop_pos_valid => drs_read_s_cell_ready,
787 start_srin_write_8b => start_srin_write_8b,
788 srin_write_ready => srin_write_ready,
789 srin_write_ack => srin_write_ack,
790 srin_data => drs_srin_data,
791 SRIN_out => SRIN_out,
792 RSRLOAD => RSRLOAD,
793 SRCLK => SRCLK1
794 );
795 led_controller_instance : led_controller
796 GENERIC MAP (
797 HEARTBEAT_PWM_DIVIDER => 50000,
798 WAITING_DIVIDER => 50000000
799 )
800 PORT MAP (
801 CLK => CLK_50_internal,
802 green => green,
803 amber => amber,
804 red => red,
805 additional_flasher_out => OPEN,
806 trigger => drs_readout_started,
807 refclk_too_high => alarm_refclk_too_high_internal,
808 refclk_too_low => alarm_refclk_too_low_internal,
809 socks_waiting => socks_waiting,
810 socks_connected => socks_connected
811 );
812 I_main_memory_manager : memory_manager
813 GENERIC MAP (
814 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
815 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
816 )
817 PORT MAP (
818 clk => CLK_25,
819 config_start => memory_manager_config_start,
820 ram_write_ready => ram_write_ready,
821 ram_write_ready_ack => ram_write_ready_ack,
822 roi_array => roi_setting,
823 ram_write_ea => ram_write_ea,
824 config_ready => memory_manager_config_valid,
825 roi_max => roi_max,
826 package_length => package_length,
827 wiz_ram_start_addr => wiz_ram_start_addr,
828 wiz_write_length => wiz_write_length,
829 wiz_number_of_channels => wiz_number_of_channels,
830 wiz_write_ea => wiz_write_ea,
831 wiz_write_header => wiz_write_header,
832 wiz_write_end => wiz_write_end,
833 wiz_busy => wiz_busy,
834 wiz_ack => wiz_ack,
835 ram_start_addr => ram_start_addr,
836 data_ram_empty => data_ram_empty
837 );
838 I_main_SPI_interface : spi_interface
839 PORT MAP (
840 clk_50MHz => CLK_50_internal,
841 config_start => spi_interface_config_start,
842 dac_array => dac_setting,
843 sclk_enable_i => sclk_enable,
844 config_ready => spi_interface_config_valid,
845 current_dac_array => current_dac_array,
846 dac_cs => dac_cs,
847 mosi => mosi,
848 sclk => sclk,
849 sensor_array => sensor_array,
850 sensor_cs => sensor_cs,
851 sensor_ready => sensor_ready,
852 miso => sio
853 );
854 timer_instance : timer
855 GENERIC MAP (
856 TIMER_WIDTH => 32,
857 PRESCALER => 5000
858 )
859 PORT MAP (
860 clk => CLK_50_internal,
861 time_o => time,
862 synch_i => trigger_out,
863 synched_o => OPEN,
864 reset_synch_i => reset_synch_i,
865 enable_i => enable_i
866 );
867 trigger_counter_instance : trigger_counter
868 PORT MAP (
869 trigger_id => trigger_id,
870 trigger => trigger_out,
871 reset => reset_trigger_id,
872 clk => CLK_25_PS_internal
873 );
874 trigger_manager_instance : trigger_manager
875 PORT MAP (
876 clk => CLK_25,
877 trigger_in => enabled_trigger_or_s_trigger,
878 trigger_out => trigger_out,
879 drs_write => dwrite_trigger_manager,
880 drs_readout_ready => drs_readout_ready,
881 drs_readout_ready_ack => drs_readout_ready_ack
882 );
883 w5300_modul_instance : w5300_modul
884 GENERIC MAP (
885 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
886 )
887 PORT MAP (
888 clk => CLK_50_internal,
889 wiz_reset => wiz_reset,
890 addr => wiz_addr,
891 data => wiz_data,
892 cs => wiz_cs,
893 wr => wiz_wr,
894 led => led,
895 rd => wiz_rd,
896 int => wiz_int,
897 write_length => wiz_write_length,
898 ram_start_addr => wiz_ram_start_addr,
899 ram_data => ram_data,
900 ram_addr => ram_addr,
901 data_valid => wiz_write_ea,
902 data_valid_ack => wiz_ack,
903 busy => wiz_busy,
904 write_header_flag => wiz_write_header,
905 write_end_flag => wiz_write_end,
906 fifo_channels => wiz_number_of_channels,
907 s_trigger => s_trigger,
908 c_trigger_enable => c_trigger_enable,
909 c_trigger_mult => c_trigger_mult,
910 memory_manager_config_start_o => memory_manager_config_start,
911 memory_manager_config_valid_i => memory_manager_config_valid,
912 spi_interface_config_start_o => spi_interface_config_start,
913 spi_interface_config_valid_i => spi_interface_config_valid,
914 data_generator_config_start_o => data_generator_config_start,
915 data_generator_config_valid_i => data_generator_config_valid,
916 dac_setting => dac_setting,
917 roi_setting => roi_setting,
918 runnumber => runnumber,
919 reset_trigger_id => reset_trigger_id,
920 data_ram_empty => data_ram_empty,
921 MAC_jumper => D_T_in,
922 BoardID => board_id,
923 CrateID => crate_id,
924 trigger_enable => trigger_enable,
925 denable => denable_prim,
926 dwrite_enable => dwrite_enable_w5300,
927 sclk_enable => sclk_enable,
928 srclk_enable => srclk_enable,
929 ps_direction => ps_direction,
930 ps_do_phase_shift => ps_do_phase_shift,
931 ps_reset => ps_reset,
932 ps_ready => DCM_ready_status,
933 socks_waiting => socks_waiting,
934 socks_connected => socks_connected
935 );
936
937 -- Implicit buffered output assignments
938 CLK_25_PS <= CLK_25_PS_internal;
939 CLK_50 <= CLK_50_internal;
940 alarm_refclk_too_high <= alarm_refclk_too_high_internal;
941 alarm_refclk_too_low <= alarm_refclk_too_low_internal;
942 counter_result <= counter_result_internal;
943
944END struct;
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