1  


2   VHDL Architecture FACT_FAD_lib.led_controller.bahavior


3  


4   Created:


5   by  dneise.UNKNOWN (E5BLABOR6)


6   at  11:04:17 04.01.2011


7  


8   using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)


9  


10  LIBRARY ieee;


11  USE ieee.std_logic_1164.all;


12  USE ieee.std_logic_arith.all;


13  use ieee.STD_LOGIC_UNSIGNED.all;


14 


15  library FACT_FAD_lib;


16 


17 


18  use FACT_FAD_lib.fad_definitions.all;


19 


20 


21  ENTITY led_controller IS


22  GENERIC(


23  HEARTBEAT_PWM_DIVIDER : integer := 500;


24  MAX_DELAY : integer := 100; not used anymore at all :(


25  WAITING_DIVIDER : integer := 500000000


26  );


27  PORT(


28  CLK : IN std_logic;


29 


30   LED outs  inverted logic


31  green : OUT std_logic;


32  amber : OUT std_logic;


33  red : OUT std_logic;


34  additional_flasher_out : OUT std_logic;


35 


36 


37   status INs


38  trigger : IN std_logic;  when trigger is received green should toggle


39 


40  socks_waiting : IN std_logic;


41  socks_connected: IN std_logic


42 


43  heartbeat_en : IN std_logic


44  );


45  END ENTITY led_controller;


46 


47  


48  ARCHITECTURE bahavior OF led_controller IS


49 


50  type states is ( INIT, WAITING, CONNECTED);


51  signal state,next_state : states := INIT;


52 


53   noninverted logic


54  signal green_loc : std_logic := '1';  on in order to show power


55  signal amber_loc : std_logic := '0'; default off


56  signal red_loc : std_logic := '0'; default off


57  signal flasher : std_logic;


58 


59  BEGIN


60   since leds have inverted logic, the outs are inverted at this point.


61  green <= not green_loc;


62  amber <= not amber_loc;


63  red <= not red_loc;


64  additional_flasher_out <= flasher;


65 


66   MAIN FSM: go to next state if rising edge


67  FSM_Registers: process(CLK)


68  begin


69  if Rising_edge(CLK) then


70  state <= next_state;


71  end if;


72  end process;


73 


74   MAIN FSM


75  FSM_logic: process(state, socks_connected, socks_waiting)


76  begin


77  next_state <= state;


78  case state is


79 


80 


81  when INIT =>


82  amber_loc <= '0';


83  if (socks_waiting = '1') then


84  next_state <= WAITING;


85  else


86  next_state <= INIT;


87  end if;


88 


89  when WAITING =>


90  amber_loc <= flasher;


91  if (socks_connected = '1') then


92  next_state <= CONNECTED;


93  else


94  next_state <= WAITING;


95  end if;


96 


97  when CONNECTED =>


98  amber_loc <= '1';


99  if (socks_connected = '0') then


100  next_state <= INIT;


101  else


102  next_state <= CONNECTED;


103  end if;


104  end case;


105  end process FSM_logic;


106 


107 


108   if trigger is received green_loc toggles


109  trigger_proc : process (trigger)


110  begin


111  if Rising_edge(trigger) then


112  green_loc <= not green_loc;


113  end if;


114  end process trigger_proc;


115 


116   heartbeat process:


117   as long as nothing else is to be done for the red led


118   it will show a ~2Hz heartbeat


119   can be switched off with heartbeat_en high


120  heartbeat : process (CLK)


121  variable Z: integer range 0 to HEARTBEAT_PWM_DIVIDER  1 := 0;


122  variable ON_TIME: integer range 0 to HEARTBEAT_PWM_DIVIDER  1 := 0;


123  variable DELAY: integer range 0 to MAX_DELAY  1 := 0;


124  variable DIR : std_logic := '1';


125 


126  begin


127  if rising_edge(CLK) then


128  if (Z < HEARTBEAT_PWM_DIVIDER  1) then


129  Z := Z + 1;


130  else


131  Z := 0;


132  if (DELAY < MAX_DELAY  1) then


133  DELAY := DELAY + 1;


134  else


135  DELAY := 0;


136  end if;


137  end if;


138 


139 


140  if (Z = 0) then


141  if (DIR = '0') then  count up


142  if (ON_TIME < HEARTBEAT_PWM_DIVIDER  11) then


143  ON_TIME := ON_TIME + 10;


144  else


145  DIR := '1';


146  end if;


147  else  DIR is '1'  count down


148  if (ON_TIME > 10) then


149  ON_TIME := ON_TIME  10;


150  else


151  DIR := '0';


152  end if;


153  end if;


154  end if;


155 


156  if (Z = 0) then


157  red_loc <= '1';


158  end if;


159  if (Z = ON_TIME) then


160  red_loc <= '0';


161  end if;


162  end if;


163  end process heartbeat;


164 


165 


166   sock_waiting_flasher process:


167  sock_waiting_flasher : process (CLK)


168  variable Y: integer range 0 to WAITING_DIVIDER  1;


169  begin


170  if rising_edge(CLK) then


171  if (Y < WAITING_DIVIDER  1) then


172  Y := Y + 1;


173  else


174  Y := 0;


175  end if;


176  if (Y = 0) then


177  flasher <= '1';


178  end if;


179  if (Y = WAITING_DIVIDER / 2) then


180  flasher <= '0';


181  end if;


182  end if;


183  end process sock_waiting_flasher;


184 


185 


186  END ARCHITECTURE bahavior;


187 

