source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak @ 9912

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1--
2-- VHDL Architecture FACT_FAD_lib.memory_manager.beha
3--
4-- Created:
5--          by - kai.UNKNOWN (E5PCXX)
6--          at - 14:33:25 02.03.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9--
10library ieee;
11use ieee.std_logic_1164.all;
12use IEEE.STD_LOGIC_ARITH.all;
13use ieee.STD_LOGIC_UNSIGNED.all;
14
15library FACT_FAD_lib;
16use FACT_FAD_lib.fad_definitions.all;
17
18-- library UNISIM;
19-- use UNISIM.VComponents.all;
20-- USE IEEE.NUMERIC_STD.all;
21
22-- RAM_ADDR_WIDTH_64B is used for
23-- output ram_start_addr
24
25-- RAM_ADDR_WIDTH_16B is used for
26-- output wiz_ram_start_addr
27
28
29ENTITY memory_manager IS
30  generic(
31     RAM_ADDR_WIDTH_64B : integer := 12;
32     RAM_ADDR_WIDTH_16B : integer := 14
33   );
34   PORT(
35      clk : IN std_logic;
36      config_start : IN std_logic;
37      ram_write_ready : IN std_logic;
38      roi_array : IN roi_array_type;
39      ram_write_ea : OUT std_logic := '0';
40      config_ready, config_started : OUT std_logic := '0';
41      roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
42      package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
43      wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0');
44      wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
45      wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
46      wiz_write_ea : OUT std_logic := '0';
47      wiz_write_header : OUT std_logic := '0';
48      wiz_write_end : OUT std_logic := '0';
49      wiz_busy : IN std_logic;
50      ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
51   );
52
53-- Declarations
54
55END memory_manager ;
56
57--
58ARCHITECTURE beha OF memory_manager IS
59
60type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1);
61signal state_mm : state_mm_type := MM_CONFIG;
62
63--type roi_array_type is array (0 to 35) of integer range 0 to 1024;
64type roi_max_array_type is array (0 to 8) of integer range 0 to 1024;
65type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
66type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
67type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9;
68type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B;
69
70signal roi_max_array : roi_max_array_type := (others => 0);
71
72-- size of channel groups (16 bit)
73signal channel_size : channel_size_type := (others => 0);
74-- write length of packages (16 bit)
75signal fifo_write_length : fifo_write_length_type := (others => 0);
76-- number of channels per package
77signal fifo_channels_array : fifo_channels_array_type := (others => 0);
78-- size of packages in ram (16 bit)
79signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0);
80--
81signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0;
82signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0;
83signal event_size : integer range 0 to RAM_SIZE_16B := 0;
84
85signal drs_id : integer range 0 to 4 := 0;
86signal channel_id : integer range 0 to 9 := 0;
87signal channel_index : integer range 0 to 9 := 0;
88signal package_index : integer range 0 to 9 := 0;
89signal number_of_packages : integer range 0 to 9 := 0;
90signal max_events_ram, events_in_ram : integer range 0 to 2048;
91signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1);
92signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1);
93signal event_ready_flag : std_logic := '0';
94
95signal roi_index : integer range 0 to 45 := 0;
96signal temp_roi : integer range 0 to 1024 := 0;
97
98BEGIN
99 
100  mm : process (clk)
101  begin
102    if rising_edge (clk) then
103      case state_mm is
104   
105        when MM_CONFIG =>
106          if (config_start = '1') then
107            config_started <= '1';
108            roi_max_array <= (others => 0);
109            channel_size <= (others => 0);
110            fifo_write_length <= (others => 0);
111            fifo_channels_array <= (others => 0);
112            event_size <= 0;
113            ram_write_ea <= '0';
114            state_mm <= MAX_ROI;
115          end if;
116       
117        -- calculate max ROIs and channel sizes
118        when MAX_ROI =>
119          roi_index <= (drs_id * 9) + channel_id;
120          state_mm <= MAX_ROI1;
121        when MAX_ROI1 =>
122          temp_roi <= roi_array (roi_index);
123          state_mm <= MAX_ROI2;
124        when MAX_ROI2 =>
125          if (channel_id < 9) then
126            if ( temp_roi > roi_max_array (channel_id)) then
127              roi_max_array (channel_id) <= temp_roi;
128            end if;
129            channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;
130            drs_id <= drs_id + 1;
131            state_mm <= MAX_ROI;
132            if (drs_id = 3) then
133              drs_id <= 0;
134              channel_id <= channel_id + 1;
135            end if;
136          else
137            drs_id <= 0;
138            channel_id <= 0;
139            channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH;
140            channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH;
141            state_mm <= FIFO_CALC;
142          end if;
143       
144        -- calculate number of channels that fit in FIFO
145        when FIFO_CALC =>
146          if (channel_id < 9) then
147            if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then
148              fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id);
149              fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1;
150              channel_id <= channel_id + 1;
151              event_size <= event_size + channel_size (channel_id);
152            else
153              package_index <= package_index + 1;
154            end if;
155          else
156            number_of_packages <= package_index + 1;
157            package_index <= 0;
158            channel_index <= 0;
159            channel_id <= 0;
160            fifo_package_size_ram <= (others => 0);
161            fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6;
162            event_size_ram <= 0;
163            event_size_ram_64b <= 0;
164            max_events_ram <= 0;           
165            state_mm <= RAM_CALC;
166          end if;
167         
168        when RAM_CALC =>
169          if (package_index < number_of_packages) then
170            if (channel_index < fifo_channels_array (package_index)) then
171              fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4);
172              channel_index <= channel_index + 1;
173              channel_id <= channel_id + 1;
174            else
175              package_index <= package_index + 1;
176              event_size_ram <= event_size_ram + fifo_package_size_ram (package_index);
177              channel_index <= 0;
178            end if;
179          else
180            fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4;
181            event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare               
182            state_mm <= RAM_CALC1;
183          end if;
184        when RAM_CALC1 =>
185          max_events_ram <= max_events_ram + 1;
186          if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then
187            state_mm <= RAM_CALC1;
188          else
189            max_events_ram <= max_events_ram - 1;
190            state_mm <= RAM_CALC2;
191          end if;
192        when RAM_CALC2 =>
193          event_size_ram_64b <= (event_size_ram / 4);
194          events_in_ram <= 0;
195          event_start_addr <= 0;
196          write_start_addr <= 0;
197          package_index <= 0;
198          channel_id <= 0;
199          ram_start_addr <= (others => '0');
200          ram_write_ea <= '1';
201          config_started <= '0';
202          config_ready <= '1';
203          package_length <= conv_std_logic_vector (event_size, 16);
204          for i in 0 to 8 loop
205            roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11);
206          end loop;
207          state_mm <= MM_MAIN;
208         
209        when MM_MAIN =>
210          state_mm <= MM_MAIN1;
211          if ((ram_write_ready = '1') and (event_ready_flag = '0')) then
212            ram_write_ea <= '0';
213            events_in_ram <= events_in_ram + 1;
214            if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then
215              event_start_addr <= event_start_addr + event_size_ram_64b;
216            else
217              event_start_addr <= 0;
218            end if;
219            event_ready_flag <= '1';
220          end if;
221          wiz_write_ea <= '0'; -- ?????
222   
223        when MM_MAIN1 =>
224          state_mm <= MM_MAIN;
225          if (config_start = '1') then
226            config_ready <= '0';
227            if (events_in_ram = 0) then
228              state_mm <= MM_CONFIG;
229            end if;
230          end if;
231          if (event_ready_flag = '1') then
232            if (events_in_ram < max_events_ram) then
233              ram_write_ea <= '1';
234              -- ram_start_addr <= conv_std_logic_vector(event_start_addr, 12);
235              ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B);
236              event_ready_flag <= '0';
237            end if;
238          end if;
239          if ((events_in_ram > 0) and (wiz_busy = '0')) then
240            if (package_index < number_of_packages) then
241              -- wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, 14);
242              wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B);
243              wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17);
244              wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4);
245              wiz_write_ea <= '1';
246              package_index <= package_index + 1;
247              if (package_index = 0) then
248                -- first package -> write header
249                wiz_write_header <= '1';
250              else
251                wiz_write_header <= '0';
252              end if;
253              if (package_index = (number_of_packages - 1)) then
254                -- last package -> write end-flag
255                wiz_write_end <= '1';
256                -- next address
257                if ((write_start_addr + event_size_ram + fifo_package_size_ram (package_index) )  < (RAM_SIZE_16B - event_size_ram)) then
258                  --write_start_addr <= write_start_addr + event_size_ram;
259                  write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
260                else
261                  write_start_addr <= 0;
262                end if;
263              else
264                write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
265                wiz_write_end <= '0';
266              end if;
267            else
268              events_in_ram <= events_in_ram - 1;
269              package_index <= 0;
270            end if;
271        end if;
272       
273         
274      end case; -- state_mm
275    end if;
276  end process mm;
277 
278   
279 
280END ARCHITECTURE beha;
281
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