source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd@ 10155

Last change on this file since 10155 was 10155, checked in by neise, 11 years ago
highly unstable version !!!
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1--
2-- VHDL Architecture FACT_FAD_lib.memory_manager.beha
3--
4-- Created:
5-- by - kai.UNKNOWN (E5PCXX)
6-- at - 14:33:25 02.03.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9--
10library ieee;
11use ieee.std_logic_1164.all;
12use IEEE.STD_LOGIC_ARITH.all;
13use ieee.STD_LOGIC_UNSIGNED.all;
14
15library FACT_FAD_lib;
16use FACT_FAD_lib.fad_definitions.all;
17
18-- library UNISIM;
19-- use UNISIM.VComponents.all;
20-- USE IEEE.NUMERIC_STD.all;
21
22-- RAM_ADDR_WIDTH_64B is used for
23-- output ram_start_addr
24
25-- RAM_ADDR_WIDTH_16B is used for
26-- output wiz_ram_start_addr
27
28
29ENTITY memory_manager IS
30 generic(
31 RAM_ADDR_WIDTH_64B : integer := 12;
32 RAM_ADDR_WIDTH_16B : integer := 14
33 );
34 PORT(
35 clk : IN std_logic;
36 config_start : IN std_logic;
37 ram_write_ready : IN std_logic;
38 -- --
39 ram_write_ready_ack : OUT std_logic := '0';
40 -- --
41 roi_array : IN roi_array_type;
42 ram_write_ea : OUT std_logic := '0';
43 config_ready, config_started : OUT std_logic := '0';
44 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
45 package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
46 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0');
47 wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
48 wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
49 wiz_write_ea : OUT std_logic := '0';
50 wiz_write_header : OUT std_logic := '0';
51 wiz_write_end : OUT std_logic := '0';
52 wiz_busy : IN std_logic;
53 wiz_ack : IN std_logic;
54 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
55 );
56
57-- Declarations
58
59END memory_manager ;
60
61--
62ARCHITECTURE beha OF memory_manager IS
63
64type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1, MM_MAIN2, MM_MAIN3, MM_MAIN4);
65signal state_mm : state_mm_type := MM_CONFIG;
66
67--type roi_array_type is array (0 to 35) of integer range 0 to 1024;
68type roi_max_array_type is array (0 to 8) of integer range 0 to 1024;
69type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
70type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
71type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9;
72type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B;
73
74signal roi_max_array : roi_max_array_type := (others => 0);
75
76-- size of channel groups (16 bit)
77signal channel_size : channel_size_type := (others => 0);
78-- write length of packages (16 bit)
79signal fifo_write_length : fifo_write_length_type := (others => 0);
80-- number of channels per package
81signal fifo_channels_array : fifo_channels_array_type := (others => 0);
82-- size of packages in ram (16 bit)
83signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0);
84--
85signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0;
86signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0;
87signal event_size : integer range 0 to RAM_SIZE_16B := 0;
88
89signal drs_id : integer range 0 to 4 := 0;
90signal channel_id : integer range 0 to 9 := 0;
91signal channel_index : integer range 0 to 9 := 0;
92signal package_index : integer range 0 to 9 := 0;
93signal number_of_packages : integer range 0 to 9 := 0;
94signal max_events_ram, events_in_ram : integer range 0 to 2048;
95signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1);
96signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1);
97signal event_ready_flag : std_logic := '0';
98signal wiz_ack_flag, wiz_write_ea_flag: std_logic := '0';
99
100signal roi_index : integer range 0 to 45 := 0;
101signal temp_roi : integer range 0 to 1024 := 0;
102
103BEGIN
104
105-- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy;
106
107 mm : process (clk)
108 begin
109 if rising_edge (clk) then
110 case state_mm is
111
112 when MM_CONFIG =>
113 if (config_start = '1') then
114 config_started <= '1';
115 roi_max_array <= (others => 0);
116 channel_size <= (others => 0);
117 fifo_write_length <= (others => 0);
118 fifo_channels_array <= (others => 0);
119 event_size <= 0;
120 ram_write_ea <= '0';
121 state_mm <= MAX_ROI;
122 end if;
123
124 -- calculate max ROIs and channel sizes
125 when MAX_ROI =>
126 roi_index <= (drs_id * 9) + channel_id;
127 state_mm <= MAX_ROI1;
128 when MAX_ROI1 =>
129 temp_roi <= roi_array (roi_index);
130 state_mm <= MAX_ROI2;
131 when MAX_ROI2 =>
132 if (channel_id < 9) then
133 if ( temp_roi > roi_max_array (channel_id)) then
134 roi_max_array (channel_id) <= temp_roi;
135 end if;
136 channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE;
137 drs_id <= drs_id + 1;
138 state_mm <= MAX_ROI;
139 if (drs_id = 3) then
140 drs_id <= 0;
141 channel_id <= channel_id + 1;
142 end if;
143 else
144 drs_id <= 0;
145 channel_id <= 0;
146 channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH;
147 channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH;
148 state_mm <= FIFO_CALC;
149 end if;
150
151 -- calculate number of channels that fit in FIFO
152 when FIFO_CALC =>
153 if (channel_id < 9) then
154 if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then
155 fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id);
156 fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1;
157 channel_id <= channel_id + 1;
158 event_size <= event_size + channel_size (channel_id);
159 else
160 package_index <= package_index + 1;
161 end if;
162 else
163 number_of_packages <= package_index + 1;
164 package_index <= 0;
165 channel_index <= 0;
166 channel_id <= 0;
167 fifo_package_size_ram <= (others => 0);
168 fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6;
169 event_size_ram <= 0;
170 event_size_ram_64b <= 0;
171 max_events_ram <= 0;
172 state_mm <= RAM_CALC;
173 end if;
174
175 when RAM_CALC =>
176 if (package_index < number_of_packages) then
177 if (channel_index < fifo_channels_array (package_index)) then
178 fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4);
179 channel_index <= channel_index + 1;
180 channel_id <= channel_id + 1;
181 else
182 package_index <= package_index + 1;
183 event_size_ram <= event_size_ram + fifo_package_size_ram (package_index);
184 channel_index <= 0;
185 end if;
186 else
187 fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4;
188 event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare
189 state_mm <= RAM_CALC1;
190 end if;
191 when RAM_CALC1 =>
192 max_events_ram <= max_events_ram + 1;
193 if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then
194 state_mm <= RAM_CALC1;
195 else
196 max_events_ram <= max_events_ram - 1;
197 state_mm <= RAM_CALC2;
198 end if;
199 when RAM_CALC2 =>
200 event_size_ram_64b <= (event_size_ram / 4);
201 events_in_ram <= 0;
202 event_start_addr <= 0;
203 write_start_addr <= 0;
204 package_index <= 0;
205 channel_id <= 0;
206 ram_start_addr <= (others => '0');
207 ram_write_ea <= '1';
208 config_started <= '0';
209 config_ready <= '1';
210 package_length <= conv_std_logic_vector (event_size, 16);
211 for i in 0 to 8 loop
212 roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11);
213 end loop;
214
215 event_ready_flag <= '0';
216 wiz_ack_flag <= '0';
217 wiz_write_ea_flag <= '0';
218 state_mm <= MM_MAIN;
219
220 when MM_MAIN =>
221 state_mm <= MM_MAIN1;
222 if (config_start = '1') then
223 config_ready <= '0';
224 if (events_in_ram = 0) then
225 state_mm <= MM_CONFIG;
226 end if;
227 end if;
228
229 when MM_MAIN1 =>
230 state_mm <= MM_MAIN2;
231 if ((ram_write_ready = '1') and (event_ready_flag = '0')) then
232 ram_write_ea <= '0';
233 -- --
234 ram_write_ready_ack <= '1';
235 -- --
236 events_in_ram <= events_in_ram + 1;
237 if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then
238 event_start_addr <= event_start_addr + event_size_ram_64b;
239 else
240 event_start_addr <= 0;
241 end if;
242 event_ready_flag <= '1';
243 end if;
244
245
246 when MM_MAIN2 =>
247 state_mm <= MM_MAIN3;
248 if ((event_ready_flag = '1') and (ram_write_ready = '0')) then
249 if (events_in_ram < max_events_ram) then
250 ram_write_ea <= '1';
251 ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B);
252 event_ready_flag <= '0';
253 -- --
254 ram_write_ready_ack <= '0';
255 -- --
256 end if;
257 end if;
258
259 when MM_MAIN3 =>
260 state_mm <= MM_MAIN4;
261 if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then
262 wiz_ack_flag <= '1';
263 wiz_write_ea <= '0';
264 package_index <= package_index + 1;
265 if (package_index = (number_of_packages - 1)) then
266 -- next address
267 if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then
268 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
269 else
270 write_start_addr <= 0;
271 end if;
272 else
273 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
274 end if;
275 end if; -- wiz_ack_int
276
277 when MM_MAIN4 =>
278 state_mm <= MM_MAIN;
279 if ((events_in_ram > 0) and (wiz_busy = '0')) then
280 if (package_index < number_of_packages) then
281 wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B);
282 wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17);
283 wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4);
284 wiz_write_ea <= '1';
285 wiz_ack_flag <= '0';
286 if (package_index = 0) then
287 -- first package -> write header
288 wiz_write_header <= '1';
289 else
290 wiz_write_header <= '0';
291 end if;
292 if (package_index = (number_of_packages - 1)) then
293 -- last package -> write end-flag
294 wiz_write_end <= '1';
295 else
296 wiz_write_end <= '0';
297 end if;
298 else
299 events_in_ram <= events_in_ram - 1;
300 package_index <= 0;
301 end if;
302 end if;
303
304
305 end case; -- state_mm
306 end if;
307 end process mm;
308
309
310
311END ARCHITECTURE beha;
312
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