source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd@ 9912

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1--
2-- VHDL Architecture FACT_FAD_lib.memory_manager.beha
3--
4-- Created:
5-- by - kai.UNKNOWN (E5PCXX)
6-- at - 14:33:25 02.03.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9--
10library ieee;
11use ieee.std_logic_1164.all;
12use IEEE.STD_LOGIC_ARITH.all;
13use ieee.STD_LOGIC_UNSIGNED.all;
14
15library FACT_FAD_lib;
16use FACT_FAD_lib.fad_definitions.all;
17
18-- library UNISIM;
19-- use UNISIM.VComponents.all;
20-- USE IEEE.NUMERIC_STD.all;
21
22-- RAM_ADDR_WIDTH_64B is used for
23-- output ram_start_addr
24
25-- RAM_ADDR_WIDTH_16B is used for
26-- output wiz_ram_start_addr
27
28
29ENTITY memory_manager IS
30 generic(
31 RAM_ADDR_WIDTH_64B : integer := 12;
32 RAM_ADDR_WIDTH_16B : integer := 14
33 );
34 PORT(
35 clk : IN std_logic;
36 config_start : IN std_logic;
37 ram_write_ready : IN std_logic;
38 roi_array : IN roi_array_type;
39 ram_write_ea : OUT std_logic := '0';
40 config_ready, config_started : OUT std_logic := '0';
41 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
42 package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
43 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0');
44 wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
45 wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
46 wiz_write_ea : OUT std_logic := '0';
47 wiz_write_header : OUT std_logic := '0';
48 wiz_write_end : OUT std_logic := '0';
49 wiz_busy : IN std_logic;
50 wiz_ack : IN std_logic;
51 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
52 );
53
54-- Declarations
55
56END memory_manager ;
57
58--
59ARCHITECTURE beha OF memory_manager IS
60
61type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1);
62signal state_mm : state_mm_type := MM_CONFIG;
63
64--type roi_array_type is array (0 to 35) of integer range 0 to 1024;
65type roi_max_array_type is array (0 to 8) of integer range 0 to 1024;
66type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
67type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
68type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9;
69type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B;
70
71signal roi_max_array : roi_max_array_type := (others => 0);
72
73-- size of channel groups (16 bit)
74signal channel_size : channel_size_type := (others => 0);
75-- write length of packages (16 bit)
76signal fifo_write_length : fifo_write_length_type := (others => 0);
77-- number of channels per package
78signal fifo_channels_array : fifo_channels_array_type := (others => 0);
79-- size of packages in ram (16 bit)
80signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0);
81--
82signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0;
83signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0;
84signal event_size : integer range 0 to RAM_SIZE_16B := 0;
85
86signal drs_id : integer range 0 to 4 := 0;
87signal channel_id : integer range 0 to 9 := 0;
88signal channel_index : integer range 0 to 9 := 0;
89signal package_index : integer range 0 to 9 := 0;
90signal number_of_packages : integer range 0 to 9 := 0;
91signal max_events_ram, events_in_ram : integer range 0 to 2048;
92signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1);
93signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1);
94signal event_ready_flag : std_logic := '0';
95signal wiz_ack_flag : std_logic := '0';
96
97signal roi_index : integer range 0 to 45 := 0;
98signal temp_roi : integer range 0 to 1024 := 0;
99
100BEGIN
101
102 mm : process (clk)
103 begin
104 if rising_edge (clk) then
105 case state_mm is
106
107 when MM_CONFIG =>
108 if (config_start = '1') then
109 config_started <= '1';
110 roi_max_array <= (others => 0);
111 channel_size <= (others => 0);
112 fifo_write_length <= (others => 0);
113 fifo_channels_array <= (others => 0);
114 event_size <= 0;
115 ram_write_ea <= '0';
116 state_mm <= MAX_ROI;
117 end if;
118
119 -- calculate max ROIs and channel sizes
120 when MAX_ROI =>
121 roi_index <= (drs_id * 9) + channel_id;
122 state_mm <= MAX_ROI1;
123 when MAX_ROI1 =>
124 temp_roi <= roi_array (roi_index);
125 state_mm <= MAX_ROI2;
126 when MAX_ROI2 =>
127 if (channel_id < 9) then
128 if ( temp_roi > roi_max_array (channel_id)) then
129 roi_max_array (channel_id) <= temp_roi;
130 end if;
131 channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;
132 drs_id <= drs_id + 1;
133 state_mm <= MAX_ROI;
134 if (drs_id = 3) then
135 drs_id <= 0;
136 channel_id <= channel_id + 1;
137 end if;
138 else
139 drs_id <= 0;
140 channel_id <= 0;
141 channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH;
142 channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH;
143 state_mm <= FIFO_CALC;
144 end if;
145
146 -- calculate number of channels that fit in FIFO
147 when FIFO_CALC =>
148 if (channel_id < 9) then
149 if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then
150 fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id);
151 fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1;
152 channel_id <= channel_id + 1;
153 event_size <= event_size + channel_size (channel_id);
154 else
155 package_index <= package_index + 1;
156 end if;
157 else
158 number_of_packages <= package_index + 1;
159 package_index <= 0;
160 channel_index <= 0;
161 channel_id <= 0;
162 fifo_package_size_ram <= (others => 0);
163 fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6;
164 event_size_ram <= 0;
165 event_size_ram_64b <= 0;
166 max_events_ram <= 0;
167 state_mm <= RAM_CALC;
168 end if;
169
170 when RAM_CALC =>
171 if (package_index < number_of_packages) then
172 if (channel_index < fifo_channels_array (package_index)) then
173 fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4);
174 channel_index <= channel_index + 1;
175 channel_id <= channel_id + 1;
176 else
177 package_index <= package_index + 1;
178 event_size_ram <= event_size_ram + fifo_package_size_ram (package_index);
179 channel_index <= 0;
180 end if;
181 else
182 fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4;
183 event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare
184 state_mm <= RAM_CALC1;
185 end if;
186 when RAM_CALC1 =>
187 max_events_ram <= max_events_ram + 1;
188 if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then
189 state_mm <= RAM_CALC1;
190 else
191 max_events_ram <= max_events_ram - 1;
192 state_mm <= RAM_CALC2;
193 end if;
194 when RAM_CALC2 =>
195 event_size_ram_64b <= (event_size_ram / 4);
196 events_in_ram <= 0;
197 event_start_addr <= 0;
198 write_start_addr <= 0;
199 package_index <= 0;
200 channel_id <= 0;
201 ram_start_addr <= (others => '0');
202 ram_write_ea <= '1';
203 config_started <= '0';
204 config_ready <= '1';
205 package_length <= conv_std_logic_vector (event_size, 16);
206 for i in 0 to 8 loop
207 roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11);
208 end loop;
209 state_mm <= MM_MAIN;
210
211 when MM_MAIN =>
212 state_mm <= MM_MAIN1;
213 if ((ram_write_ready = '1') and (event_ready_flag = '0')) then
214 ram_write_ea <= '0';
215 events_in_ram <= events_in_ram + 1;
216 if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then
217 event_start_addr <= event_start_addr + event_size_ram_64b;
218 else
219 event_start_addr <= 0;
220 end if;
221 event_ready_flag <= '1';
222 end if;
223
224
225 when MM_MAIN1 =>
226 state_mm <= MM_MAIN;
227 if (config_start = '1') then
228 config_ready <= '0';
229 if (events_in_ram = 0) then
230 state_mm <= MM_CONFIG;
231 end if;
232 end if;
233 if (event_ready_flag = '1') then
234 if (events_in_ram < max_events_ram) then
235 ram_write_ea <= '1';
236 ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B);
237 event_ready_flag <= '0';
238 end if;
239 end if;
240
241 if ((events_in_ram > 0) and (wiz_busy = '0')) then
242 if (package_index < number_of_packages) then
243 wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B);
244 wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17);
245 wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4);
246 wiz_write_ea <= '1';
247 wiz_ack_flag <= '0';
248 if (package_index = 0) then
249 -- first package -> write header
250 wiz_write_header <= '1';
251 else
252 wiz_write_header <= '0';
253 end if;
254 if (package_index = (number_of_packages - 1)) then
255 -- last package -> write end-flag
256 wiz_write_end <= '1';
257 else
258 wiz_write_end <= '0';
259 end if;
260 else
261 events_in_ram <= events_in_ram - 1;
262 package_index <= 0;
263 end if;
264 end if;
265
266 if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then
267 wiz_ack_flag <= '1';
268 wiz_write_ea <= '0';
269 package_index <= package_index + 1;
270 if (package_index = (number_of_packages - 1)) then
271 -- next address
272 if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then
273 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
274 else
275 write_start_addr <= 0;
276 end if;
277 else
278 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
279 end if;
280 end if; -- wiz_ack
281
282 end case; -- state_mm
283 end if;
284 end process mm;
285
286
287
288END ARCHITECTURE beha;
289
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