source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak@ 10074

Last change on this file since 10074 was 10074, checked in by neise, 15 years ago
added LED controller
File size: 29.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 s_trigger : OUT std_logic := '0';
56 new_config : OUT std_logic := '0';
57 config_started : in std_logic;
58 config_addr : out std_logic_vector (7 downto 0);
59 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
60 config_wr_en : out std_logic := '0';
61 config_rd_en : out std_logic := '0';
62 -- --
63 config_rw_ack, config_rw_ready : in std_logic;
64 -- --
65 config_busy : in std_logic;
66
67
68
69 denable : out std_logic := '0'; -- default domino wave off
70 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
71 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
72 ps_direction : out std_logic := '1'; -- default phase shift upwards
73 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
74 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
75
76 srclk_enable : out std_logic := '1' -- default SRCLK on.
77 );
78
79-- Declarations
80
81END w5300_modul ;
82
83architecture Behavioral of w5300_modul is
84
85type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
86 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
87 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
88type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
89 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
90type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
91type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
92type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
93
94signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
95
96signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
97signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
98signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
99signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
100
101signal state_init, next_state , next_state_tmp : state_init_type := RESET;
102signal count : std_logic_vector (2 downto 0) := "000";
103signal state_write : state_write_type := WR_START;
104signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
105signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
106signal state_read_data : state_read_data_type := RD_1;
107
108signal interrupt_ignore : std_logic := '1';
109signal int_flag : std_logic := '0';
110signal ram_access : std_logic := '0';
111
112signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
113signal data_cnt : integer := 0;
114signal drs_cnt : integer :=0;
115signal channel_cnt : integer range 0 to 9 :=0;
116signal socket_cnt : std_logic_vector (2 downto 0) := "000";
117signal roi_max : std_logic_vector (10 downto 0);
118signal data_end : integer := 0;
119
120signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
121signal write_length_bytes : std_logic_vector (16 downto 0);
122
123signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
124signal chk_recv_cntr : integer range 0 to 10000 := 0;
125
126-- --
127signal wait_cntr : integer range 0 to 10000 := 0;
128-- --
129
130signal rx_packets_cnt : std_logic_vector (15 downto 0);
131signal next_packet_data : std_logic := '0';
132signal new_config_flag : std_logic := '0';
133
134signal trigger_stop : std_logic := '1';
135
136signal local_write_length : std_logic_vector (16 DOWNTO 0);
137signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
138signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
139signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
140signal local_write_header_flag, local_write_end_flag : std_logic;
141signal local_fifo_channels : std_logic_vector (3 downto 0);
142
143signal data_valid_int : std_logic := '0';
144
145-- only for debugging
146--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
147--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
148
149
150begin
151
152 --synthesis translate_off
153 RST_TIME <= X"00120";
154 --synthesis translate_on
155
156
157 w5300_init_proc : process (clk, int)
158 begin
159
160 if rising_edge (clk) then
161
162 -- Interrupt low
163 if (int = '0') and (interrupt_ignore = '0') then
164 case state_interrupt_1 is
165 when IR1_01 =>
166 int_flag <= '1';
167 busy <= '1';
168 state_interrupt_1 <= IR1_02;
169 when IR1_02 =>
170 state_interrupt_1 <= IR1_03;
171 when IR1_03 =>
172 state_init <= INTERRUPT;
173 socket_cnt <= "000";
174 ram_access <= '0';
175 zaehler <= X"00000";
176 count <= "000";
177 int_flag <= '0';
178 interrupt_ignore <= '1';
179 state_interrupt_1 <= IR1_04;
180 when others =>
181 null;
182 end case;
183 end if; -- int = '0'
184
185 if int_flag = '0' then
186 case state_init is
187 -- Interrupt
188 when INTERRUPT =>
189 case state_interrupt_2 is
190 when IR2_01 =>
191 par_addr <= W5300_IR;
192 state_init <= READ_REG;
193 next_state <= INTERRUPT;
194 state_interrupt_2 <= IR2_02;
195 when IR2_02 =>
196 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
197 state_interrupt_2 <= IR2_03;
198 else
199 socket_cnt <= socket_cnt + 1;
200 if (socket_cnt = 7) then
201 state_interrupt_2 <= IR2_06;
202 else
203 state_interrupt_2 <= IR2_02;
204 end if;
205 end if;
206 when IR2_03 =>
207 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
208 state_init <= READ_REG;
209 next_state <= INTERRUPT;
210 state_interrupt_2 <= IR2_04;
211 when IR2_04 =>
212 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
213 par_data <= data_read; -- clear Interrupts
214 state_init <= WRITE_REG;
215 next_state <= INTERRUPT;
216 state_interrupt_2 <= IR2_05;
217 when IR2_05 =>
218 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
219 par_data <= X"0010"; -- CLOSE
220 state_init <= WRITE_REG;
221 next_state <= INTERRUPT;
222 socket_cnt <= socket_cnt + 1;
223 if (socket_cnt = 7) then
224 state_interrupt_2 <= IR2_06;
225 else
226 state_interrupt_2 <= IR2_01;
227 end if;
228
229 when IR2_06 =>
230 state_interrupt_1 <= IR1_01;
231 state_interrupt_2 <= IR2_01;
232 socket_cnt <= "000";
233 state_init <= RESET;
234 end case;
235
236 -- reset W5300
237 when RESET =>
238 busy <= '1';
239 zaehler <= zaehler + 1;
240 wiz_reset <= '0';
241-- led <= X"FF";
242 if (zaehler >= X"00064") then -- wait 2µs
243 wiz_reset <= '1';
244 end if;
245 if (zaehler = RST_TIME) then -- wait 10ms
246 zaehler <= X"00000";
247 socket_cnt <= "000";
248 count <= "000";
249 ram_access <= '0';
250 interrupt_ignore <= '0';
251 rd <= '1';
252 wr <= '1';
253 cs <= '1';
254 state_write <= WR_START;
255 state_init <= INIT;
256 end if;
257
258 -- Init
259 when INIT =>
260 par_addr <= W5300_MR;
261 par_data <= X"0000";
262 state_init <= WRITE_REG;
263 next_state <= IM;
264
265 -- Interrupt Mask
266 when IM =>
267 par_addr <= W5300_IMR;
268 par_data <= X"00FF"; -- S0-S7 Interrupts
269 state_init <= WRITE_REG;
270 next_state <= MT;
271
272 -- Memory Type
273 when MT =>
274 par_addr <= W5300_MTYPER;
275 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
276 state_init <= WRITE_REG;
277 next_state <= STX;
278
279 -- Socket TX Memory Size
280 when STX =>
281 par_data <= X"0F0F"; -- 15K TX
282
283 par_addr <= W5300_TMS01R;
284 state_init <=WRITE_REG;
285 next_state <= STX1;
286 when STX1 =>
287 par_addr <= W5300_TMS23R;
288 state_init <=WRITE_REG;
289 next_state <= STX2;
290 when STX2 =>
291 par_addr <= W5300_TMS45R;
292 state_init <=WRITE_REG;
293 next_state <= STX3;
294 when STX3 =>
295 par_addr <= W5300_TMS67R;
296 state_init <=WRITE_REG;
297 next_state <= SRX;
298
299 -- Socket RX Memory Size
300 when SRX =>
301 par_data <= X"0101"; -- 1K RX
302
303 par_addr <= W5300_RMS01R;
304 state_init <=WRITE_REG;
305 next_state <= SRX1;
306 when SRX1 =>
307 par_addr <= W5300_RMS23R;
308 state_init <=WRITE_REG;
309 next_state <= SRX2;
310 when SRX2 =>
311 par_addr <= W5300_RMS45R;
312 state_init <=WRITE_REG;
313 next_state <= SRX3;
314 when SRX3 =>
315 par_addr <= W5300_RMS67R;
316 state_init <=WRITE_REG;
317 next_state <= MAC;
318
319 -- MAC
320 when MAC =>
321 par_addr <= W5300_SHAR;
322 par_data <= MAC_ADDRESS (0);
323 state_init <= WRITE_REG;
324 next_state <= MAC1;
325 when MAC1 =>
326 par_addr <= W5300_SHAR + 2;
327 par_data <= MAC_ADDRESS (1);
328 state_init <= WRITE_REG;
329 next_state <= MAC2;
330 when MAC2 =>
331 par_addr <= W5300_SHAR + 4;
332 par_data <= MAC_ADDRESS (2);
333 state_init <= WRITE_REG;
334 next_state <= GW;
335
336 -- Gateway
337 when GW =>
338 par_addr <= W5300_GAR;
339 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
340 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
341 state_init <= WRITE_REG;
342 next_state <= GW1;
343 when GW1 =>
344 par_addr <= W5300_GAR + 2;
345 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
346 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
347 state_init <= WRITE_REG;
348 next_state <= SNM;
349
350 -- Subnet Mask
351 when SNM =>
352 par_addr <= W5300_SUBR;
353 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
354 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
355 state_init <= WRITE_REG;
356 next_state <= SNM1;
357 when SNM1 =>
358 par_addr <= W5300_SUBR + 2;
359 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
360 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
361 state_init <= WRITE_REG;
362 next_state <= IP;
363 -- Own IP-Address
364 when IP =>
365 par_addr <= W5300_SIPR;
366 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
367 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
368 state_init <= WRITE_REG;
369 next_state <= IP1;
370 when IP1 =>
371 par_addr <= W5300_SIPR + 2;
372 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
373 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
374 state_init <= WRITE_REG;
375 next_state <= SI;
376-- when TIMEOUT =>
377-- par_addr <= W5300_RTR;
378-- par_data <= X"07D0"; -- 0x07D0 = 200ms
379-- state_init <= WRITE_REG;
380-- next_state <= RETRY;
381-- when RETRY =>
382-- par_addr <= W5300_RCR;
383-- par_data <= X"0008";
384-- state_init <= WRITE_REG;
385-- next_state <= SI;
386--
387
388 -- Socket Init
389 when SI =>
390 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
391 par_data <= X"0101"; -- ALIGN, TCP
392 state_init <= WRITE_REG;
393 next_state <= SI1;
394 -- Sx Interrupt Mask
395 when SI1 =>
396 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
397 par_data <= X"000A"; -- TIMEOUT, DISCON
398 state_init <= WRITE_REG;
399 next_state <= SI2;
400 when SI2 =>
401 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
402 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
403 state_init <= WRITE_REG;
404 next_state <= SI3;
405 when SI3 =>
406 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
407 par_data <= X"0001"; -- OPEN
408 state_init <= WRITE_REG;
409 next_state <= SI4;
410 when SI4 =>
411 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
412 state_init <= READ_REG;
413 next_state <= SI5;
414 when SI5 =>
415 if (data_read (7 downto 0) = X"13") then -- is open?
416 state_init <= SI6;
417 else
418 state_init <= SI4;
419 end if;
420 when SI6 =>
421 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
422 par_data <= X"0002"; -- LISTEN
423 state_init <= WRITE_REG;
424 socket_cnt <= socket_cnt + 1;
425 if (socket_cnt = 7) then
426 socket_cnt <= "000";
427 next_state <= ESTABLISH; -- All Sockets open
428 else
429 next_state <= SI; -- Next Socket
430 end if;
431 -- End Socket Init
432
433 when ESTABLISH =>
434 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
435 state_init <= READ_REG;
436 next_state <= EST1;
437 when EST1 =>
438-- led <= data_read (7 downto 0);
439-- led <= X"00";
440 case data_read (7 downto 0) is
441 when X"17" => -- established
442 if (socket_cnt = 7) then
443 socket_cnt <= "000";
444 busy <= '0';
445 state_init <= MAIN;
446 else
447 socket_cnt <= socket_cnt + 1;
448 state_init <= ESTABLISH;
449 end if;
450 when others =>
451 state_init <= ESTABLISH;
452 end case;
453
454 when CONFIG =>
455-- led <= X"F0";
456 new_config <= '1';
457 if (config_started = '1') then
458-- led <= X"0F";
459 new_config <= '0';
460 state_init <= MAIN;
461 end if;
462
463 -- main "loop"
464 when MAIN =>
465 ps_do_phase_shift <= '0';
466 ps_reset <= '0';
467 if (trigger_stop = '1') then
468 s_trigger <= '0';
469 end if;
470 data_valid_ack <= '0';
471 state_init <= MAIN1;
472 data_valid_int <= data_valid;
473 when MAIN1 =>
474 if (chk_recv_cntr = 1000) then
475 chk_recv_cntr <= 0;
476 state_read_data <= RD_1;
477 state_init <= READ_DATA;
478 busy <= '1';
479 else
480 chk_recv_cntr <= chk_recv_cntr + 1;
481 state_init <= MAIN2;
482 end if;
483 when MAIN2 =>
484 busy <= '0';
485 if (data_valid = '1') then
486 data_valid_int <= '0';
487 busy <= '1';
488 local_write_length <= write_length;
489 local_ram_start_addr <= ram_start_addr;
490 local_ram_addr <= (others => '0');
491 local_write_header_flag <= write_header_flag;
492 local_write_end_flag <= write_end_flag;
493 local_fifo_channels <= fifo_channels;
494-- data_valid_ack <= '1';
495-- next_state <= MAIN;
496-- state_init <= WRITE_DATA;
497 state_init <= MAIN3;
498 else
499 state_init <= MAIN1;
500 end if;
501 when MAIN3 =>
502-- led <= local_ram_start_addr (7 downto 0);
503 data_valid_ack <= '1';
504 next_state <= MAIN;
505 state_init <= WRITE_DATA;
506
507
508 -- read data from socket 0
509 when READ_DATA =>
510 case state_read_data is
511 when RD_1 =>
512 par_addr <= W5300_S0_RX_RSR;
513 state_init <= READ_REG;
514 next_state <= READ_DATA;
515 state_read_data <= RD_2;
516 when RD_2 =>
517 socket_rx_received (31 downto 16) <= data_read;
518 par_addr <= W5300_S0_RX_RSR + X"2";
519 state_init <= READ_REG;
520 next_state <= READ_DATA;
521 state_read_data <= RD_3;
522 when RD_3 =>
523 socket_rx_received (15 downto 0) <= data_read;
524 state_read_data <= RD_4;
525 when RD_4 =>
526 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
527 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
528 state_read_data <= RD_5;
529 else
530 busy <= '0';
531 state_init <= MAIN;
532 end if;
533 when RD_5 =>
534 if (rx_packets_cnt > 0) then
535 rx_packets_cnt <= rx_packets_cnt - '1';
536 par_addr <= W5300_S0_RX_FIFOR;
537 state_init <= READ_REG;
538 next_state <= READ_DATA;
539 state_read_data <= RD_6;
540 else
541 state_read_data <= RD_END;
542 end if;
543 when RD_6 =>
544-- led <= data_read (15 downto 8);
545 -- read command
546 if (next_packet_data = '0') then
547 case data_read (15 downto 8) is
548 when CMD_TRIGGER =>
549 trigger_stop <= '1';
550 s_trigger <= '1';
551 state_read_data <= RD_5;
552 when CMD_DWRITE_RUN =>
553 dwrite_enable <= '1';
554 state_read_data <= RD_5;
555 when CMD_DWRITE_STOP =>
556 dwrite_enable <= '0';
557 state_read_data <= RD_5;
558 when CMD_SCLK_ON =>
559 sclk_enable <= '1';
560 state_read_data <= RD_5;
561 when CMD_SCLK_OFF =>
562 sclk_enable <= '0';
563 state_read_data <= RD_5;
564 when CMD_DENABLE =>
565 denable <= '1';
566 state_read_data <= RD_5;
567 when CMD_DDISABLE =>
568 denable <= '0';
569 state_read_data <= RD_5;
570 when CMD_TRIGGER_C =>
571 trigger_stop <= '0';
572 s_trigger <= '1';
573 state_read_data <= RD_5;
574 when CMD_TRIGGER_S =>
575 trigger_stop <= '1';
576 state_read_data <= RD_5;
577 -- phase shift commands here:
578 when CMD_PS_DO =>
579 ps_do_phase_shift <= '1';
580 state_read_data <= RD_5;
581 when CMD_PS_DIRINC =>
582 ps_direction <= '1';
583 state_read_data <= RD_5;
584 when CMD_PS_RESET =>
585 ps_reset <= '1';
586 state_read_data <= RD_5;
587 when CMD_SRCLK_ON =>
588 srclk_enable <= '1';
589 state_read_data <= RD_5;
590 when CMD_SRCLK_OFF =>
591 srclk_enable <= '0';
592 state_read_data <= RD_5;
593 when CMD_PS_DIRDEC =>
594 ps_direction <= '0';
595 state_read_data <= RD_5;
596 when CMD_WRITE =>
597 next_packet_data <= '1';
598 config_addr <= data_read (7 downto 0);
599 state_read_data <= RD_5;
600 when others =>
601 state_read_data <= RD_5;
602 end case;
603 -- read data
604 else
605 if (config_busy = '0') then
606 config_data <= data_read;
607 config_wr_en <= '1';
608 new_config_flag <= '1';
609 next_packet_data <= '0';
610 state_read_data <= RD_WAIT;
611 end if;
612 end if;
613 when RD_WAIT =>
614 if (config_rw_ack = '1') then
615 state_read_data <= RD_WAIT1;
616 end if;
617 when RD_WAIT1 =>
618 if (config_rw_ready = '1') then
619 config_data <= (others => 'Z');
620 config_wr_en <= '0';
621 state_read_data <= RD_5;
622 end if;
623 when RD_END =>
624 par_addr <= W5300_S0_CR;
625 par_data <= X"0040"; -- RECV
626 state_init <= WRITE_REG;
627 if (new_config_flag = '1') then
628 new_config_flag <= '0';
629 next_state <= CONFIG;
630 else
631 next_state <= MAIN;
632 end if;
633
634 end case; -- state_data_read
635
636
637
638 when WRITE_DATA =>
639 case state_write is
640 when WR_START =>
641 if (local_write_header_flag = '1') then
642 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
643 end if;
644 state_write <= WR_WAIT1;
645 when WR_WAIT1 =>
646 state_write <= WR_LENGTH;
647 when WR_LENGTH =>
648 if (local_write_header_flag = '1') then
649 local_socket_nr <= ram_data (2 downto 0);
650-- local_socket_nr <= "000";
651 end if;
652 next_state_tmp <= next_state;
653 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
654 data_cnt <= 0;
655 state_write <= WR_01;
656 -- Check FIFO Size
657 when WR_01 =>
658 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
659 state_init <= READ_REG;
660 next_state <= WRITE_DATA;
661 state_write <= WR_02;
662 when WR_02 =>
663 socket_tx_free (31 downto 16) <= data_read;
664 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
665 state_init <= READ_REG;
666 next_state <= WRITE_DATA;
667 state_write <= WR_03;
668 when WR_03 =>
669 socket_tx_free (15 downto 0) <= data_read;
670 state_write <= WR_04;
671 when WR_04 =>
672
673-- led <= socket_tx_free (15 downto 8);
674
675-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
676 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
677 state_write <= WR_01;
678 else
679 if (local_write_header_flag = '1') then
680 state_write <= WR_FIFO;
681 else
682 state_write <= WR_ADC;
683 end if;
684 end if;
685
686 -- Fill FIFO
687
688 -- Write Header
689 when WR_FIFO =>
690 ram_addr <= local_ram_start_addr + local_ram_addr;
691 state_write <= WR_FIFO1;
692 when WR_FIFO1 =>
693 data_cnt <= data_cnt + 1;
694 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
695 local_ram_addr <= local_ram_addr + 1;
696 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
697 local_ram_addr <= local_ram_addr + 2;
698 end if;
699 if (data_cnt = 9) then -- skip empty words
700 local_ram_addr <= local_ram_addr + 4;
701 end if;
702 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
703 ram_access <= '1';
704 state_init <= WRITE_REG;
705 next_state <= WRITE_DATA;
706 state_write <= WR_FIFO;
707 else
708 state_write <= WR_ADC;
709 end if;
710 -- End Write Header
711
712 -- Write ADC-Data
713 ---- Start...
714 when WR_ADC =>
715 adc_data_addr <= local_ram_start_addr + local_ram_addr;
716 drs_cnt <= 0;
717 channel_cnt <= 1;
718 data_cnt <= 0;
719 roi_max <= (others => '0');
720 data_end <= 3;
721 state_write <= WR_ADC1;
722
723 ---- Write Channel
724 when WR_ADC1 =>
725 -- read ROI and set end of Channel-Data
726 if (data_cnt = 3) then
727 data_end <= conv_integer (ram_data) + 3;
728 if (ram_data > roi_max) then
729 roi_max <= ram_data (10 downto 0);
730 end if;
731 end if;
732 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
733 state_write <= WR_ADC2;
734 when WR_ADC2 =>
735 if (data_cnt < data_end) then
736 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
737 ram_access <= '1';
738 state_init <= WRITE_REG;
739 next_state <= WRITE_DATA;
740 data_cnt <= data_cnt + 1;
741 state_write <= WR_ADC1;
742 else
743 -- Next DRS
744 if (drs_cnt < 3) then
745 drs_cnt <= drs_cnt + 1;
746 data_cnt <= 0;
747 data_end <= 3;
748 state_write <= WR_ADC1;
749 else
750 -- Next Channel
751 if (channel_cnt < local_fifo_channels) then
752 channel_cnt <= channel_cnt + 1;
753 roi_max <= (others => '0');
754 drs_cnt <= 0;
755 data_cnt <= 0;
756 data_end <= 3;
757 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
758 state_write <= WR_ADC1;
759 else
760 -- Ready
761 if (local_write_end_flag = '1') then
762 state_write <= WR_ENDFLAG;
763 else
764 state_write <= WR_05;
765 end if;
766 end if;
767 end if;
768 end if;
769 -- End Write ADC-Data
770
771 -- Write End Package Flag
772 when WR_ENDFLAG =>
773 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
774 state_write <= WR_ENDFLAG1;
775 when WR_ENDFLAG1 =>
776 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
777 ram_access <= '1';
778 state_init <= WRITE_REG;
779 next_state <= WRITE_DATA;
780 state_write <= WR_ENDFLAG2;
781 when WR_ENDFLAG2 =>
782 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
783 state_write <= WR_ENDFLAG3;
784 when WR_ENDFLAG3 =>
785 state_init <= WRITE_REG;
786 next_state <= WRITE_DATA;
787 state_write <= WR_05a;
788
789 -- End Write End Package Flag
790
791 -- Wait????
792 when WR_05a =>
793 if (wait_cntr < 10) then -- 3000 works???
794 wait_cntr <= wait_cntr + 1;
795 else
796 wait_cntr <= 0;
797 state_write <= WR_05b;
798 end if;
799 when WR_05b =>
800 state_write <= WR_05;
801
802 --Send FIFO
803 when WR_05 =>
804 ram_access <= '0';
805 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
806 par_data <= (0 => write_length_bytes (16), others => '0');
807 state_init <= WRITE_REG;
808 state_write <= WR_06;
809 when WR_06 =>
810 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
811 par_data <= write_length_bytes (15 downto 0);
812 state_init <= WRITE_REG;
813 state_write <= WR_07;
814 when WR_07 =>
815 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
816 par_data <= X"0020"; -- Send
817 state_init <= WRITE_REG;
818 state_write <= WR_08;
819 when others =>
820 state_init <= next_state_tmp;
821 state_write <= WR_START;
822 end case;
823 -- End WRITE_DATA
824
825 when READ_REG =>
826 case count is
827 when "000" =>
828 cs <= '0';
829 rd <= '0';
830 wr <= '1';
831 data <= (others => 'Z'); -- !!!!!!!!!!
832 count <= "001";
833 addr <= par_addr;
834 when "001" =>
835 count <= "010";
836 when "010" =>
837 count <= "100";
838 when "100" =>
839 data_read <= data;
840 count <= "110";
841 when "110" =>
842 count <= "111";
843 when "111" =>
844 cs <= '1';
845 rd <= '1';
846 count <= "000";
847 state_init <= next_state;
848 when others =>
849 null;
850 end case;
851
852 when WRITE_REG =>
853 case count is
854 when "000" =>
855 cs <= '0';
856 wr <= '0';
857 rd <= '1';
858 addr <= par_addr;
859 if (ram_access = '1') then
860 data <= ram_data;
861 else
862 data <= par_data;
863 end if;
864 count <= "100";
865 when "100" =>
866 count <= "101";
867 when "101" =>
868 count <= "110";
869 when "110" =>
870 cs <= '1';
871 wr <= '1';
872 state_init <= next_state;
873 count <= "000";
874 when others =>
875 null;
876 end case;
877
878 when others =>
879 null;
880 end case;
881 end if; -- int_flag = '0'
882
883 end if; -- rising_edge (clk)
884
885 end process w5300_init_proc;
886
887end Behavioral;
888
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