source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak@ 10121

Last change on this file since 10121 was 10121, checked in by neise, 12 years ago
synchronous trigger handling added continous soft trigger generation. ---> control frequency via 'send 0x21??' each step increases trigger delay by 12.5ms 0x2100 = 40Hz 0x21FF = 0.3Hz
File size: 31.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 -- softtrigger:
56 s_trigger : OUT std_logic := '0';
57 c_trigger_enable: out std_logic := '0';
58 c_trigger_mult: out std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject to changes
59 --
60 new_config : OUT std_logic := '0';
61 config_started : in std_logic;
62 config_addr : out std_logic_vector (7 downto 0);
63 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
64 config_wr_en : out std_logic := '0';
65 config_rd_en : out std_logic := '0';
66 -- --
67 config_rw_ack, config_rw_ready : in std_logic;
68 -- --
69 config_busy : in std_logic;
70
71
72
73 denable : out std_logic := '0'; -- default domino wave off
74 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
75 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
76 ps_direction : out std_logic := '1'; -- default phase shift upwards
77 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
78 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
79
80 srclk_enable : out std_logic := '1'; -- default SRCLK on.
81
82 trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted
83
84 socks_waiting : out std_logic;
85 socks_connected: out std_logic
86 );
87
88-- Declarations
89
90END w5300_modul ;
91
92architecture Behavioral of w5300_modul is
93
94type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
95 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
96 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
97type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
98 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
99type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
100type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
101type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
102
103signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
104
105signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
106signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
107signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
108signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
109
110signal state_init, next_state , next_state_tmp : state_init_type := RESET;
111signal count : std_logic_vector (2 downto 0) := "000";
112signal state_write : state_write_type := WR_START;
113signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
114signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
115signal state_read_data : state_read_data_type := RD_1;
116
117signal interrupt_ignore : std_logic := '1';
118signal int_flag : std_logic := '0';
119signal ram_access : std_logic := '0';
120
121signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
122signal data_cnt : integer := 0;
123signal drs_cnt : integer :=0;
124signal channel_cnt : integer range 0 to 9 :=0;
125signal socket_cnt : std_logic_vector (2 downto 0) := "000";
126signal roi_max : std_logic_vector (10 downto 0);
127signal data_end : integer := 0;
128
129signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
130signal write_length_bytes : std_logic_vector (16 downto 0);
131
132signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
133signal chk_recv_cntr : integer range 0 to 10000 := 0;
134
135-- --
136signal wait_cntr : integer range 0 to 10000 := 0;
137-- --
138
139signal rx_packets_cnt : std_logic_vector (15 downto 0);
140signal next_packet_data : std_logic := '0';
141signal new_config_flag : std_logic := '0';
142
143signal trigger_stop : std_logic := '1';
144
145signal local_write_length : std_logic_vector (16 DOWNTO 0);
146signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
147signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
148signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
149signal local_write_header_flag, local_write_end_flag : std_logic;
150signal local_fifo_channels : std_logic_vector (3 downto 0);
151
152signal data_valid_int : std_logic := '0';
153
154-- only for debugging
155--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
156--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
157
158
159-- signals for different socket modes: DN 04.01.11
160signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
161signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
162
163begin
164
165 --synthesis translate_off
166 RST_TIME <= X"00120";
167 --synthesis translate_on
168
169
170 w5300_init_proc : process (clk, int)
171 begin
172
173 if rising_edge (clk) then
174
175 -- Interrupt low
176 if (int = '0') and (interrupt_ignore = '0') then
177 case state_interrupt_1 is
178 when IR1_01 =>
179 int_flag <= '1';
180 busy <= '1';
181 state_interrupt_1 <= IR1_02;
182 when IR1_02 =>
183 state_interrupt_1 <= IR1_03;
184 when IR1_03 =>
185 state_init <= INTERRUPT;
186 socket_cnt <= "000";
187 ram_access <= '0';
188 zaehler <= X"00000";
189 count <= "000";
190 int_flag <= '0';
191 interrupt_ignore <= '1';
192 state_interrupt_1 <= IR1_04;
193 when others =>
194 null;
195 end case;
196 end if; -- int = '0'
197
198 if int_flag = '0' then
199 case state_init is
200 -- Interrupt
201 when INTERRUPT =>
202 case state_interrupt_2 is
203 when IR2_01 =>
204 par_addr <= W5300_IR;
205 state_init <= READ_REG;
206 next_state <= INTERRUPT;
207 state_interrupt_2 <= IR2_02;
208 when IR2_02 =>
209 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
210 state_interrupt_2 <= IR2_03;
211 else
212 socket_cnt <= socket_cnt + 1;
213 if (socket_cnt = 7) then
214 state_interrupt_2 <= IR2_06;
215 else
216 state_interrupt_2 <= IR2_02;
217 end if;
218 end if;
219 when IR2_03 =>
220 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
221 state_init <= READ_REG;
222 next_state <= INTERRUPT;
223 state_interrupt_2 <= IR2_04;
224 when IR2_04 =>
225 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
226 par_data <= data_read; -- clear Interrupts
227 state_init <= WRITE_REG;
228 next_state <= INTERRUPT;
229 state_interrupt_2 <= IR2_05;
230 when IR2_05 =>
231 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
232 par_data <= X"0010"; -- CLOSE
233 state_init <= WRITE_REG;
234 next_state <= INTERRUPT;
235 socket_cnt <= socket_cnt + 1;
236 if (socket_cnt = 7) then
237 state_interrupt_2 <= IR2_06;
238 else
239 state_interrupt_2 <= IR2_01;
240 end if;
241
242 when IR2_06 =>
243 state_interrupt_1 <= IR1_01;
244 state_interrupt_2 <= IR2_01;
245 socket_cnt <= "000";
246 state_init <= RESET;
247 end case;
248
249 -- reset W5300
250 when RESET =>
251 socket_send_mode <= '0';
252 busy <= '1';
253 zaehler <= zaehler + 1;
254 socks_waiting <= '0';
255 socks_connected <= '0';
256 wiz_reset <= '0';
257-- led <= X"FF";
258 if (zaehler >= X"00064") then -- wait 2µs
259 wiz_reset <= '1';
260 end if;
261 if (zaehler = RST_TIME) then -- wait 10ms
262 zaehler <= X"00000";
263 socket_cnt <= "000";
264 count <= "000";
265 ram_access <= '0';
266 interrupt_ignore <= '0';
267 rd <= '1';
268 wr <= '1';
269 cs <= '1';
270 state_write <= WR_START;
271 state_init <= INIT;
272 end if;
273
274 -- Init
275 when INIT =>
276 par_addr <= W5300_MR;
277 par_data <= X"0000";
278 state_init <= WRITE_REG;
279 next_state <= IM;
280
281 -- Interrupt Mask
282 when IM =>
283 par_addr <= W5300_IMR;
284 par_data <= X"00FF"; -- S0-S7 Interrupts
285 state_init <= WRITE_REG;
286 next_state <= MT;
287
288 -- Memory Type
289 when MT =>
290 par_addr <= W5300_MTYPER;
291 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
292 state_init <= WRITE_REG;
293 next_state <= STX;
294
295 -- Socket TX Memory Size
296 when STX =>
297 par_data <= X"0F0F"; -- 15K TX
298
299 par_addr <= W5300_TMS01R;
300 state_init <=WRITE_REG;
301 next_state <= STX1;
302 when STX1 =>
303 par_addr <= W5300_TMS23R;
304 state_init <=WRITE_REG;
305 next_state <= STX2;
306 when STX2 =>
307 par_addr <= W5300_TMS45R;
308 state_init <=WRITE_REG;
309 next_state <= STX3;
310 when STX3 =>
311 par_addr <= W5300_TMS67R;
312 state_init <=WRITE_REG;
313 next_state <= SRX;
314
315 -- Socket RX Memory Size
316 when SRX =>
317 par_data <= X"0101"; -- 1K RX
318
319 par_addr <= W5300_RMS01R;
320 state_init <=WRITE_REG;
321 next_state <= SRX1;
322 when SRX1 =>
323 par_addr <= W5300_RMS23R;
324 state_init <=WRITE_REG;
325 next_state <= SRX2;
326 when SRX2 =>
327 par_addr <= W5300_RMS45R;
328 state_init <=WRITE_REG;
329 next_state <= SRX3;
330 when SRX3 =>
331 par_addr <= W5300_RMS67R;
332 state_init <=WRITE_REG;
333 next_state <= MAC;
334
335 -- MAC
336 when MAC =>
337 par_addr <= W5300_SHAR;
338 par_data <= MAC_ADDRESS (0);
339 state_init <= WRITE_REG;
340 next_state <= MAC1;
341 when MAC1 =>
342 par_addr <= W5300_SHAR + 2;
343 par_data <= MAC_ADDRESS (1);
344 state_init <= WRITE_REG;
345 next_state <= MAC2;
346 when MAC2 =>
347 par_addr <= W5300_SHAR + 4;
348 par_data <= MAC_ADDRESS (2);
349 state_init <= WRITE_REG;
350 next_state <= GW;
351
352 -- Gateway
353 when GW =>
354 par_addr <= W5300_GAR;
355 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
356 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
357 state_init <= WRITE_REG;
358 next_state <= GW1;
359 when GW1 =>
360 par_addr <= W5300_GAR + 2;
361 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
362 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
363 state_init <= WRITE_REG;
364 next_state <= SNM;
365
366 -- Subnet Mask
367 when SNM =>
368 par_addr <= W5300_SUBR;
369 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
370 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
371 state_init <= WRITE_REG;
372 next_state <= SNM1;
373 when SNM1 =>
374 par_addr <= W5300_SUBR + 2;
375 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
376 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
377 state_init <= WRITE_REG;
378 next_state <= IP;
379 -- Own IP-Address
380 when IP =>
381 par_addr <= W5300_SIPR;
382 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
383 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
384 state_init <= WRITE_REG;
385 next_state <= IP1;
386 when IP1 =>
387 par_addr <= W5300_SIPR + 2;
388 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
389 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
390 state_init <= WRITE_REG;
391 next_state <= SI;
392-- when TIMEOUT =>
393-- par_addr <= W5300_RTR;
394-- par_data <= X"07D0"; -- 0x07D0 = 200ms
395-- state_init <= WRITE_REG;
396-- next_state <= RETRY;
397-- when RETRY =>
398-- par_addr <= W5300_RCR;
399-- par_data <= X"0008";
400-- state_init <= WRITE_REG;
401-- next_state <= SI;
402--
403
404 -- Socket Init
405 when SI =>
406 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
407 par_data <= X"0101"; -- ALIGN, TCP
408 state_init <= WRITE_REG;
409 next_state <= SI1;
410 -- Sx Interrupt Mask
411 when SI1 =>
412 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
413 par_data <= X"000A"; -- TIMEOUT, DISCON
414 state_init <= WRITE_REG;
415 next_state <= SI2;
416 when SI2 =>
417 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
418 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
419 state_init <= WRITE_REG;
420 next_state <= SI3;
421 when SI3 =>
422 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
423 par_data <= X"0001"; -- OPEN
424 state_init <= WRITE_REG;
425 next_state <= SI4;
426 when SI4 =>
427 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
428 state_init <= READ_REG;
429 next_state <= SI5;
430 when SI5 =>
431 if (data_read (7 downto 0) = X"13") then -- is open?
432 state_init <= SI6;
433 else
434 state_init <= SI4;
435 end if;
436 when SI6 =>
437 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
438 par_data <= X"0002"; -- LISTEN
439 state_init <= WRITE_REG;
440 socket_cnt <= socket_cnt + 1;
441 if (socket_cnt = 7) then
442 socket_cnt <= "000";
443 next_state <= ESTABLISH; -- All Sockets open
444 else
445 next_state <= SI; -- Next Socket
446 end if;
447 -- End Socket Init
448
449 when ESTABLISH =>
450 socks_waiting <= '1';
451 socks_connected <= '0';
452 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
453 state_init <= READ_REG;
454 next_state <= EST1;
455 when EST1 =>
456-- led <= data_read (7 downto 0);
457-- led <= X"00";
458 case data_read (7 downto 0) is
459 when X"17" => -- established
460 if (socket_cnt = 7) then
461 socket_cnt <= "000";
462 busy <= '0';
463 state_init <= MAIN;
464 else
465 socket_cnt <= socket_cnt + 1;
466 state_init <= ESTABLISH;
467 end if;
468 when others =>
469 state_init <= ESTABLISH;
470 end case;
471
472 when CONFIG =>
473-- led <= X"F0";
474 new_config <= '1';
475 if (config_started = '1') then
476-- led <= X"0F";
477 new_config <= '0';
478 state_init <= MAIN;
479 end if;
480
481 -- main "loop"
482 when MAIN =>
483 socks_waiting <= '0';
484 socks_connected <= '1';
485
486 ps_do_phase_shift <= '0';
487 ps_reset <= '0';
488 if (trigger_stop = '1') then
489 s_trigger <= '0';
490 end if;
491 data_valid_ack <= '0';
492 state_init <= MAIN1;
493 data_valid_int <= data_valid;
494 when MAIN1 =>
495 if (chk_recv_cntr = 1000) then
496 chk_recv_cntr <= 0;
497 state_read_data <= RD_1;
498 state_init <= READ_DATA;
499 busy <= '1';
500 else
501 chk_recv_cntr <= chk_recv_cntr + 1;
502 state_init <= MAIN2;
503 end if;
504 when MAIN2 =>
505 busy <= '0';
506 if (data_valid = '1') then
507 data_valid_int <= '0';
508 busy <= '1';
509 local_write_length <= write_length;
510 local_ram_start_addr <= ram_start_addr;
511 local_ram_addr <= (others => '0');
512 local_write_header_flag <= write_header_flag;
513 local_write_end_flag <= write_end_flag;
514 local_fifo_channels <= fifo_channels;
515-- data_valid_ack <= '1';
516-- next_state <= MAIN;
517-- state_init <= WRITE_DATA;
518 state_init <= MAIN3;
519 else
520 state_init <= MAIN1;
521 end if;
522 when MAIN3 =>
523-- led <= local_ram_start_addr (7 downto 0);
524 data_valid_ack <= '1';
525 next_state <= MAIN;
526 state_init <= WRITE_DATA;
527
528
529 -- read data from socket 0
530 when READ_DATA =>
531 case state_read_data is
532 when RD_1 =>
533 par_addr <= W5300_S0_RX_RSR;
534 state_init <= READ_REG;
535 next_state <= READ_DATA;
536 state_read_data <= RD_2;
537 when RD_2 =>
538 socket_rx_received (31 downto 16) <= data_read;
539 par_addr <= W5300_S0_RX_RSR + X"2";
540 state_init <= READ_REG;
541 next_state <= READ_DATA;
542 state_read_data <= RD_3;
543 when RD_3 =>
544 socket_rx_received (15 downto 0) <= data_read;
545 state_read_data <= RD_4;
546 when RD_4 =>
547 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
548 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
549 state_read_data <= RD_5;
550 else
551 busy <= '0';
552 state_init <= MAIN;
553 end if;
554 when RD_5 =>
555 if (rx_packets_cnt > 0) then
556 rx_packets_cnt <= rx_packets_cnt - '1';
557 par_addr <= W5300_S0_RX_FIFOR;
558 state_init <= READ_REG;
559 next_state <= READ_DATA;
560 state_read_data <= RD_6;
561 else
562 state_read_data <= RD_END;
563 end if;
564 when RD_6 =>
565-- led <= data_read (15 downto 8);
566 -- read command
567 if (next_packet_data = '0') then
568 case data_read (15 downto 8) is
569
570 when CMD_START => -- all data will be send via socket 1..7
571 socket_send_mode <= '1';
572 state_read_data <= RD_5;
573 when CMD_STOP => -- all data will be send via socket 0
574 socket_send_mode <= '0';
575 state_read_data <= RD_5;
576
577
578 when CMD_TRIGGER =>
579 trigger_stop <= '1';
580 s_trigger <= '1';
581 state_read_data <= RD_5;
582 when CMD_DWRITE_RUN =>
583 dwrite_enable <= '1';
584 state_read_data <= RD_5;
585 when CMD_DWRITE_STOP =>
586 dwrite_enable <= '0';
587 state_read_data <= RD_5;
588 when CMD_SCLK_ON =>
589 sclk_enable <= '1';
590 state_read_data <= RD_5;
591 when CMD_SCLK_OFF =>
592 sclk_enable <= '0';
593 state_read_data <= RD_5;
594 when CMD_DENABLE =>
595 denable <= '1';
596 state_read_data <= RD_5;
597 when CMD_DDISABLE =>
598 denable <= '0';
599 state_read_data <= RD_5;
600 when CMD_TRIGGER_C =>
601 c_trigger_enable <= '1';
602 --trigger_stop <= '0';
603 --s_trigger <= '1';
604 state_read_data <= RD_5;
605 when CMD_TRIGGER_S =>
606 c_trigger_enable <= '0';
607 --trigger_stop <= '1';
608 state_read_data <= RD_5;
609 -- phase shift commands here:
610 when CMD_PS_DO =>
611 ps_do_phase_shift <= '1';
612 state_read_data <= RD_5;
613 when CMD_PS_DIRINC =>
614 ps_direction <= '1';
615 state_read_data <= RD_5;
616 when CMD_PS_RESET =>
617 ps_reset <= '1';
618 state_read_data <= RD_5;
619
620 when CMD_SRCLK_ON =>
621 srclk_enable <= '1';
622 state_read_data <= RD_5;
623 when CMD_SRCLK_OFF =>
624 srclk_enable <= '0';
625 state_read_data <= RD_5;
626
627 when CMD_TRIGGERS_ON =>
628 trigger_enable <= '1';
629 state_read_data <= RD_5;
630 when CMD_TRIGGERS_OFF =>
631 trigger_enable <= '0';
632 state_read_data <= RD_5;
633
634
635 when CMD_PS_DIRDEC =>
636 ps_direction <= '0';
637 state_read_data <= RD_5;
638 when CMD_WRITE =>
639 next_packet_data <= '1';
640 config_addr <= data_read (7 downto 0);
641 state_read_data <= RD_5;
642 when others =>
643 state_read_data <= RD_5;
644 end case;
645 -- read data
646 else
647 if (config_busy = '0') then
648 config_data <= data_read;
649 config_wr_en <= '1';
650 new_config_flag <= '1';
651 next_packet_data <= '0';
652 state_read_data <= RD_WAIT;
653 end if;
654 end if;
655 when RD_WAIT =>
656 if (config_rw_ack = '1') then
657 state_read_data <= RD_WAIT1;
658 end if;
659 when RD_WAIT1 =>
660 if (config_rw_ready = '1') then
661 config_data <= (others => 'Z');
662 config_wr_en <= '0';
663 state_read_data <= RD_5;
664 end if;
665 when RD_END =>
666 par_addr <= W5300_S0_CR;
667 par_data <= X"0040"; -- RECV
668 state_init <= WRITE_REG;
669 if (new_config_flag = '1') then
670 new_config_flag <= '0';
671 next_state <= CONFIG;
672 else
673 next_state <= MAIN;
674 end if;
675
676 end case; -- state_data_read
677
678
679
680 when WRITE_DATA =>
681 case state_write is
682 when WR_START =>
683 if (local_write_header_flag = '1') then
684 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
685 end if;
686 state_write <= WR_WAIT1;
687 when WR_WAIT1 =>
688 state_write <= WR_LENGTH;
689 when WR_LENGTH =>
690 if (local_write_header_flag = '1') then
691 if (socket_send_mode = '1') then -- send via all sockets
692 local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3);
693 if (socket_nr_counter < 7) then
694 socket_nr_counter <= socket_nr_counter + 1;
695 else
696 socket_nr_counter <= 1;
697 end if;
698 else -- only send via socket 0\
699 local_socket_nr <= "000";
700 end if;
701 end if;
702 next_state_tmp <= next_state;
703 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
704 data_cnt <= 0;
705 state_write <= WR_01;
706 -- Check FIFO Size
707 when WR_01 =>
708 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
709 state_init <= READ_REG;
710 next_state <= WRITE_DATA;
711 state_write <= WR_02;
712 when WR_02 =>
713 socket_tx_free (31 downto 16) <= data_read;
714 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
715 state_init <= READ_REG;
716 next_state <= WRITE_DATA;
717 state_write <= WR_03;
718 when WR_03 =>
719 socket_tx_free (15 downto 0) <= data_read;
720 state_write <= WR_04;
721 when WR_04 =>
722
723-- led <= socket_tx_free (15 downto 8);
724
725-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
726 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
727 state_write <= WR_01;
728 else
729 if (local_write_header_flag = '1') then
730 state_write <= WR_FIFO;
731 else
732 state_write <= WR_ADC;
733 end if;
734 end if;
735
736 -- Fill FIFO
737
738 -- Write Header
739 when WR_FIFO =>
740 ram_addr <= local_ram_start_addr + local_ram_addr;
741 state_write <= WR_FIFO1;
742 when WR_FIFO1 =>
743 data_cnt <= data_cnt + 1;
744 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
745 local_ram_addr <= local_ram_addr + 1;
746 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
747 local_ram_addr <= local_ram_addr + 2;
748 end if;
749 if (data_cnt = 9) then -- skip empty words
750 local_ram_addr <= local_ram_addr + 4;
751 end if;
752 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
753 ram_access <= '1';
754 state_init <= WRITE_REG;
755 next_state <= WRITE_DATA;
756 state_write <= WR_FIFO;
757 else
758 state_write <= WR_ADC;
759 end if;
760 -- End Write Header
761
762 -- Write ADC-Data
763 ---- Start...
764 when WR_ADC =>
765 adc_data_addr <= local_ram_start_addr + local_ram_addr;
766 drs_cnt <= 0;
767 channel_cnt <= 1;
768 data_cnt <= 0;
769 roi_max <= (others => '0');
770 data_end <= 3;
771 state_write <= WR_ADC1;
772
773 ---- Write Channel
774 when WR_ADC1 =>
775 -- read ROI and set end of Channel-Data
776 if (data_cnt = 3) then
777 data_end <= conv_integer (ram_data) + 3;
778 if (ram_data > roi_max) then
779 roi_max <= ram_data (10 downto 0);
780 end if;
781 end if;
782 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
783 state_write <= WR_ADC2;
784 when WR_ADC2 =>
785 if (data_cnt < data_end) then
786 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
787 ram_access <= '1';
788 state_init <= WRITE_REG;
789 next_state <= WRITE_DATA;
790 data_cnt <= data_cnt + 1;
791 state_write <= WR_ADC1;
792 else
793 -- Next DRS
794 if (drs_cnt < 3) then
795 drs_cnt <= drs_cnt + 1;
796 data_cnt <= 0;
797 data_end <= 3;
798 state_write <= WR_ADC1;
799 else
800 -- Next Channel
801 if (channel_cnt < local_fifo_channels) then
802 channel_cnt <= channel_cnt + 1;
803 roi_max <= (others => '0');
804 drs_cnt <= 0;
805 data_cnt <= 0;
806 data_end <= 3;
807 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
808 state_write <= WR_ADC1;
809 else
810 -- Ready
811 if (local_write_end_flag = '1') then
812 state_write <= WR_ENDFLAG;
813 else
814 state_write <= WR_05;
815 end if;
816 end if;
817 end if;
818 end if;
819 -- End Write ADC-Data
820
821 -- Write End Package Flag
822 when WR_ENDFLAG =>
823 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
824 state_write <= WR_ENDFLAG1;
825 when WR_ENDFLAG1 =>
826 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
827 ram_access <= '1';
828 state_init <= WRITE_REG;
829 next_state <= WRITE_DATA;
830 state_write <= WR_ENDFLAG2;
831 when WR_ENDFLAG2 =>
832 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
833 state_write <= WR_ENDFLAG3;
834 when WR_ENDFLAG3 =>
835 state_init <= WRITE_REG;
836 next_state <= WRITE_DATA;
837 state_write <= WR_05a;
838
839 -- End Write End Package Flag
840
841 -- Wait????
842 when WR_05a =>
843 if (wait_cntr < 10) then -- 3000 works???
844 wait_cntr <= wait_cntr + 1;
845 else
846 wait_cntr <= 0;
847 state_write <= WR_05b;
848 end if;
849 when WR_05b =>
850 state_write <= WR_05;
851
852 --Send FIFO
853 when WR_05 =>
854 ram_access <= '0';
855 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
856 par_data <= (0 => write_length_bytes (16), others => '0');
857 state_init <= WRITE_REG;
858 state_write <= WR_06;
859 when WR_06 =>
860 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
861 par_data <= write_length_bytes (15 downto 0);
862 state_init <= WRITE_REG;
863 state_write <= WR_07;
864 when WR_07 =>
865 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
866 par_data <= X"0020"; -- Send
867 state_init <= WRITE_REG;
868 state_write <= WR_08;
869 when others =>
870 state_init <= next_state_tmp;
871 state_write <= WR_START;
872 end case;
873 -- End WRITE_DATA
874
875 when READ_REG =>
876 case count is
877 when "000" =>
878 cs <= '0';
879 rd <= '0';
880 wr <= '1';
881 data <= (others => 'Z'); -- !!!!!!!!!!
882 count <= "001";
883 addr <= par_addr;
884 when "001" =>
885 count <= "010";
886 when "010" =>
887 count <= "100";
888 when "100" =>
889 data_read <= data;
890 count <= "110";
891 when "110" =>
892 count <= "111";
893 when "111" =>
894 cs <= '1';
895 rd <= '1';
896 count <= "000";
897 state_init <= next_state;
898 when others =>
899 null;
900 end case;
901
902 when WRITE_REG =>
903 case count is
904 when "000" =>
905 cs <= '0';
906 wr <= '0';
907 rd <= '1';
908 addr <= par_addr;
909 if (ram_access = '1') then
910 data <= ram_data;
911 else
912 data <= par_data;
913 end if;
914 count <= "100";
915 when "100" =>
916 count <= "101";
917 when "101" =>
918 count <= "110";
919 when "110" =>
920 cs <= '1';
921 wr <= '1';
922 state_init <= next_state;
923 count <= "000";
924 when others =>
925 null;
926 end case;
927
928 when others =>
929 null;
930 end case;
931 end if; -- int_flag = '0'
932
933 end if; -- rising_edge (clk)
934
935 end process w5300_init_proc;
936
937end Behavioral;
938
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