source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd@ 10074

Last change on this file since 10074 was 10074, checked in by neise, 12 years ago
added LED controller
File size: 29.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 s_trigger : OUT std_logic := '0';
56 new_config : OUT std_logic := '0';
57 config_started : in std_logic;
58 config_addr : out std_logic_vector (7 downto 0);
59 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
60 config_wr_en : out std_logic := '0';
61 config_rd_en : out std_logic := '0';
62 -- --
63 config_rw_ack, config_rw_ready : in std_logic;
64 -- --
65 config_busy : in std_logic;
66
67
68
69 denable : out std_logic := '0'; -- default domino wave off
70 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
71 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
72 ps_direction : out std_logic := '1'; -- default phase shift upwards
73 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
74 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
75
76 srclk_enable : out std_logic := '1'; -- default SRCLK on.
77
78 socks_waiting : out std_logic;
79 socks_connected: out std_logic
80 );
81
82-- Declarations
83
84END w5300_modul ;
85
86architecture Behavioral of w5300_modul is
87
88type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
89 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
90 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
91type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
92 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
93type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
94type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
95type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
96
97signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
98
99signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
100signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
101signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
102signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
103
104signal state_init, next_state , next_state_tmp : state_init_type := RESET;
105signal count : std_logic_vector (2 downto 0) := "000";
106signal state_write : state_write_type := WR_START;
107signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
108signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
109signal state_read_data : state_read_data_type := RD_1;
110
111signal interrupt_ignore : std_logic := '1';
112signal int_flag : std_logic := '0';
113signal ram_access : std_logic := '0';
114
115signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
116signal data_cnt : integer := 0;
117signal drs_cnt : integer :=0;
118signal channel_cnt : integer range 0 to 9 :=0;
119signal socket_cnt : std_logic_vector (2 downto 0) := "000";
120signal roi_max : std_logic_vector (10 downto 0);
121signal data_end : integer := 0;
122
123signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
124signal write_length_bytes : std_logic_vector (16 downto 0);
125
126signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
127signal chk_recv_cntr : integer range 0 to 10000 := 0;
128
129-- --
130signal wait_cntr : integer range 0 to 10000 := 0;
131-- --
132
133signal rx_packets_cnt : std_logic_vector (15 downto 0);
134signal next_packet_data : std_logic := '0';
135signal new_config_flag : std_logic := '0';
136
137signal trigger_stop : std_logic := '1';
138
139signal local_write_length : std_logic_vector (16 DOWNTO 0);
140signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
141signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
142signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
143signal local_write_header_flag, local_write_end_flag : std_logic;
144signal local_fifo_channels : std_logic_vector (3 downto 0);
145
146signal data_valid_int : std_logic := '0';
147
148-- only for debugging
149--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
150--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
151
152
153begin
154
155 --synthesis translate_off
156 RST_TIME <= X"00120";
157 --synthesis translate_on
158
159
160 w5300_init_proc : process (clk, int)
161 begin
162
163 if rising_edge (clk) then
164
165 -- Interrupt low
166 if (int = '0') and (interrupt_ignore = '0') then
167 case state_interrupt_1 is
168 when IR1_01 =>
169 int_flag <= '1';
170 busy <= '1';
171 state_interrupt_1 <= IR1_02;
172 when IR1_02 =>
173 state_interrupt_1 <= IR1_03;
174 when IR1_03 =>
175 state_init <= INTERRUPT;
176 socket_cnt <= "000";
177 ram_access <= '0';
178 zaehler <= X"00000";
179 count <= "000";
180 int_flag <= '0';
181 interrupt_ignore <= '1';
182 state_interrupt_1 <= IR1_04;
183 when others =>
184 null;
185 end case;
186 end if; -- int = '0'
187
188 if int_flag = '0' then
189 case state_init is
190 -- Interrupt
191 when INTERRUPT =>
192 case state_interrupt_2 is
193 when IR2_01 =>
194 par_addr <= W5300_IR;
195 state_init <= READ_REG;
196 next_state <= INTERRUPT;
197 state_interrupt_2 <= IR2_02;
198 when IR2_02 =>
199 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
200 state_interrupt_2 <= IR2_03;
201 else
202 socket_cnt <= socket_cnt + 1;
203 if (socket_cnt = 7) then
204 state_interrupt_2 <= IR2_06;
205 else
206 state_interrupt_2 <= IR2_02;
207 end if;
208 end if;
209 when IR2_03 =>
210 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
211 state_init <= READ_REG;
212 next_state <= INTERRUPT;
213 state_interrupt_2 <= IR2_04;
214 when IR2_04 =>
215 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
216 par_data <= data_read; -- clear Interrupts
217 state_init <= WRITE_REG;
218 next_state <= INTERRUPT;
219 state_interrupt_2 <= IR2_05;
220 when IR2_05 =>
221 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
222 par_data <= X"0010"; -- CLOSE
223 state_init <= WRITE_REG;
224 next_state <= INTERRUPT;
225 socket_cnt <= socket_cnt + 1;
226 if (socket_cnt = 7) then
227 state_interrupt_2 <= IR2_06;
228 else
229 state_interrupt_2 <= IR2_01;
230 end if;
231
232 when IR2_06 =>
233 state_interrupt_1 <= IR1_01;
234 state_interrupt_2 <= IR2_01;
235 socket_cnt <= "000";
236 state_init <= RESET;
237 end case;
238
239 -- reset W5300
240 when RESET =>
241 busy <= '1';
242 zaehler <= zaehler + 1;
243 socks_waiting <= '0';
244 socks_connected <= '0';
245 wiz_reset <= '0';
246-- led <= X"FF";
247 if (zaehler >= X"00064") then -- wait 2µs
248 wiz_reset <= '1';
249 end if;
250 if (zaehler = RST_TIME) then -- wait 10ms
251 zaehler <= X"00000";
252 socket_cnt <= "000";
253 count <= "000";
254 ram_access <= '0';
255 interrupt_ignore <= '0';
256 rd <= '1';
257 wr <= '1';
258 cs <= '1';
259 state_write <= WR_START;
260 state_init <= INIT;
261 end if;
262
263 -- Init
264 when INIT =>
265 par_addr <= W5300_MR;
266 par_data <= X"0000";
267 state_init <= WRITE_REG;
268 next_state <= IM;
269
270 -- Interrupt Mask
271 when IM =>
272 par_addr <= W5300_IMR;
273 par_data <= X"00FF"; -- S0-S7 Interrupts
274 state_init <= WRITE_REG;
275 next_state <= MT;
276
277 -- Memory Type
278 when MT =>
279 par_addr <= W5300_MTYPER;
280 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
281 state_init <= WRITE_REG;
282 next_state <= STX;
283
284 -- Socket TX Memory Size
285 when STX =>
286 par_data <= X"0F0F"; -- 15K TX
287
288 par_addr <= W5300_TMS01R;
289 state_init <=WRITE_REG;
290 next_state <= STX1;
291 when STX1 =>
292 par_addr <= W5300_TMS23R;
293 state_init <=WRITE_REG;
294 next_state <= STX2;
295 when STX2 =>
296 par_addr <= W5300_TMS45R;
297 state_init <=WRITE_REG;
298 next_state <= STX3;
299 when STX3 =>
300 par_addr <= W5300_TMS67R;
301 state_init <=WRITE_REG;
302 next_state <= SRX;
303
304 -- Socket RX Memory Size
305 when SRX =>
306 par_data <= X"0101"; -- 1K RX
307
308 par_addr <= W5300_RMS01R;
309 state_init <=WRITE_REG;
310 next_state <= SRX1;
311 when SRX1 =>
312 par_addr <= W5300_RMS23R;
313 state_init <=WRITE_REG;
314 next_state <= SRX2;
315 when SRX2 =>
316 par_addr <= W5300_RMS45R;
317 state_init <=WRITE_REG;
318 next_state <= SRX3;
319 when SRX3 =>
320 par_addr <= W5300_RMS67R;
321 state_init <=WRITE_REG;
322 next_state <= MAC;
323
324 -- MAC
325 when MAC =>
326 par_addr <= W5300_SHAR;
327 par_data <= MAC_ADDRESS (0);
328 state_init <= WRITE_REG;
329 next_state <= MAC1;
330 when MAC1 =>
331 par_addr <= W5300_SHAR + 2;
332 par_data <= MAC_ADDRESS (1);
333 state_init <= WRITE_REG;
334 next_state <= MAC2;
335 when MAC2 =>
336 par_addr <= W5300_SHAR + 4;
337 par_data <= MAC_ADDRESS (2);
338 state_init <= WRITE_REG;
339 next_state <= GW;
340
341 -- Gateway
342 when GW =>
343 par_addr <= W5300_GAR;
344 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
345 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
346 state_init <= WRITE_REG;
347 next_state <= GW1;
348 when GW1 =>
349 par_addr <= W5300_GAR + 2;
350 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
351 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
352 state_init <= WRITE_REG;
353 next_state <= SNM;
354
355 -- Subnet Mask
356 when SNM =>
357 par_addr <= W5300_SUBR;
358 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
359 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
360 state_init <= WRITE_REG;
361 next_state <= SNM1;
362 when SNM1 =>
363 par_addr <= W5300_SUBR + 2;
364 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
365 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
366 state_init <= WRITE_REG;
367 next_state <= IP;
368 -- Own IP-Address
369 when IP =>
370 par_addr <= W5300_SIPR;
371 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
372 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
373 state_init <= WRITE_REG;
374 next_state <= IP1;
375 when IP1 =>
376 par_addr <= W5300_SIPR + 2;
377 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
378 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
379 state_init <= WRITE_REG;
380 next_state <= SI;
381-- when TIMEOUT =>
382-- par_addr <= W5300_RTR;
383-- par_data <= X"07D0"; -- 0x07D0 = 200ms
384-- state_init <= WRITE_REG;
385-- next_state <= RETRY;
386-- when RETRY =>
387-- par_addr <= W5300_RCR;
388-- par_data <= X"0008";
389-- state_init <= WRITE_REG;
390-- next_state <= SI;
391--
392
393 -- Socket Init
394 when SI =>
395 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
396 par_data <= X"0101"; -- ALIGN, TCP
397 state_init <= WRITE_REG;
398 next_state <= SI1;
399 -- Sx Interrupt Mask
400 when SI1 =>
401 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
402 par_data <= X"000A"; -- TIMEOUT, DISCON
403 state_init <= WRITE_REG;
404 next_state <= SI2;
405 when SI2 =>
406 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
407 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
408 state_init <= WRITE_REG;
409 next_state <= SI3;
410 when SI3 =>
411 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
412 par_data <= X"0001"; -- OPEN
413 state_init <= WRITE_REG;
414 next_state <= SI4;
415 when SI4 =>
416 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
417 state_init <= READ_REG;
418 next_state <= SI5;
419 when SI5 =>
420 if (data_read (7 downto 0) = X"13") then -- is open?
421 state_init <= SI6;
422 else
423 state_init <= SI4;
424 end if;
425 when SI6 =>
426 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
427 par_data <= X"0002"; -- LISTEN
428 state_init <= WRITE_REG;
429 socket_cnt <= socket_cnt + 1;
430 if (socket_cnt = 7) then
431 socket_cnt <= "000";
432 next_state <= ESTABLISH; -- All Sockets open
433 else
434 next_state <= SI; -- Next Socket
435 end if;
436 -- End Socket Init
437
438 when ESTABLISH =>
439 socks_waiting <= '1';
440 socks_connected <= '0';
441 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
442 state_init <= READ_REG;
443 next_state <= EST1;
444 when EST1 =>
445-- led <= data_read (7 downto 0);
446-- led <= X"00";
447 case data_read (7 downto 0) is
448 when X"17" => -- established
449 if (socket_cnt = 7) then
450 socket_cnt <= "000";
451 busy <= '0';
452 state_init <= MAIN;
453 else
454 socket_cnt <= socket_cnt + 1;
455 state_init <= ESTABLISH;
456 end if;
457 when others =>
458 state_init <= ESTABLISH;
459 end case;
460
461 when CONFIG =>
462-- led <= X"F0";
463 new_config <= '1';
464 if (config_started = '1') then
465-- led <= X"0F";
466 new_config <= '0';
467 state_init <= MAIN;
468 end if;
469
470 -- main "loop"
471 when MAIN =>
472 socks_waiting <= '0';
473 socks_connected <= '1';
474
475 ps_do_phase_shift <= '0';
476 ps_reset <= '0';
477 if (trigger_stop = '1') then
478 s_trigger <= '0';
479 end if;
480 data_valid_ack <= '0';
481 state_init <= MAIN1;
482 data_valid_int <= data_valid;
483 when MAIN1 =>
484 if (chk_recv_cntr = 1000) then
485 chk_recv_cntr <= 0;
486 state_read_data <= RD_1;
487 state_init <= READ_DATA;
488 busy <= '1';
489 else
490 chk_recv_cntr <= chk_recv_cntr + 1;
491 state_init <= MAIN2;
492 end if;
493 when MAIN2 =>
494 busy <= '0';
495 if (data_valid = '1') then
496 data_valid_int <= '0';
497 busy <= '1';
498 local_write_length <= write_length;
499 local_ram_start_addr <= ram_start_addr;
500 local_ram_addr <= (others => '0');
501 local_write_header_flag <= write_header_flag;
502 local_write_end_flag <= write_end_flag;
503 local_fifo_channels <= fifo_channels;
504-- data_valid_ack <= '1';
505-- next_state <= MAIN;
506-- state_init <= WRITE_DATA;
507 state_init <= MAIN3;
508 else
509 state_init <= MAIN1;
510 end if;
511 when MAIN3 =>
512-- led <= local_ram_start_addr (7 downto 0);
513 data_valid_ack <= '1';
514 next_state <= MAIN;
515 state_init <= WRITE_DATA;
516
517
518 -- read data from socket 0
519 when READ_DATA =>
520 case state_read_data is
521 when RD_1 =>
522 par_addr <= W5300_S0_RX_RSR;
523 state_init <= READ_REG;
524 next_state <= READ_DATA;
525 state_read_data <= RD_2;
526 when RD_2 =>
527 socket_rx_received (31 downto 16) <= data_read;
528 par_addr <= W5300_S0_RX_RSR + X"2";
529 state_init <= READ_REG;
530 next_state <= READ_DATA;
531 state_read_data <= RD_3;
532 when RD_3 =>
533 socket_rx_received (15 downto 0) <= data_read;
534 state_read_data <= RD_4;
535 when RD_4 =>
536 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
537 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
538 state_read_data <= RD_5;
539 else
540 busy <= '0';
541 state_init <= MAIN;
542 end if;
543 when RD_5 =>
544 if (rx_packets_cnt > 0) then
545 rx_packets_cnt <= rx_packets_cnt - '1';
546 par_addr <= W5300_S0_RX_FIFOR;
547 state_init <= READ_REG;
548 next_state <= READ_DATA;
549 state_read_data <= RD_6;
550 else
551 state_read_data <= RD_END;
552 end if;
553 when RD_6 =>
554-- led <= data_read (15 downto 8);
555 -- read command
556 if (next_packet_data = '0') then
557 case data_read (15 downto 8) is
558 when CMD_TRIGGER =>
559 trigger_stop <= '1';
560 s_trigger <= '1';
561 state_read_data <= RD_5;
562 when CMD_DWRITE_RUN =>
563 dwrite_enable <= '1';
564 state_read_data <= RD_5;
565 when CMD_DWRITE_STOP =>
566 dwrite_enable <= '0';
567 state_read_data <= RD_5;
568 when CMD_SCLK_ON =>
569 sclk_enable <= '1';
570 state_read_data <= RD_5;
571 when CMD_SCLK_OFF =>
572 sclk_enable <= '0';
573 state_read_data <= RD_5;
574 when CMD_DENABLE =>
575 denable <= '1';
576 state_read_data <= RD_5;
577 when CMD_DDISABLE =>
578 denable <= '0';
579 state_read_data <= RD_5;
580 when CMD_TRIGGER_C =>
581 trigger_stop <= '0';
582 s_trigger <= '1';
583 state_read_data <= RD_5;
584 when CMD_TRIGGER_S =>
585 trigger_stop <= '1';
586 state_read_data <= RD_5;
587 -- phase shift commands here:
588 when CMD_PS_DO =>
589 ps_do_phase_shift <= '1';
590 state_read_data <= RD_5;
591 when CMD_PS_DIRINC =>
592 ps_direction <= '1';
593 state_read_data <= RD_5;
594 when CMD_PS_RESET =>
595 ps_reset <= '1';
596 state_read_data <= RD_5;
597 when CMD_SRCLK_ON =>
598 srclk_enable <= '1';
599 state_read_data <= RD_5;
600 when CMD_SRCLK_OFF =>
601 srclk_enable <= '0';
602 state_read_data <= RD_5;
603 when CMD_PS_DIRDEC =>
604 ps_direction <= '0';
605 state_read_data <= RD_5;
606 when CMD_WRITE =>
607 next_packet_data <= '1';
608 config_addr <= data_read (7 downto 0);
609 state_read_data <= RD_5;
610 when others =>
611 state_read_data <= RD_5;
612 end case;
613 -- read data
614 else
615 if (config_busy = '0') then
616 config_data <= data_read;
617 config_wr_en <= '1';
618 new_config_flag <= '1';
619 next_packet_data <= '0';
620 state_read_data <= RD_WAIT;
621 end if;
622 end if;
623 when RD_WAIT =>
624 if (config_rw_ack = '1') then
625 state_read_data <= RD_WAIT1;
626 end if;
627 when RD_WAIT1 =>
628 if (config_rw_ready = '1') then
629 config_data <= (others => 'Z');
630 config_wr_en <= '0';
631 state_read_data <= RD_5;
632 end if;
633 when RD_END =>
634 par_addr <= W5300_S0_CR;
635 par_data <= X"0040"; -- RECV
636 state_init <= WRITE_REG;
637 if (new_config_flag = '1') then
638 new_config_flag <= '0';
639 next_state <= CONFIG;
640 else
641 next_state <= MAIN;
642 end if;
643
644 end case; -- state_data_read
645
646
647
648 when WRITE_DATA =>
649 case state_write is
650 when WR_START =>
651 if (local_write_header_flag = '1') then
652 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
653 end if;
654 state_write <= WR_WAIT1;
655 when WR_WAIT1 =>
656 state_write <= WR_LENGTH;
657 when WR_LENGTH =>
658 if (local_write_header_flag = '1') then
659 local_socket_nr <= ram_data (2 downto 0);
660-- local_socket_nr <= "000";
661 end if;
662 next_state_tmp <= next_state;
663 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
664 data_cnt <= 0;
665 state_write <= WR_01;
666 -- Check FIFO Size
667 when WR_01 =>
668 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
669 state_init <= READ_REG;
670 next_state <= WRITE_DATA;
671 state_write <= WR_02;
672 when WR_02 =>
673 socket_tx_free (31 downto 16) <= data_read;
674 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
675 state_init <= READ_REG;
676 next_state <= WRITE_DATA;
677 state_write <= WR_03;
678 when WR_03 =>
679 socket_tx_free (15 downto 0) <= data_read;
680 state_write <= WR_04;
681 when WR_04 =>
682
683-- led <= socket_tx_free (15 downto 8);
684
685-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
686 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
687 state_write <= WR_01;
688 else
689 if (local_write_header_flag = '1') then
690 state_write <= WR_FIFO;
691 else
692 state_write <= WR_ADC;
693 end if;
694 end if;
695
696 -- Fill FIFO
697
698 -- Write Header
699 when WR_FIFO =>
700 ram_addr <= local_ram_start_addr + local_ram_addr;
701 state_write <= WR_FIFO1;
702 when WR_FIFO1 =>
703 data_cnt <= data_cnt + 1;
704 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
705 local_ram_addr <= local_ram_addr + 1;
706 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
707 local_ram_addr <= local_ram_addr + 2;
708 end if;
709 if (data_cnt = 9) then -- skip empty words
710 local_ram_addr <= local_ram_addr + 4;
711 end if;
712 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
713 ram_access <= '1';
714 state_init <= WRITE_REG;
715 next_state <= WRITE_DATA;
716 state_write <= WR_FIFO;
717 else
718 state_write <= WR_ADC;
719 end if;
720 -- End Write Header
721
722 -- Write ADC-Data
723 ---- Start...
724 when WR_ADC =>
725 adc_data_addr <= local_ram_start_addr + local_ram_addr;
726 drs_cnt <= 0;
727 channel_cnt <= 1;
728 data_cnt <= 0;
729 roi_max <= (others => '0');
730 data_end <= 3;
731 state_write <= WR_ADC1;
732
733 ---- Write Channel
734 when WR_ADC1 =>
735 -- read ROI and set end of Channel-Data
736 if (data_cnt = 3) then
737 data_end <= conv_integer (ram_data) + 3;
738 if (ram_data > roi_max) then
739 roi_max <= ram_data (10 downto 0);
740 end if;
741 end if;
742 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
743 state_write <= WR_ADC2;
744 when WR_ADC2 =>
745 if (data_cnt < data_end) then
746 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
747 ram_access <= '1';
748 state_init <= WRITE_REG;
749 next_state <= WRITE_DATA;
750 data_cnt <= data_cnt + 1;
751 state_write <= WR_ADC1;
752 else
753 -- Next DRS
754 if (drs_cnt < 3) then
755 drs_cnt <= drs_cnt + 1;
756 data_cnt <= 0;
757 data_end <= 3;
758 state_write <= WR_ADC1;
759 else
760 -- Next Channel
761 if (channel_cnt < local_fifo_channels) then
762 channel_cnt <= channel_cnt + 1;
763 roi_max <= (others => '0');
764 drs_cnt <= 0;
765 data_cnt <= 0;
766 data_end <= 3;
767 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
768 state_write <= WR_ADC1;
769 else
770 -- Ready
771 if (local_write_end_flag = '1') then
772 state_write <= WR_ENDFLAG;
773 else
774 state_write <= WR_05;
775 end if;
776 end if;
777 end if;
778 end if;
779 -- End Write ADC-Data
780
781 -- Write End Package Flag
782 when WR_ENDFLAG =>
783 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
784 state_write <= WR_ENDFLAG1;
785 when WR_ENDFLAG1 =>
786 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
787 ram_access <= '1';
788 state_init <= WRITE_REG;
789 next_state <= WRITE_DATA;
790 state_write <= WR_ENDFLAG2;
791 when WR_ENDFLAG2 =>
792 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
793 state_write <= WR_ENDFLAG3;
794 when WR_ENDFLAG3 =>
795 state_init <= WRITE_REG;
796 next_state <= WRITE_DATA;
797 state_write <= WR_05a;
798
799 -- End Write End Package Flag
800
801 -- Wait????
802 when WR_05a =>
803 if (wait_cntr < 10) then -- 3000 works???
804 wait_cntr <= wait_cntr + 1;
805 else
806 wait_cntr <= 0;
807 state_write <= WR_05b;
808 end if;
809 when WR_05b =>
810 state_write <= WR_05;
811
812 --Send FIFO
813 when WR_05 =>
814 ram_access <= '0';
815 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
816 par_data <= (0 => write_length_bytes (16), others => '0');
817 state_init <= WRITE_REG;
818 state_write <= WR_06;
819 when WR_06 =>
820 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
821 par_data <= write_length_bytes (15 downto 0);
822 state_init <= WRITE_REG;
823 state_write <= WR_07;
824 when WR_07 =>
825 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
826 par_data <= X"0020"; -- Send
827 state_init <= WRITE_REG;
828 state_write <= WR_08;
829 when others =>
830 state_init <= next_state_tmp;
831 state_write <= WR_START;
832 end case;
833 -- End WRITE_DATA
834
835 when READ_REG =>
836 case count is
837 when "000" =>
838 cs <= '0';
839 rd <= '0';
840 wr <= '1';
841 data <= (others => 'Z'); -- !!!!!!!!!!
842 count <= "001";
843 addr <= par_addr;
844 when "001" =>
845 count <= "010";
846 when "010" =>
847 count <= "100";
848 when "100" =>
849 data_read <= data;
850 count <= "110";
851 when "110" =>
852 count <= "111";
853 when "111" =>
854 cs <= '1';
855 rd <= '1';
856 count <= "000";
857 state_init <= next_state;
858 when others =>
859 null;
860 end case;
861
862 when WRITE_REG =>
863 case count is
864 when "000" =>
865 cs <= '0';
866 wr <= '0';
867 rd <= '1';
868 addr <= par_addr;
869 if (ram_access = '1') then
870 data <= ram_data;
871 else
872 data <= par_data;
873 end if;
874 count <= "100";
875 when "100" =>
876 count <= "101";
877 when "101" =>
878 count <= "110";
879 when "110" =>
880 cs <= '1';
881 wr <= '1';
882 state_init <= next_state;
883 count <= "000";
884 when others =>
885 null;
886 end case;
887
888 when others =>
889 null;
890 end case;
891 end if; -- int_flag = '0'
892
893 end if; -- rising_edge (clk)
894
895 end process w5300_init_proc;
896
897end Behavioral;
898
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