source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd@ 10076

Last change on this file since 10076 was 10076, checked in by neise, 12 years ago
different socket modes - untested
File size: 30.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 s_trigger : OUT std_logic := '0';
56 new_config : OUT std_logic := '0';
57 config_started : in std_logic;
58 config_addr : out std_logic_vector (7 downto 0);
59 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
60 config_wr_en : out std_logic := '0';
61 config_rd_en : out std_logic := '0';
62 -- --
63 config_rw_ack, config_rw_ready : in std_logic;
64 -- --
65 config_busy : in std_logic;
66
67
68
69 denable : out std_logic := '0'; -- default domino wave off
70 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
71 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
72 ps_direction : out std_logic := '1'; -- default phase shift upwards
73 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
74 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
75
76 srclk_enable : out std_logic := '1'; -- default SRCLK on.
77
78 socks_waiting : out std_logic;
79 socks_connected: out std_logic
80 );
81
82-- Declarations
83
84END w5300_modul ;
85
86architecture Behavioral of w5300_modul is
87
88type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
89 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
90 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
91type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
92 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
93type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
94type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
95type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
96
97signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
98
99signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
100signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
101signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
102signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
103
104signal state_init, next_state , next_state_tmp : state_init_type := RESET;
105signal count : std_logic_vector (2 downto 0) := "000";
106signal state_write : state_write_type := WR_START;
107signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
108signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
109signal state_read_data : state_read_data_type := RD_1;
110
111signal interrupt_ignore : std_logic := '1';
112signal int_flag : std_logic := '0';
113signal ram_access : std_logic := '0';
114
115signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
116signal data_cnt : integer := 0;
117signal drs_cnt : integer :=0;
118signal channel_cnt : integer range 0 to 9 :=0;
119signal socket_cnt : std_logic_vector (2 downto 0) := "000";
120signal roi_max : std_logic_vector (10 downto 0);
121signal data_end : integer := 0;
122
123signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
124signal write_length_bytes : std_logic_vector (16 downto 0);
125
126signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
127signal chk_recv_cntr : integer range 0 to 10000 := 0;
128
129-- --
130signal wait_cntr : integer range 0 to 10000 := 0;
131-- --
132
133signal rx_packets_cnt : std_logic_vector (15 downto 0);
134signal next_packet_data : std_logic := '0';
135signal new_config_flag : std_logic := '0';
136
137signal trigger_stop : std_logic := '1';
138
139signal local_write_length : std_logic_vector (16 DOWNTO 0);
140signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
141signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
142signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
143signal local_write_header_flag, local_write_end_flag : std_logic;
144signal local_fifo_channels : std_logic_vector (3 downto 0);
145
146signal data_valid_int : std_logic := '0';
147
148-- only for debugging
149--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
150--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
151
152
153-- signals for different socket modes: DN 04.01.11
154signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
155signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
156
157begin
158
159 --synthesis translate_off
160 RST_TIME <= X"00120";
161 --synthesis translate_on
162
163
164 w5300_init_proc : process (clk, int)
165 begin
166
167 if rising_edge (clk) then
168
169 -- Interrupt low
170 if (int = '0') and (interrupt_ignore = '0') then
171 case state_interrupt_1 is
172 when IR1_01 =>
173 int_flag <= '1';
174 busy <= '1';
175 state_interrupt_1 <= IR1_02;
176 when IR1_02 =>
177 state_interrupt_1 <= IR1_03;
178 when IR1_03 =>
179 state_init <= INTERRUPT;
180 socket_cnt <= "000";
181 ram_access <= '0';
182 zaehler <= X"00000";
183 count <= "000";
184 int_flag <= '0';
185 interrupt_ignore <= '1';
186 state_interrupt_1 <= IR1_04;
187 when others =>
188 null;
189 end case;
190 end if; -- int = '0'
191
192 if int_flag = '0' then
193 case state_init is
194 -- Interrupt
195 when INTERRUPT =>
196 case state_interrupt_2 is
197 when IR2_01 =>
198 par_addr <= W5300_IR;
199 state_init <= READ_REG;
200 next_state <= INTERRUPT;
201 state_interrupt_2 <= IR2_02;
202 when IR2_02 =>
203 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
204 state_interrupt_2 <= IR2_03;
205 else
206 socket_cnt <= socket_cnt + 1;
207 if (socket_cnt = 7) then
208 state_interrupt_2 <= IR2_06;
209 else
210 state_interrupt_2 <= IR2_02;
211 end if;
212 end if;
213 when IR2_03 =>
214 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
215 state_init <= READ_REG;
216 next_state <= INTERRUPT;
217 state_interrupt_2 <= IR2_04;
218 when IR2_04 =>
219 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
220 par_data <= data_read; -- clear Interrupts
221 state_init <= WRITE_REG;
222 next_state <= INTERRUPT;
223 state_interrupt_2 <= IR2_05;
224 when IR2_05 =>
225 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
226 par_data <= X"0010"; -- CLOSE
227 state_init <= WRITE_REG;
228 next_state <= INTERRUPT;
229 socket_cnt <= socket_cnt + 1;
230 if (socket_cnt = 7) then
231 state_interrupt_2 <= IR2_06;
232 else
233 state_interrupt_2 <= IR2_01;
234 end if;
235
236 when IR2_06 =>
237 state_interrupt_1 <= IR1_01;
238 state_interrupt_2 <= IR2_01;
239 socket_cnt <= "000";
240 state_init <= RESET;
241 end case;
242
243 -- reset W5300
244 when RESET =>
245 busy <= '1';
246 zaehler <= zaehler + 1;
247 socks_waiting <= '0';
248 socks_connected <= '0';
249 wiz_reset <= '0';
250-- led <= X"FF";
251 if (zaehler >= X"00064") then -- wait 2µs
252 wiz_reset <= '1';
253 end if;
254 if (zaehler = RST_TIME) then -- wait 10ms
255 zaehler <= X"00000";
256 socket_cnt <= "000";
257 count <= "000";
258 ram_access <= '0';
259 interrupt_ignore <= '0';
260 rd <= '1';
261 wr <= '1';
262 cs <= '1';
263 state_write <= WR_START;
264 state_init <= INIT;
265 end if;
266
267 -- Init
268 when INIT =>
269 par_addr <= W5300_MR;
270 par_data <= X"0000";
271 state_init <= WRITE_REG;
272 next_state <= IM;
273
274 -- Interrupt Mask
275 when IM =>
276 par_addr <= W5300_IMR;
277 par_data <= X"00FF"; -- S0-S7 Interrupts
278 state_init <= WRITE_REG;
279 next_state <= MT;
280
281 -- Memory Type
282 when MT =>
283 par_addr <= W5300_MTYPER;
284 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
285 state_init <= WRITE_REG;
286 next_state <= STX;
287
288 -- Socket TX Memory Size
289 when STX =>
290 par_data <= X"0F0F"; -- 15K TX
291
292 par_addr <= W5300_TMS01R;
293 state_init <=WRITE_REG;
294 next_state <= STX1;
295 when STX1 =>
296 par_addr <= W5300_TMS23R;
297 state_init <=WRITE_REG;
298 next_state <= STX2;
299 when STX2 =>
300 par_addr <= W5300_TMS45R;
301 state_init <=WRITE_REG;
302 next_state <= STX3;
303 when STX3 =>
304 par_addr <= W5300_TMS67R;
305 state_init <=WRITE_REG;
306 next_state <= SRX;
307
308 -- Socket RX Memory Size
309 when SRX =>
310 par_data <= X"0101"; -- 1K RX
311
312 par_addr <= W5300_RMS01R;
313 state_init <=WRITE_REG;
314 next_state <= SRX1;
315 when SRX1 =>
316 par_addr <= W5300_RMS23R;
317 state_init <=WRITE_REG;
318 next_state <= SRX2;
319 when SRX2 =>
320 par_addr <= W5300_RMS45R;
321 state_init <=WRITE_REG;
322 next_state <= SRX3;
323 when SRX3 =>
324 par_addr <= W5300_RMS67R;
325 state_init <=WRITE_REG;
326 next_state <= MAC;
327
328 -- MAC
329 when MAC =>
330 par_addr <= W5300_SHAR;
331 par_data <= MAC_ADDRESS (0);
332 state_init <= WRITE_REG;
333 next_state <= MAC1;
334 when MAC1 =>
335 par_addr <= W5300_SHAR + 2;
336 par_data <= MAC_ADDRESS (1);
337 state_init <= WRITE_REG;
338 next_state <= MAC2;
339 when MAC2 =>
340 par_addr <= W5300_SHAR + 4;
341 par_data <= MAC_ADDRESS (2);
342 state_init <= WRITE_REG;
343 next_state <= GW;
344
345 -- Gateway
346 when GW =>
347 par_addr <= W5300_GAR;
348 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
349 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
350 state_init <= WRITE_REG;
351 next_state <= GW1;
352 when GW1 =>
353 par_addr <= W5300_GAR + 2;
354 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
355 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
356 state_init <= WRITE_REG;
357 next_state <= SNM;
358
359 -- Subnet Mask
360 when SNM =>
361 par_addr <= W5300_SUBR;
362 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
363 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
364 state_init <= WRITE_REG;
365 next_state <= SNM1;
366 when SNM1 =>
367 par_addr <= W5300_SUBR + 2;
368 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
369 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
370 state_init <= WRITE_REG;
371 next_state <= IP;
372 -- Own IP-Address
373 when IP =>
374 par_addr <= W5300_SIPR;
375 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
376 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
377 state_init <= WRITE_REG;
378 next_state <= IP1;
379 when IP1 =>
380 par_addr <= W5300_SIPR + 2;
381 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
382 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
383 state_init <= WRITE_REG;
384 next_state <= SI;
385-- when TIMEOUT =>
386-- par_addr <= W5300_RTR;
387-- par_data <= X"07D0"; -- 0x07D0 = 200ms
388-- state_init <= WRITE_REG;
389-- next_state <= RETRY;
390-- when RETRY =>
391-- par_addr <= W5300_RCR;
392-- par_data <= X"0008";
393-- state_init <= WRITE_REG;
394-- next_state <= SI;
395--
396
397 -- Socket Init
398 when SI =>
399 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
400 par_data <= X"0101"; -- ALIGN, TCP
401 state_init <= WRITE_REG;
402 next_state <= SI1;
403 -- Sx Interrupt Mask
404 when SI1 =>
405 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
406 par_data <= X"000A"; -- TIMEOUT, DISCON
407 state_init <= WRITE_REG;
408 next_state <= SI2;
409 when SI2 =>
410 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
411 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
412 state_init <= WRITE_REG;
413 next_state <= SI3;
414 when SI3 =>
415 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
416 par_data <= X"0001"; -- OPEN
417 state_init <= WRITE_REG;
418 next_state <= SI4;
419 when SI4 =>
420 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
421 state_init <= READ_REG;
422 next_state <= SI5;
423 when SI5 =>
424 if (data_read (7 downto 0) = X"13") then -- is open?
425 state_init <= SI6;
426 else
427 state_init <= SI4;
428 end if;
429 when SI6 =>
430 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
431 par_data <= X"0002"; -- LISTEN
432 state_init <= WRITE_REG;
433 socket_cnt <= socket_cnt + 1;
434 if (socket_cnt = 7) then
435 socket_cnt <= "000";
436 next_state <= ESTABLISH; -- All Sockets open
437 else
438 next_state <= SI; -- Next Socket
439 end if;
440 -- End Socket Init
441
442 when ESTABLISH =>
443 socks_waiting <= '1';
444 socks_connected <= '0';
445 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
446 state_init <= READ_REG;
447 next_state <= EST1;
448 when EST1 =>
449-- led <= data_read (7 downto 0);
450-- led <= X"00";
451 case data_read (7 downto 0) is
452 when X"17" => -- established
453 if (socket_cnt = 7) then
454 socket_cnt <= "000";
455 busy <= '0';
456 state_init <= MAIN;
457 else
458 socket_cnt <= socket_cnt + 1;
459 state_init <= ESTABLISH;
460 end if;
461 when others =>
462 state_init <= ESTABLISH;
463 end case;
464
465 when CONFIG =>
466-- led <= X"F0";
467 new_config <= '1';
468 if (config_started = '1') then
469-- led <= X"0F";
470 new_config <= '0';
471 state_init <= MAIN;
472 end if;
473
474 -- main "loop"
475 when MAIN =>
476 socks_waiting <= '0';
477 socks_connected <= '1';
478
479 ps_do_phase_shift <= '0';
480 ps_reset <= '0';
481 if (trigger_stop = '1') then
482 s_trigger <= '0';
483 end if;
484 data_valid_ack <= '0';
485 state_init <= MAIN1;
486 data_valid_int <= data_valid;
487 when MAIN1 =>
488 if (chk_recv_cntr = 1000) then
489 chk_recv_cntr <= 0;
490 state_read_data <= RD_1;
491 state_init <= READ_DATA;
492 busy <= '1';
493 else
494 chk_recv_cntr <= chk_recv_cntr + 1;
495 state_init <= MAIN2;
496 end if;
497 when MAIN2 =>
498 busy <= '0';
499 if (data_valid = '1') then
500 data_valid_int <= '0';
501 busy <= '1';
502 local_write_length <= write_length;
503 local_ram_start_addr <= ram_start_addr;
504 local_ram_addr <= (others => '0');
505 local_write_header_flag <= write_header_flag;
506 local_write_end_flag <= write_end_flag;
507 local_fifo_channels <= fifo_channels;
508-- data_valid_ack <= '1';
509-- next_state <= MAIN;
510-- state_init <= WRITE_DATA;
511 state_init <= MAIN3;
512 else
513 state_init <= MAIN1;
514 end if;
515 when MAIN3 =>
516-- led <= local_ram_start_addr (7 downto 0);
517 data_valid_ack <= '1';
518 next_state <= MAIN;
519 state_init <= WRITE_DATA;
520
521
522 -- read data from socket 0
523 when READ_DATA =>
524 case state_read_data is
525 when RD_1 =>
526 par_addr <= W5300_S0_RX_RSR;
527 state_init <= READ_REG;
528 next_state <= READ_DATA;
529 state_read_data <= RD_2;
530 when RD_2 =>
531 socket_rx_received (31 downto 16) <= data_read;
532 par_addr <= W5300_S0_RX_RSR + X"2";
533 state_init <= READ_REG;
534 next_state <= READ_DATA;
535 state_read_data <= RD_3;
536 when RD_3 =>
537 socket_rx_received (15 downto 0) <= data_read;
538 state_read_data <= RD_4;
539 when RD_4 =>
540 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
541 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
542 state_read_data <= RD_5;
543 else
544 busy <= '0';
545 state_init <= MAIN;
546 end if;
547 when RD_5 =>
548 if (rx_packets_cnt > 0) then
549 rx_packets_cnt <= rx_packets_cnt - '1';
550 par_addr <= W5300_S0_RX_FIFOR;
551 state_init <= READ_REG;
552 next_state <= READ_DATA;
553 state_read_data <= RD_6;
554 else
555 state_read_data <= RD_END;
556 end if;
557 when RD_6 =>
558-- led <= data_read (15 downto 8);
559 -- read command
560 if (next_packet_data = '0') then
561 case data_read (15 downto 8) is
562
563 when CMD_START => -- all data will be send via socket 0
564 socket_send_mode <= '1';
565 state_read_data <= RD_5;
566 when CMD_STOP => -- all data will be send via socket 1..7
567 socket_send_mode <= '0';
568 state_read_data <= RD_5;
569
570
571 when CMD_TRIGGER =>
572 trigger_stop <= '1';
573 s_trigger <= '1';
574 state_read_data <= RD_5;
575 when CMD_DWRITE_RUN =>
576 dwrite_enable <= '1';
577 state_read_data <= RD_5;
578 when CMD_DWRITE_STOP =>
579 dwrite_enable <= '0';
580 state_read_data <= RD_5;
581 when CMD_SCLK_ON =>
582 sclk_enable <= '1';
583 state_read_data <= RD_5;
584 when CMD_SCLK_OFF =>
585 sclk_enable <= '0';
586 state_read_data <= RD_5;
587 when CMD_DENABLE =>
588 denable <= '1';
589 state_read_data <= RD_5;
590 when CMD_DDISABLE =>
591 denable <= '0';
592 state_read_data <= RD_5;
593 when CMD_TRIGGER_C =>
594 trigger_stop <= '0';
595 s_trigger <= '1';
596 state_read_data <= RD_5;
597 when CMD_TRIGGER_S =>
598 trigger_stop <= '1';
599 state_read_data <= RD_5;
600 -- phase shift commands here:
601 when CMD_PS_DO =>
602 ps_do_phase_shift <= '1';
603 state_read_data <= RD_5;
604 when CMD_PS_DIRINC =>
605 ps_direction <= '1';
606 state_read_data <= RD_5;
607 when CMD_PS_RESET =>
608 ps_reset <= '1';
609 state_read_data <= RD_5;
610 when CMD_SRCLK_ON =>
611 srclk_enable <= '1';
612 state_read_data <= RD_5;
613 when CMD_SRCLK_OFF =>
614 srclk_enable <= '0';
615 state_read_data <= RD_5;
616 when CMD_PS_DIRDEC =>
617 ps_direction <= '0';
618 state_read_data <= RD_5;
619 when CMD_WRITE =>
620 next_packet_data <= '1';
621 config_addr <= data_read (7 downto 0);
622 state_read_data <= RD_5;
623 when others =>
624 state_read_data <= RD_5;
625 end case;
626 -- read data
627 else
628 if (config_busy = '0') then
629 config_data <= data_read;
630 config_wr_en <= '1';
631 new_config_flag <= '1';
632 next_packet_data <= '0';
633 state_read_data <= RD_WAIT;
634 end if;
635 end if;
636 when RD_WAIT =>
637 if (config_rw_ack = '1') then
638 state_read_data <= RD_WAIT1;
639 end if;
640 when RD_WAIT1 =>
641 if (config_rw_ready = '1') then
642 config_data <= (others => 'Z');
643 config_wr_en <= '0';
644 state_read_data <= RD_5;
645 end if;
646 when RD_END =>
647 par_addr <= W5300_S0_CR;
648 par_data <= X"0040"; -- RECV
649 state_init <= WRITE_REG;
650 if (new_config_flag = '1') then
651 new_config_flag <= '0';
652 next_state <= CONFIG;
653 else
654 next_state <= MAIN;
655 end if;
656
657 end case; -- state_data_read
658
659
660
661 when WRITE_DATA =>
662 case state_write is
663 when WR_START =>
664 if (local_write_header_flag = '1') then
665 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
666 end if;
667 state_write <= WR_WAIT1;
668 when WR_WAIT1 =>
669 state_write <= WR_LENGTH;
670 when WR_LENGTH =>
671 if (local_write_header_flag = '1') then
672 if (socket_send_mode = '1') then -- send via all sockets
673 local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3);
674 if (socket_nr_counter < 7) then
675 socket_nr_counter <= socket_nr_counter + 1;
676 else
677 socket_nr_counter <= 1;
678 end if;
679 else -- only send via socket 0\
680 local_socket_nr <= "000";
681 end if;
682 end if;
683 next_state_tmp <= next_state;
684 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
685 data_cnt <= 0;
686 state_write <= WR_01;
687 -- Check FIFO Size
688 when WR_01 =>
689 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
690 state_init <= READ_REG;
691 next_state <= WRITE_DATA;
692 state_write <= WR_02;
693 when WR_02 =>
694 socket_tx_free (31 downto 16) <= data_read;
695 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
696 state_init <= READ_REG;
697 next_state <= WRITE_DATA;
698 state_write <= WR_03;
699 when WR_03 =>
700 socket_tx_free (15 downto 0) <= data_read;
701 state_write <= WR_04;
702 when WR_04 =>
703
704-- led <= socket_tx_free (15 downto 8);
705
706-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
707 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
708 state_write <= WR_01;
709 else
710 if (local_write_header_flag = '1') then
711 state_write <= WR_FIFO;
712 else
713 state_write <= WR_ADC;
714 end if;
715 end if;
716
717 -- Fill FIFO
718
719 -- Write Header
720 when WR_FIFO =>
721 ram_addr <= local_ram_start_addr + local_ram_addr;
722 state_write <= WR_FIFO1;
723 when WR_FIFO1 =>
724 data_cnt <= data_cnt + 1;
725 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
726 local_ram_addr <= local_ram_addr + 1;
727 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
728 local_ram_addr <= local_ram_addr + 2;
729 end if;
730 if (data_cnt = 9) then -- skip empty words
731 local_ram_addr <= local_ram_addr + 4;
732 end if;
733 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
734 ram_access <= '1';
735 state_init <= WRITE_REG;
736 next_state <= WRITE_DATA;
737 state_write <= WR_FIFO;
738 else
739 state_write <= WR_ADC;
740 end if;
741 -- End Write Header
742
743 -- Write ADC-Data
744 ---- Start...
745 when WR_ADC =>
746 adc_data_addr <= local_ram_start_addr + local_ram_addr;
747 drs_cnt <= 0;
748 channel_cnt <= 1;
749 data_cnt <= 0;
750 roi_max <= (others => '0');
751 data_end <= 3;
752 state_write <= WR_ADC1;
753
754 ---- Write Channel
755 when WR_ADC1 =>
756 -- read ROI and set end of Channel-Data
757 if (data_cnt = 3) then
758 data_end <= conv_integer (ram_data) + 3;
759 if (ram_data > roi_max) then
760 roi_max <= ram_data (10 downto 0);
761 end if;
762 end if;
763 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
764 state_write <= WR_ADC2;
765 when WR_ADC2 =>
766 if (data_cnt < data_end) then
767 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
768 ram_access <= '1';
769 state_init <= WRITE_REG;
770 next_state <= WRITE_DATA;
771 data_cnt <= data_cnt + 1;
772 state_write <= WR_ADC1;
773 else
774 -- Next DRS
775 if (drs_cnt < 3) then
776 drs_cnt <= drs_cnt + 1;
777 data_cnt <= 0;
778 data_end <= 3;
779 state_write <= WR_ADC1;
780 else
781 -- Next Channel
782 if (channel_cnt < local_fifo_channels) then
783 channel_cnt <= channel_cnt + 1;
784 roi_max <= (others => '0');
785 drs_cnt <= 0;
786 data_cnt <= 0;
787 data_end <= 3;
788 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
789 state_write <= WR_ADC1;
790 else
791 -- Ready
792 if (local_write_end_flag = '1') then
793 state_write <= WR_ENDFLAG;
794 else
795 state_write <= WR_05;
796 end if;
797 end if;
798 end if;
799 end if;
800 -- End Write ADC-Data
801
802 -- Write End Package Flag
803 when WR_ENDFLAG =>
804 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
805 state_write <= WR_ENDFLAG1;
806 when WR_ENDFLAG1 =>
807 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
808 ram_access <= '1';
809 state_init <= WRITE_REG;
810 next_state <= WRITE_DATA;
811 state_write <= WR_ENDFLAG2;
812 when WR_ENDFLAG2 =>
813 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
814 state_write <= WR_ENDFLAG3;
815 when WR_ENDFLAG3 =>
816 state_init <= WRITE_REG;
817 next_state <= WRITE_DATA;
818 state_write <= WR_05a;
819
820 -- End Write End Package Flag
821
822 -- Wait????
823 when WR_05a =>
824 if (wait_cntr < 10) then -- 3000 works???
825 wait_cntr <= wait_cntr + 1;
826 else
827 wait_cntr <= 0;
828 state_write <= WR_05b;
829 end if;
830 when WR_05b =>
831 state_write <= WR_05;
832
833 --Send FIFO
834 when WR_05 =>
835 ram_access <= '0';
836 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
837 par_data <= (0 => write_length_bytes (16), others => '0');
838 state_init <= WRITE_REG;
839 state_write <= WR_06;
840 when WR_06 =>
841 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
842 par_data <= write_length_bytes (15 downto 0);
843 state_init <= WRITE_REG;
844 state_write <= WR_07;
845 when WR_07 =>
846 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
847 par_data <= X"0020"; -- Send
848 state_init <= WRITE_REG;
849 state_write <= WR_08;
850 when others =>
851 state_init <= next_state_tmp;
852 state_write <= WR_START;
853 end case;
854 -- End WRITE_DATA
855
856 when READ_REG =>
857 case count is
858 when "000" =>
859 cs <= '0';
860 rd <= '0';
861 wr <= '1';
862 data <= (others => 'Z'); -- !!!!!!!!!!
863 count <= "001";
864 addr <= par_addr;
865 when "001" =>
866 count <= "010";
867 when "010" =>
868 count <= "100";
869 when "100" =>
870 data_read <= data;
871 count <= "110";
872 when "110" =>
873 count <= "111";
874 when "111" =>
875 cs <= '1';
876 rd <= '1';
877 count <= "000";
878 state_init <= next_state;
879 when others =>
880 null;
881 end case;
882
883 when WRITE_REG =>
884 case count is
885 when "000" =>
886 cs <= '0';
887 wr <= '0';
888 rd <= '1';
889 addr <= par_addr;
890 if (ram_access = '1') then
891 data <= ram_data;
892 else
893 data <= par_data;
894 end if;
895 count <= "100";
896 when "100" =>
897 count <= "101";
898 when "101" =>
899 count <= "110";
900 when "110" =>
901 cs <= '1';
902 wr <= '1';
903 state_init <= next_state;
904 count <= "000";
905 when others =>
906 null;
907 end case;
908
909 when others =>
910 null;
911 end case;
912 end if; -- int_flag = '0'
913
914 end if; -- rising_edge (clk)
915
916 end process w5300_init_proc;
917
918end Behavioral;
919
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